[][openwrt][switch][ARHT][update switch app to v1.0.7]
[Description]
Add below modification:
1). align switch app version to v1.0.7 with ARHT
2). fixed check_patch errors as much as possible in switch app
3). get_chip_name() directly return AN8855 to prevent 0x1f register
from being overwritten by reg_read
4). correct some files from Windos(CRLF) to UNIX(LF)
[Release-log]
N/A
Change-Id: I4913c8124ded81cffe0493748c0347fdb1fbb22f
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/9453546
diff --git a/feed/app/switch/src/switch_ioctl.h b/feed/app/switch/src/switch_ioctl.h
index dffe9c7..3ee43d7 100644
--- a/feed/app/switch/src/switch_ioctl.h
+++ b/feed/app/switch/src/switch_ioctl.h
@@ -8,48 +8,43 @@
#define ETH_DEVNAME "eth0"
#define BR_DEVNAME "br-lan"
-#define RAETH_MII_READ 0x89F3
-#define RAETH_MII_WRITE 0x89F4
-#define RAETH_ESW_PHY_DUMP 0x89F7
+#define RAETH_MII_READ 0x89F3
+#define RAETH_MII_WRITE 0x89F4
+#define RAETH_ESW_PHY_DUMP 0x89F7
struct esw_reg {
- unsigned int off;
- unsigned int val;
+ unsigned int off;
+ unsigned int val;
};
struct ra_mii_ioctl_data {
- __u16 phy_id;
- __u16 reg_num;
- __u32 val_in;
- __u32 val_out;
-/*
- __u32 port_num;
- __u32 dev_addr;
- __u32 reg_addr;
-*/
+ __u16 phy_id;
+ __u16 reg_num;
+ __u32 val_in;
+ __u32 val_out;
};
struct ra_switch_ioctl_data {
- unsigned int cmd;
- unsigned int on_off;
- unsigned int port;
- unsigned int bw;
- unsigned int vid;
- unsigned int fid;
- unsigned int port_map;
- unsigned int rx_port_map;
- unsigned int tx_port_map;
- unsigned int igmp_query_interval;
- unsigned int reg_addr;
- unsigned int reg_val;
- unsigned int mode;
- unsigned int qos_queue_num;
- unsigned int qos_type;
- unsigned int qos_pri;
- unsigned int qos_dscp;
- unsigned int qos_table_idx;
- unsigned int qos_weight;
- unsigned char mac[6];
+ unsigned int cmd;
+ unsigned int on_off;
+ unsigned int port;
+ unsigned int bw;
+ unsigned int vid;
+ unsigned int fid;
+ unsigned int port_map;
+ unsigned int rx_port_map;
+ unsigned int tx_port_map;
+ unsigned int igmp_query_interval;
+ unsigned int reg_addr;
+ unsigned int reg_val;
+ unsigned int mode;
+ unsigned int qos_queue_num;
+ unsigned int qos_type;
+ unsigned int qos_pri;
+ unsigned int qos_dscp;
+ unsigned int qos_table_idx;
+ unsigned int qos_weight;
+ unsigned char mac[6];
};
extern int chip_name;
@@ -60,11 +55,11 @@
int reg_write_ioctl(unsigned int offset, unsigned int value);
int phy_dump_ioctl(unsigned int phy_addr);
int mii_mgr_cl22_read_ioctl(unsigned int port_num, unsigned int reg,
- unsigned int *value);
+ unsigned int *value);
int mii_mgr_cl22_write_ioctl(unsigned int port_num, unsigned int reg,
- unsigned int value);
+ unsigned int value);
int mii_mgr_cl45_read_ioctl(unsigned int port_num, unsigned int dev,
- unsigned int reg, unsigned int *value);
+ unsigned int reg, unsigned int *value);
int mii_mgr_cl45_write_ioctl(unsigned int port_num, unsigned int dev,
- unsigned int reg, unsigned int value);
+ unsigned int reg, unsigned int value);
#endif