developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 1 | diff --git a/drivers/net/ethernet/mediatek/Makefile b/drivers/net/ethernet/mediatek/Makefile |
| 2 | index 0c724a5..93cd55f 100644 |
| 3 | --- a/drivers/net/ethernet/mediatek/Makefile |
| 4 | +++ b/drivers/net/ethernet/mediatek/Makefile |
| 5 | @@ -5,7 +5,7 @@ |
| 6 | |
| 7 | obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o |
developer | 6883854 | 2022-10-03 23:42:21 +0800 | [diff] [blame] | 8 | mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_usxgmii.o mtk_eth_path.o mtk_eth_dbg.o mtk_eth_reset.o \ |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 9 | - mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o |
| 10 | + mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o mtk_qdma_debugfs.o |
| 11 | mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o |
| 12 | ifdef CONFIG_DEBUG_FS |
| 13 | mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o |
| 14 | diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c |
developer | 1fb19c9 | 2023-03-07 23:45:23 +0800 | [diff] [blame] | 15 | index ca76047..809c735 100644 |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 16 | --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c |
| 17 | +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c |
developer | 1fb19c9 | 2023-03-07 23:45:23 +0800 | [diff] [blame] | 18 | @@ -4787,6 +4787,8 @@ static int mtk_probe(struct platform_device *pdev) |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 19 | } |
| 20 | |
| 21 | mtk_ppe_debugfs_init(eth); |
| 22 | + |
| 23 | + mtk_qdma_debugfs_init(eth); |
| 24 | } |
| 25 | |
| 26 | for (i = 0; i < MTK_MAX_DEVS; i++) { |
developer | 1fb19c9 | 2023-03-07 23:45:23 +0800 | [diff] [blame] | 27 | @@ -4901,6 +4903,7 @@ static const struct mtk_soc_data mt2701_data = { |
| 28 | .rx_dma_l4_valid = RX_DMA_L4_VALID, |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 29 | .dma_max_len = MTK_TX_DMA_BUF_LEN, |
| 30 | .dma_len_offset = MTK_TX_DMA_BUF_SHIFT, |
| 31 | + .qdma_tx_sch = 2, |
| 32 | }, |
| 33 | }; |
| 34 | |
developer | 1fb19c9 | 2023-03-07 23:45:23 +0800 | [diff] [blame] | 35 | @@ -4920,6 +4923,7 @@ static const struct mtk_soc_data mt7621_data = { |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 36 | .rxd_size = sizeof(struct mtk_rx_dma), |
| 37 | .dma_max_len = MTK_TX_DMA_BUF_LEN, |
| 38 | .dma_len_offset = MTK_TX_DMA_BUF_SHIFT, |
| 39 | + .qdma_tx_sch = 2, |
| 40 | }, |
| 41 | }; |
| 42 | |
developer | 1fb19c9 | 2023-03-07 23:45:23 +0800 | [diff] [blame] | 43 | @@ -4940,6 +4944,7 @@ static const struct mtk_soc_data mt7622_data = { |
| 44 | .rx_dma_l4_valid = RX_DMA_L4_VALID, |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 45 | .dma_max_len = MTK_TX_DMA_BUF_LEN, |
| 46 | .dma_len_offset = MTK_TX_DMA_BUF_SHIFT, |
| 47 | + .qdma_tx_sch = 2, |
| 48 | }, |
| 49 | }; |
| 50 | |
developer | 1fb19c9 | 2023-03-07 23:45:23 +0800 | [diff] [blame] | 51 | @@ -4959,6 +4964,7 @@ static const struct mtk_soc_data mt7623_data = { |
| 52 | .rx_dma_l4_valid = RX_DMA_L4_VALID, |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 53 | .dma_max_len = MTK_TX_DMA_BUF_LEN, |
| 54 | .dma_len_offset = MTK_TX_DMA_BUF_SHIFT, |
| 55 | + .qdma_tx_sch = 2, |
| 56 | }, |
| 57 | }; |
| 58 | |
developer | 1fb19c9 | 2023-03-07 23:45:23 +0800 | [diff] [blame] | 59 | @@ -4997,6 +5003,7 @@ static const struct mtk_soc_data mt7986_data = { |
| 60 | .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 61 | .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, |
| 62 | .dma_len_offset = MTK_TX_DMA_BUF_SHIFT_V2, |
| 63 | + .qdma_tx_sch = 4, |
| 64 | }, |
| 65 | }; |
| 66 | |
developer | 1fb19c9 | 2023-03-07 23:45:23 +0800 | [diff] [blame] | 67 | @@ -5017,6 +5024,7 @@ static const struct mtk_soc_data mt7981_data = { |
| 68 | .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 69 | .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, |
| 70 | .dma_len_offset = MTK_TX_DMA_BUF_SHIFT_V2, |
| 71 | + .qdma_tx_sch = 4, |
| 72 | }, |
| 73 | }; |
| 74 | |
developer | 1fb19c9 | 2023-03-07 23:45:23 +0800 | [diff] [blame] | 75 | @@ -5034,6 +5042,7 @@ static const struct mtk_soc_data mt7988_data = { |
| 76 | .rx_dma_l4_valid = RX_DMA_L4_VALID_V2, |
| 77 | .dma_max_len = MTK_TX_DMA_BUF_LEN_V2, |
| 78 | .dma_len_offset = MTK_TX_DMA_BUF_SHIFT_V2, |
| 79 | + .qdma_tx_sch = 4, |
| 80 | }, |
| 81 | }; |
| 82 | |
| 83 | @@ -5051,6 +5060,7 @@ static const struct mtk_soc_data rt5350_data = { |
| 84 | .rx_dma_l4_valid = RX_DMA_L4_VALID_PDMA, |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 85 | .dma_max_len = MTK_TX_DMA_BUF_LEN, |
| 86 | .dma_len_offset = MTK_TX_DMA_BUF_SHIFT, |
| 87 | + .qdma_tx_sch = 4, |
| 88 | }, |
| 89 | }; |
| 90 | |
| 91 | diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h |
developer | 1fb19c9 | 2023-03-07 23:45:23 +0800 | [diff] [blame] | 92 | index c6afff5..bd73c27 100644 |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 93 | --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h |
| 94 | +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h |
developer | 1fb19c9 | 2023-03-07 23:45:23 +0800 | [diff] [blame] | 95 | @@ -385,10 +385,21 @@ |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 96 | |
| 97 | /* QDMA TX Queue Configuration Registers */ |
| 98 | #define MTK_QTX_CFG(x) (QDMA_BASE + (x * 0x10)) |
| 99 | +#define MTK_QTX_CFG_HW_RESV_CNT_OFFSET GENMASK(15, 8) |
| 100 | +#define MTK_QTX_CFG_SW_RESV_CNT_OFFSET GENMASK(7, 0) |
| 101 | #define QDMA_RES_THRES 4 |
| 102 | |
| 103 | /* QDMA TX Queue Scheduler Registers */ |
| 104 | #define MTK_QTX_SCH(x) (QDMA_BASE + 4 + (x * 0x10)) |
| 105 | +#define MTK_QTX_SCH_TX_SCH_SEL BIT(31) |
| 106 | +#define MTK_QTX_SCH_TX_SCH_SEL_V2 GENMASK(31, 30) |
| 107 | +#define MTK_QTX_SCH_MIN_RATE_EN BIT(27) |
| 108 | +#define MTK_QTX_SCH_MIN_RATE_MAN GENMASK(26, 20) |
| 109 | +#define MTK_QTX_SCH_MIN_RATE_EXP GENMASK(19, 16) |
| 110 | +#define MTK_QTX_SCH_MAX_RATE_WGHT GENMASK(15, 12) |
| 111 | +#define MTK_QTX_SCH_MAX_RATE_EN BIT(11) |
| 112 | +#define MTK_QTX_SCH_MAX_RATE_MAN GENMASK(10, 4) |
| 113 | +#define MTK_QTX_SCH_MAX_RATE_EXP GENMASK(3, 0) |
| 114 | |
| 115 | /* QDMA RX Base Pointer Register */ |
| 116 | #define MTK_QRX_BASE_PTR0 (QDMA_BASE + 0x100) |
developer | 1fb19c9 | 2023-03-07 23:45:23 +0800 | [diff] [blame] | 117 | @@ -406,7 +417,9 @@ |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 118 | #define MTK_QRX_DRX_IDX0 (QDMA_BASE + 0x10c) |
| 119 | |
| 120 | /* QDMA Page Configuration Register */ |
| 121 | -#define MTK_QDMA_PAGE (QDMA_BASE + 0x1f0) |
| 122 | +#define MTK_QDMA_PAGE (QDMA_BASE + 0x1f0) |
| 123 | +#define MTK_QTX_CFG_PAGE GENMASK(3, 0) |
| 124 | +#define MTK_QTX_PER_PAGE (16) |
| 125 | |
| 126 | /* QDMA Global Configuration Register */ |
| 127 | #define MTK_QDMA_GLO_CFG (QDMA_BASE + 0x204) |
developer | 1fb19c9 | 2023-03-07 23:45:23 +0800 | [diff] [blame] | 128 | @@ -443,6 +456,9 @@ |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 129 | #define FC_THRES_DROP_EN (7 << 16) |
| 130 | #define FC_THRES_MIN 0x4444 |
| 131 | |
| 132 | +/* QDMA TX Scheduler Rate Control Register */ |
| 133 | +#define MTK_QDMA_TX_2SCH_BASE (QDMA_BASE + 0x214) |
| 134 | + |
| 135 | /* QDMA Interrupt Status Register */ |
| 136 | #define MTK_QDMA_INT_STATUS (QDMA_BASE + 0x218) |
developer | 1fb19c9 | 2023-03-07 23:45:23 +0800 | [diff] [blame] | 137 | #if defined(CONFIG_MEDIATEK_NETSYS_V2) || defined(CONFIG_MEDIATEK_NETSYS_V3) |
| 138 | @@ -478,6 +494,11 @@ |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 139 | /* QDMA Interrupt Mask Register */ |
| 140 | #define MTK_QDMA_HRED2 (QDMA_BASE + 0x244) |
| 141 | |
| 142 | +/* QDMA TX Queue MIB Interface Register */ |
| 143 | +#define MTK_QTX_MIB_IF (QDMA_BASE + 0x2bc) |
| 144 | +#define MTK_MIB_ON_QTX_CFG BIT(31) |
| 145 | +#define MTK_VQTX_MIB_EN BIT(28) |
| 146 | + |
| 147 | /* QDMA TX Forward CPU Pointer Register */ |
| 148 | #define MTK_QTX_CTX_PTR (QDMA_BASE +0x300) |
| 149 | |
developer | 1fb19c9 | 2023-03-07 23:45:23 +0800 | [diff] [blame] | 150 | @@ -505,6 +526,14 @@ |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 151 | /* QDMA FQ Free Page Buffer Length Register */ |
| 152 | #define MTK_QDMA_FQ_BLEN (QDMA_BASE +0x32c) |
| 153 | |
| 154 | +/* QDMA TX Scheduler Rate Control Register */ |
| 155 | +#define MTK_QDMA_TX_4SCH_BASE(x) (QDMA_BASE + 0x398 + (((x) >> 1) * 0x4)) |
| 156 | +#define MTK_QDMA_TX_SCH_MASK GENMASK(15, 0) |
| 157 | +#define MTK_QDMA_TX_SCH_MAX_WFQ BIT(15) |
| 158 | +#define MTK_QDMA_TX_SCH_RATE_EN BIT(11) |
| 159 | +#define MTK_QDMA_TX_SCH_RATE_MAN GENMASK(10, 4) |
| 160 | +#define MTK_QDMA_TX_SCH_RATE_EXP GENMASK(3, 0) |
| 161 | + |
| 162 | /* WDMA Registers */ |
developer | 1fb19c9 | 2023-03-07 23:45:23 +0800 | [diff] [blame] | 163 | #define MTK_WDMA_CTX_PTR(x) (WDMA_BASE(x) + 0x8) |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 164 | #define MTK_WDMA_DTX_PTR(x) (WDMA_BASE(x) + 0xC) |
developer | 1fb19c9 | 2023-03-07 23:45:23 +0800 | [diff] [blame] | 165 | @@ -1596,6 +1625,7 @@ struct mtk_soc_data { |
| 166 | u32 rx_dma_l4_valid; |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 167 | u32 dma_max_len; |
| 168 | u32 dma_len_offset; |
| 169 | + u32 qdma_tx_sch; |
| 170 | } txrx; |
| 171 | }; |
| 172 | |
developer | 1fb19c9 | 2023-03-07 23:45:23 +0800 | [diff] [blame] | 173 | @@ -1736,6 +1766,7 @@ struct mtk_eth { |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 174 | spinlock_t syscfg0_lock; |
| 175 | struct timer_list mtk_dma_monitor_timer; |
| 176 | |
developer | 0a32014 | 2022-09-21 23:18:01 +0800 | [diff] [blame] | 177 | + u8 qos_toggle; |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 178 | u8 ppe_num; |
| 179 | struct mtk_ppe *ppe[MTK_MAX_PPE_NUM]; |
| 180 | struct rhashtable flow_table; |
developer | 1fb19c9 | 2023-03-07 23:45:23 +0800 | [diff] [blame] | 181 | @@ -1815,4 +1846,6 @@ int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type, |
| 182 | void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev); |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 183 | |
| 184 | int mtk_ppe_debugfs_init(struct mtk_eth *eth); |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 185 | + |
developer | 1fb19c9 | 2023-03-07 23:45:23 +0800 | [diff] [blame] | 186 | +int mtk_qdma_debugfs_init(struct mtk_eth *eth); |
| 187 | #endif /* MTK_ETH_H */ |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 188 | diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.c b/drivers/net/ethernet/mediatek/mtk_ppe.c |
| 189 | index a49275f..1767823 100755 |
| 190 | --- a/drivers/net/ethernet/mediatek/mtk_ppe.c |
| 191 | +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c |
| 192 | @@ -406,6 +406,16 @@ int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq, |
| 193 | return 0; |
| 194 | } |
| 195 | |
| 196 | +int mtk_foe_entry_set_qid(struct mtk_foe_entry *entry, int qid) |
| 197 | +{ |
| 198 | + u32 *ib2 = mtk_foe_entry_ib2(entry); |
| 199 | + |
| 200 | + *ib2 &= ~MTK_FOE_IB2_QID; |
| 201 | + *ib2 |= FIELD_PREP(MTK_FOE_IB2_QID, qid); |
| 202 | + *ib2 |= MTK_FOE_IB2_PSE_QOS; |
| 203 | + |
| 204 | + return 0; |
| 205 | +} |
| 206 | static inline bool mtk_foe_entry_usable(struct mtk_foe_entry *entry) |
| 207 | { |
| 208 | return !(entry->ib1 & MTK_FOE_IB1_STATIC) && |
| 209 | diff --git a/drivers/net/ethernet/mediatek/mtk_ppe.h b/drivers/net/ethernet/mediatek/mtk_ppe.h |
| 210 | index 8076e5d..c46c4d9 100644 |
| 211 | --- a/drivers/net/ethernet/mediatek/mtk_ppe.h |
| 212 | +++ b/drivers/net/ethernet/mediatek/mtk_ppe.h |
| 213 | @@ -356,6 +356,7 @@ int mtk_foe_entry_set_vlan(struct mtk_foe_entry *entry, int vid); |
| 214 | int mtk_foe_entry_set_pppoe(struct mtk_foe_entry *entry, int sid); |
| 215 | int mtk_foe_entry_set_wdma(struct mtk_foe_entry *entry, int wdma_idx, int txq, |
| 216 | int bss, int wcid); |
| 217 | +int mtk_foe_entry_set_qid(struct mtk_foe_entry *entry, int qid); |
| 218 | int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_flow_entry *entry); |
| 219 | void mtk_foe_entry_clear(struct mtk_ppe *ppe, struct mtk_flow_entry *entry); |
| 220 | int mtk_foe_entry_idle_time(struct mtk_ppe *ppe, struct mtk_flow_entry *entry); |
| 221 | diff --git a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c |
| 222 | index f258539..3b17819 100755 |
| 223 | --- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c |
| 224 | +++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c |
developer | 0a32014 | 2022-09-21 23:18:01 +0800 | [diff] [blame] | 225 | @@ -9,6 +9,8 @@ |
| 226 | #include <linux/ipv6.h> |
| 227 | #include <net/flow_offload.h> |
| 228 | #include <net/pkt_cls.h> |
| 229 | +#include <net/netfilter/nf_conntrack.h> |
| 230 | +#include <net/netfilter/nf_flow_table.h> |
| 231 | #include <net/dsa.h> |
| 232 | #include "mtk_eth_soc.h" |
| 233 | #include "mtk_wed.h" |
| 234 | @@ -183,7 +185,7 @@ mtk_flow_get_dsa_port(struct net_device **dev) |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 235 | |
developer | 0a32014 | 2022-09-21 23:18:01 +0800 | [diff] [blame] | 236 | static int |
| 237 | mtk_flow_set_output_device(struct mtk_eth *eth, struct mtk_foe_entry *foe, |
| 238 | - struct net_device *dev, const u8 *dest_mac, |
| 239 | + struct net_device *dev, struct nf_conn *ct, const u8 *dest_mac, |
| 240 | int *wed_index) |
| 241 | { |
| 242 | struct mtk_wdma_info info = {}; |
| 243 | @@ -211,6 +211,11 @@ mtk_flow_set_output_device(struct mtk_eth *eth, struct mtk_foe_entry *foe, |
| 244 | if (dsa_port >= 0) |
| 245 | mtk_foe_entry_set_dsa(foe, dsa_port); |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 246 | |
developer | 0a32014 | 2022-09-21 23:18:01 +0800 | [diff] [blame] | 247 | + if (eth->qos_toggle == 1 || ct->mark >= 6) |
| 248 | + mtk_foe_entry_set_qid(foe, ct->mark & MTK_QDMA_TX_MASK); |
| 249 | + if (eth->qos_toggle == 2 && dsa_port >= 0) |
| 250 | + mtk_foe_entry_set_qid(foe, dsa_port & MTK_QDMA_TX_MASK); |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 251 | + |
| 252 | if (dev == eth->netdev[0]) |
developer | c693c15 | 2022-12-02 09:38:46 +0800 | [diff] [blame] | 253 | pse_port = PSE_GDM1_PORT; |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 254 | else if (dev == eth->netdev[1]) |
developer | 0a32014 | 2022-09-21 23:18:01 +0800 | [diff] [blame] | 255 | @@ -433,7 +443,7 @@ mtk_flow_offload_replace(struct mtk_eth *eth, struct flow_cls_offload *f) |
| 256 | if (data.pppoe.num == 1) |
| 257 | mtk_foe_entry_set_pppoe(&foe, data.pppoe.sid); |
| 258 | |
| 259 | - err = mtk_flow_set_output_device(eth, &foe, odev, data.eth.h_dest, |
| 260 | + err = mtk_flow_set_output_device(eth, &foe, odev, f->flow->ct, data.eth.h_dest, |
| 261 | &wed_index); |
| 262 | if (err) |
| 263 | return err; |
| 264 | diff --git a/include/net/flow_offload.h b/include/net/flow_offload.h |
| 265 | index 59b8736..7261b6d 100644 |
| 266 | --- a/include/net/flow_offload.h |
| 267 | +++ b/include/net/flow_offload.h |
| 268 | @@ -365,6 +378,7 @@ struct flow_cls_offload { |
| 269 | struct flow_cls_common_offload common; |
| 270 | enum flow_cls_command command; |
| 271 | unsigned long cookie; |
| 272 | + struct flow_offload *flow; |
| 273 | struct flow_rule *rule; |
| 274 | struct flow_stats stats; |
| 275 | u32 classid; |
| 276 | diff --git a/net/netfilter/nf_flow_table_offload.c b/net/netfilter/nf_flow_table_offload.c |
| 277 | index d94c6fb..886ced5 100644 |
| 278 | --- a/net/netfilter/nf_flow_table_offload.c |
| 279 | +++ b/net/netfilter/nf_flow_table_offload.c |
| 280 | @@ -810,11 +810,13 @@ static int nf_flow_offload_alloc(const struct flow_offload_work *offload, |
| 281 | } |
| 282 | |
| 283 | static void nf_flow_offload_init(struct flow_cls_offload *cls_flow, |
| 284 | + struct flow_offload *flow, |
| 285 | __be16 proto, int priority, |
| 286 | enum flow_cls_command cmd, |
| 287 | const struct flow_offload_tuple *tuple, |
| 288 | struct netlink_ext_ack *extack) |
| 289 | { |
| 290 | + cls_flow->flow = flow; |
| 291 | cls_flow->common.protocol = proto; |
| 292 | cls_flow->common.prio = priority; |
| 293 | cls_flow->common.extack = extack; |
| 294 | @@ -836,7 +838,7 @@ static int nf_flow_offload_tuple(struct nf_flowtable *flowtable, |
| 295 | __be16 proto = ETH_P_ALL; |
| 296 | int err, i = 0; |
| 297 | |
| 298 | - nf_flow_offload_init(&cls_flow, proto, priority, cmd, |
| 299 | + nf_flow_offload_init(&cls_flow, flow, proto, priority, cmd, |
| 300 | &flow->tuplehash[dir].tuple, &extack); |
| 301 | if (cmd == FLOW_CLS_REPLACE) |
| 302 | cls_flow.rule = flow_rule->rule; |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 303 | diff --git a/drivers/net/ethernet/mediatek/mtk_qdma_debugfs.c b/drivers/net/ethernet/mediatek/mtk_qdma_debugfs.c |
| 304 | new file mode 100644 |
| 305 | index 0000000..198b924 |
| 306 | --- /dev/null |
| 307 | +++ b/drivers/net/ethernet/mediatek/mtk_qdma_debugfs.c |
developer | c66b215 | 2023-01-11 15:20:04 +0800 | [diff] [blame] | 308 | @@ -0,0 +1,435 @@ |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 309 | +/* SPDX-License-Identifier: GPL-2.0 |
| 310 | + * |
| 311 | + * Copyright (c) 2022 MediaTek Inc. |
| 312 | + * Author: Henry Yen <henry.yen@mediatek.com> |
| 313 | + * Bo-Cun Chen <bc-bocun.chen@mediatek.com> |
| 314 | + */ |
| 315 | + |
| 316 | +#include <linux/kernel.h> |
| 317 | +#include <linux/debugfs.h> |
| 318 | +#include "mtk_eth_soc.h" |
| 319 | + |
| 320 | +#define MAX_PPPQ_PORT_NUM 6 |
| 321 | + |
| 322 | +static struct mtk_eth *_eth; |
| 323 | + |
| 324 | +static void mtk_qdma_qos_shaper_ebl(struct mtk_eth *eth, u32 id, u32 enable) |
| 325 | +{ |
| 326 | + u32 val; |
| 327 | + |
| 328 | + if (enable) { |
| 329 | + val = MTK_QTX_SCH_MIN_RATE_EN | MTK_QTX_SCH_MAX_RATE_EN; |
| 330 | + val |= FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) | |
| 331 | + FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) | |
| 332 | + FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, 25) | |
| 333 | + FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, 5) | |
| 334 | + FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WGHT, 4); |
| 335 | + |
| 336 | + writel(val, eth->base + MTK_QTX_SCH(id % MTK_QTX_PER_PAGE)); |
| 337 | + } else { |
| 338 | + writel(0, eth->base + MTK_QTX_SCH(id % MTK_QTX_PER_PAGE)); |
| 339 | + } |
| 340 | +} |
| 341 | + |
| 342 | +static void mtk_qdma_qos_disable(struct mtk_eth *eth) |
| 343 | +{ |
| 344 | + u32 id, val; |
| 345 | + |
| 346 | + for (id = 0; id < MAX_PPPQ_PORT_NUM; id++) { |
| 347 | + mtk_qdma_qos_shaper_ebl(eth, id, 0); |
| 348 | + |
| 349 | + writel(FIELD_PREP(MTK_QTX_CFG_HW_RESV_CNT_OFFSET, 4) | |
| 350 | + FIELD_PREP(MTK_QTX_CFG_SW_RESV_CNT_OFFSET, 4), |
| 351 | + eth->base + MTK_QTX_CFG(id % MTK_QTX_PER_PAGE)); |
| 352 | + } |
| 353 | + |
| 354 | + val = (MTK_QDMA_TX_SCH_MAX_WFQ) | (MTK_QDMA_TX_SCH_MAX_WFQ << 16); |
| 355 | + for (id = 0; id < eth->soc->txrx.qdma_tx_sch; id += 2) { |
| 356 | + if (eth->soc->txrx.qdma_tx_sch == 4) |
| 357 | + writel(val, eth->base + MTK_QDMA_TX_4SCH_BASE(id)); |
| 358 | + else |
| 359 | + writel(val, eth->base + MTK_QDMA_TX_2SCH_BASE); |
| 360 | + } |
| 361 | +} |
| 362 | + |
| 363 | +static void mtk_qdma_qos_pppq_enable(struct mtk_eth *eth) |
| 364 | +{ |
| 365 | + u32 id, val; |
| 366 | + |
| 367 | + for (id = 0; id < MAX_PPPQ_PORT_NUM; id++) { |
| 368 | + mtk_qdma_qos_shaper_ebl(eth, id, 1); |
| 369 | + |
| 370 | + writel(FIELD_PREP(MTK_QTX_CFG_HW_RESV_CNT_OFFSET, 4) | |
| 371 | + FIELD_PREP(MTK_QTX_CFG_SW_RESV_CNT_OFFSET, 4), |
| 372 | + eth->base + MTK_QTX_CFG(id % MTK_QTX_PER_PAGE)); |
| 373 | + } |
| 374 | + |
| 375 | + val = (MTK_QDMA_TX_SCH_MAX_WFQ) | (MTK_QDMA_TX_SCH_MAX_WFQ << 16); |
| 376 | + for (id = 0; id < eth->soc->txrx.qdma_tx_sch; id+= 2) { |
| 377 | + if (eth->soc->txrx.qdma_tx_sch == 4) |
| 378 | + writel(val, eth->base + MTK_QDMA_TX_4SCH_BASE(id)); |
| 379 | + else |
| 380 | + writel(val, eth->base + MTK_QDMA_TX_2SCH_BASE); |
| 381 | + } |
| 382 | +} |
| 383 | + |
| 384 | + static ssize_t mtk_qmda_debugfs_write_qos(struct file *file, const char __user *buffer, |
| 385 | + size_t count, loff_t *data) |
| 386 | +{ |
| 387 | + struct seq_file *m = file->private_data; |
| 388 | + struct mtk_eth *eth = m->private; |
| 389 | + char buf[8]; |
| 390 | + int len = count; |
| 391 | + |
| 392 | + if ((len > 8) || copy_from_user(buf, buffer, len)) |
| 393 | + return -EFAULT; |
| 394 | + |
| 395 | + if (buf[0] == '0') { |
| 396 | + pr_info("HQoS is going to be disabled !\n"); |
developer | 0a32014 | 2022-09-21 23:18:01 +0800 | [diff] [blame] | 397 | + eth->qos_toggle = 0; |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 398 | + mtk_qdma_qos_disable(eth); |
| 399 | + } else if (buf[0] == '1') { |
| 400 | + pr_info("HQoS mode is going to be enabled !\n"); |
developer | 0a32014 | 2022-09-21 23:18:01 +0800 | [diff] [blame] | 401 | + eth->qos_toggle = 1; |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 402 | + } else if (buf[0] == '2') { |
| 403 | + pr_info("Per-port-per-queue mode is going to be enabled !\n"); |
| 404 | + pr_info("PPPQ use qid 0~5 (scheduler 0).\n"); |
developer | 0a32014 | 2022-09-21 23:18:01 +0800 | [diff] [blame] | 405 | + eth->qos_toggle = 2; |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 406 | + mtk_qdma_qos_pppq_enable(eth); |
| 407 | + } |
| 408 | + |
| 409 | + return len; |
| 410 | +} |
| 411 | + |
| 412 | +static int mtk_qmda_debugfs_read_qos(struct seq_file *m, void *private) |
| 413 | +{ |
| 414 | + struct mtk_eth *eth = m->private; |
| 415 | + |
| 416 | + seq_printf(m, "value=%d, HQoS is %s now!\n", |
developer | 0a32014 | 2022-09-21 23:18:01 +0800 | [diff] [blame] | 417 | + eth->qos_toggle, (eth->qos_toggle) ? "enabled" : "disabled"); |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 418 | + |
| 419 | + return 0; |
| 420 | +} |
| 421 | + |
| 422 | +static int mtk_qmda_debugfs_open_qos(struct inode *inode, struct file *file) |
| 423 | +{ |
| 424 | + return single_open(file, mtk_qmda_debugfs_read_qos, |
| 425 | + inode->i_private); |
| 426 | +} |
| 427 | + |
| 428 | +static ssize_t mtk_qmda_debugfs_read_qos_sched(struct file *file, char __user *user_buf, |
| 429 | + size_t count, loff_t *ppos) |
| 430 | +{ |
| 431 | + struct mtk_eth *eth = _eth; |
| 432 | + long id = (long)file->private_data; |
| 433 | + char *buf; |
| 434 | + unsigned int len = 0, buf_len = 1500; |
developer | c66b215 | 2023-01-11 15:20:04 +0800 | [diff] [blame] | 435 | + int enable, scheduling, max_rate, exp, scheduler, i; |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 436 | + ssize_t ret_cnt; |
| 437 | + u32 val; |
| 438 | + |
| 439 | + buf = kzalloc(buf_len, GFP_KERNEL); |
| 440 | + if (!buf) |
| 441 | + return -ENOMEM; |
| 442 | + |
| 443 | + if (eth->soc->txrx.qdma_tx_sch == 4) |
| 444 | + val = readl(eth->base + MTK_QDMA_TX_4SCH_BASE(id)); |
| 445 | + else |
| 446 | + val = readl(eth->base + MTK_QDMA_TX_2SCH_BASE); |
| 447 | + |
| 448 | + if (id & 0x1) |
| 449 | + val >>= 16; |
| 450 | + |
developer | c66b215 | 2023-01-11 15:20:04 +0800 | [diff] [blame] | 451 | + val &= MTK_QDMA_TX_SCH_MASK; |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 452 | + enable = FIELD_GET(MTK_QDMA_TX_SCH_RATE_EN, val); |
| 453 | + scheduling = FIELD_GET(MTK_QDMA_TX_SCH_MAX_WFQ, val); |
| 454 | + max_rate = FIELD_GET(MTK_QDMA_TX_SCH_RATE_MAN, val); |
developer | c66b215 | 2023-01-11 15:20:04 +0800 | [diff] [blame] | 455 | + exp = FIELD_GET(MTK_QDMA_TX_SCH_RATE_EXP, val); |
| 456 | + while (exp--) |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 457 | + max_rate *= 10; |
| 458 | + |
| 459 | + len += scnprintf(buf + len, buf_len - len, |
| 460 | + "EN\tScheduling\tMAX\tQueue#\n%d\t%s%16d\t", enable, |
| 461 | + (scheduling == 1) ? "WRR" : "SP", max_rate); |
| 462 | + |
| 463 | + for (i = 0; i < MTK_QDMA_TX_NUM; i++) { |
| 464 | + val = readl(eth->base + MTK_QDMA_PAGE) & ~MTK_QTX_CFG_PAGE; |
| 465 | + val |= FIELD_PREP(MTK_QTX_CFG_PAGE, i / MTK_QTX_PER_PAGE); |
| 466 | + writel(val, eth->base + MTK_QDMA_PAGE); |
| 467 | + |
| 468 | + val = readl(eth->base + MTK_QTX_SCH(i % MTK_QTX_PER_PAGE)); |
| 469 | + if (eth->soc->txrx.qdma_tx_sch == 4) |
| 470 | + scheduler = FIELD_GET(MTK_QTX_SCH_TX_SCH_SEL_V2, val); |
| 471 | + else |
| 472 | + scheduler = FIELD_GET(MTK_QTX_SCH_TX_SCH_SEL, val); |
| 473 | + if (id == scheduler) |
| 474 | + len += scnprintf(buf + len, buf_len - len, "%d ", i); |
| 475 | + } |
| 476 | + |
| 477 | + len += scnprintf(buf + len, buf_len - len, "\n"); |
| 478 | + if (len > buf_len) |
| 479 | + len = buf_len; |
| 480 | + |
| 481 | + ret_cnt = simple_read_from_buffer(user_buf, count, ppos, buf, len); |
| 482 | + |
| 483 | + kfree(buf); |
| 484 | + return ret_cnt; |
| 485 | +} |
| 486 | + |
| 487 | +static ssize_t mtk_qmda_debugfs_write_qos_sched(struct file *file, const char __user *buf, |
| 488 | + size_t length, loff_t *offset) |
| 489 | +{ |
| 490 | + struct mtk_eth *eth = _eth; |
| 491 | + long id = (long)file->private_data; |
| 492 | + char line[64] = {0}, scheduling[32]; |
| 493 | + int enable, rate, exp = 0, shift = 0; |
| 494 | + size_t size; |
developer | c66b215 | 2023-01-11 15:20:04 +0800 | [diff] [blame] | 495 | + u32 sch, val = 0; |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 496 | + |
| 497 | + if (length >= sizeof(line)) |
| 498 | + return -EINVAL; |
| 499 | + |
| 500 | + if (copy_from_user(line, buf, length)) |
| 501 | + return -EFAULT; |
| 502 | + |
| 503 | + if (sscanf(line, "%d %s %d", &enable, scheduling, &rate) != 3) |
| 504 | + return -EFAULT; |
| 505 | + |
| 506 | + while (rate > 127) { |
| 507 | + rate /= 10; |
| 508 | + exp++; |
| 509 | + } |
| 510 | + |
| 511 | + line[length] = '\0'; |
| 512 | + |
| 513 | + if (enable) |
| 514 | + val |= FIELD_PREP(MTK_QDMA_TX_SCH_RATE_EN, 1); |
| 515 | + if (strcmp(scheduling, "sp") != 0) |
| 516 | + val |= FIELD_PREP(MTK_QDMA_TX_SCH_MAX_WFQ, 1); |
| 517 | + val |= FIELD_PREP(MTK_QDMA_TX_SCH_RATE_MAN, rate); |
| 518 | + val |= FIELD_PREP(MTK_QDMA_TX_SCH_RATE_EXP, exp); |
| 519 | + |
| 520 | + if (id & 0x1) |
| 521 | + shift = 16; |
| 522 | + |
| 523 | + if (eth->soc->txrx.qdma_tx_sch == 4) |
developer | c66b215 | 2023-01-11 15:20:04 +0800 | [diff] [blame] | 524 | + sch = readl(eth->base + MTK_QDMA_TX_4SCH_BASE(id)); |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 525 | + else |
developer | c66b215 | 2023-01-11 15:20:04 +0800 | [diff] [blame] | 526 | + sch = readl(eth->base + MTK_QDMA_TX_2SCH_BASE); |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 527 | + |
developer | c66b215 | 2023-01-11 15:20:04 +0800 | [diff] [blame] | 528 | + sch &= ~(MTK_QDMA_TX_SCH_MASK << shift); |
| 529 | + sch |= val << shift; |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 530 | + if (eth->soc->txrx.qdma_tx_sch == 4) |
developer | c66b215 | 2023-01-11 15:20:04 +0800 | [diff] [blame] | 531 | + writel(sch, eth->base + MTK_QDMA_TX_4SCH_BASE(id)); |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 532 | + else |
developer | c66b215 | 2023-01-11 15:20:04 +0800 | [diff] [blame] | 533 | + writel(sch, eth->base + MTK_QDMA_TX_2SCH_BASE); |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 534 | + |
| 535 | + size = strlen(line); |
| 536 | + *offset += size; |
| 537 | + |
| 538 | + return length; |
| 539 | +} |
| 540 | + |
| 541 | +static ssize_t mtk_qmda_debugfs_read_qos_queue(struct file *file, char __user *user_buf, |
| 542 | + size_t count, loff_t *ppos) |
| 543 | +{ |
| 544 | + struct mtk_eth *eth = _eth; |
| 545 | + long id = (long)file->private_data; |
| 546 | + char *buf; |
| 547 | + unsigned int len = 0, buf_len = 1500; |
| 548 | + int min_rate_en, min_rate, min_rate_exp; |
| 549 | + int max_rate_en, max_weight, max_rate, max_rate_exp; |
| 550 | + u32 qtx_sch, qtx_cfg, scheduler, val; |
| 551 | + ssize_t ret_cnt; |
| 552 | + |
| 553 | + buf = kzalloc(buf_len, GFP_KERNEL); |
| 554 | + if (!buf) |
| 555 | + return -ENOMEM; |
| 556 | + |
| 557 | + val = readl(eth->base + MTK_QDMA_PAGE) & ~MTK_QTX_CFG_PAGE; |
| 558 | + val |= FIELD_PREP(MTK_QTX_CFG_PAGE, id / MTK_QTX_PER_PAGE); |
| 559 | + writel(val, eth->base + MTK_QDMA_PAGE); |
| 560 | + |
| 561 | + qtx_cfg = readl(eth->base + MTK_QTX_CFG(id % MTK_QTX_PER_PAGE)); |
| 562 | + qtx_sch = readl(eth->base + MTK_QTX_SCH(id % MTK_QTX_PER_PAGE)); |
| 563 | + if (eth->soc->txrx.qdma_tx_sch == 4) |
| 564 | + scheduler = FIELD_GET(MTK_QTX_SCH_TX_SCH_SEL_V2, qtx_sch); |
| 565 | + else |
| 566 | + scheduler = FIELD_GET(MTK_QTX_SCH_TX_SCH_SEL, qtx_sch); |
| 567 | + |
| 568 | + min_rate_en = FIELD_GET(MTK_QTX_SCH_MIN_RATE_EN, qtx_sch); |
| 569 | + min_rate = FIELD_GET(MTK_QTX_SCH_MIN_RATE_MAN, qtx_sch); |
| 570 | + min_rate_exp = FIELD_GET(MTK_QTX_SCH_MIN_RATE_EXP, qtx_sch); |
| 571 | + max_rate_en = FIELD_GET(MTK_QTX_SCH_MAX_RATE_EN, qtx_sch); |
| 572 | + max_weight = FIELD_GET(MTK_QTX_SCH_MAX_RATE_WGHT, qtx_sch); |
| 573 | + max_rate = FIELD_GET(MTK_QTX_SCH_MAX_RATE_MAN, qtx_sch); |
| 574 | + max_rate_exp = FIELD_GET(MTK_QTX_SCH_MAX_RATE_EXP, qtx_sch); |
| 575 | + while (min_rate_exp--) |
| 576 | + min_rate *= 10; |
| 577 | + |
| 578 | + while (max_rate_exp--) |
| 579 | + max_rate *= 10; |
| 580 | + |
| 581 | + len += scnprintf(buf + len, buf_len - len, |
| 582 | + "scheduler: %d\nhw resv: %d\nsw resv: %d\n", scheduler, |
| 583 | + (qtx_cfg >> 8) & 0xff, qtx_cfg & 0xff); |
| 584 | + |
| 585 | + /* Switch to debug mode */ |
| 586 | + val = readl(eth->base + MTK_QTX_MIB_IF) & ~MTK_MIB_ON_QTX_CFG; |
| 587 | + val |= MTK_MIB_ON_QTX_CFG; |
| 588 | + writel(val, eth->base + MTK_QTX_MIB_IF); |
| 589 | + |
| 590 | + val = readl(eth->base + MTK_QTX_MIB_IF) & ~MTK_VQTX_MIB_EN; |
| 591 | + val |= MTK_VQTX_MIB_EN; |
| 592 | + writel(val, eth->base + MTK_QTX_MIB_IF); |
| 593 | + |
| 594 | + qtx_cfg = readl(eth->base + MTK_QTX_CFG(id % MTK_QTX_PER_PAGE)); |
| 595 | + qtx_sch = readl(eth->base + MTK_QTX_SCH(id % MTK_QTX_PER_PAGE)); |
| 596 | + |
| 597 | + len += scnprintf(buf + len, buf_len - len, |
| 598 | + "packet count: %u\n", qtx_cfg); |
| 599 | + len += scnprintf(buf + len, buf_len - len, |
| 600 | + "packet drop: %u\n\n", qtx_sch); |
| 601 | + |
| 602 | + /* Recover to normal mode */ |
| 603 | + val = readl(eth->base + MTK_QTX_MIB_IF); |
| 604 | + val &= ~MTK_MIB_ON_QTX_CFG; |
| 605 | + writel(val, eth->base + MTK_QTX_MIB_IF); |
| 606 | + |
| 607 | + val = readl(eth->base + MTK_QTX_MIB_IF); |
| 608 | + val &= ~MTK_VQTX_MIB_EN; |
| 609 | + writel(val, eth->base + MTK_QTX_MIB_IF); |
| 610 | + |
| 611 | + len += scnprintf(buf + len, buf_len - len, |
| 612 | + " EN RATE WEIGHT\n"); |
| 613 | + len += scnprintf(buf + len, buf_len - len, |
| 614 | + "----------------------------\n"); |
| 615 | + len += scnprintf(buf + len, buf_len - len, |
| 616 | + "max%5d%9d%9d\n", max_rate_en, max_rate, max_weight); |
| 617 | + len += scnprintf(buf + len, buf_len - len, |
| 618 | + "min%5d%9d -\n", min_rate_en, min_rate); |
| 619 | + |
| 620 | + if (len > buf_len) |
| 621 | + len = buf_len; |
| 622 | + |
| 623 | + ret_cnt = simple_read_from_buffer(user_buf, count, ppos, buf, len); |
| 624 | + |
| 625 | + kfree(buf); |
| 626 | + |
| 627 | + return ret_cnt; |
| 628 | +} |
| 629 | + |
| 630 | +static ssize_t mtk_qmda_debugfs_write_qos_queue(struct file *file, const char __user *buf, |
| 631 | + size_t length, loff_t *offset) |
| 632 | +{ |
| 633 | + struct mtk_eth *eth = _eth; |
| 634 | + long id = (long)file->private_data; |
| 635 | + char line[64] = {0}; |
| 636 | + int max_enable, max_rate, max_exp = 0; |
| 637 | + int min_enable, min_rate, min_exp = 0; |
| 638 | + int scheduler, weight, resv; |
| 639 | + size_t size; |
| 640 | + u32 val; |
| 641 | + |
| 642 | + if (length >= sizeof(line)) |
| 643 | + return -EINVAL; |
| 644 | + |
| 645 | + if (copy_from_user(line, buf, length)) |
| 646 | + return -EFAULT; |
| 647 | + |
| 648 | + if (sscanf(line, "%d %d %d %d %d %d %d", &scheduler, &min_enable, &min_rate, |
| 649 | + &max_enable, &max_rate, &weight, &resv) != 7) |
| 650 | + return -EFAULT; |
| 651 | + |
| 652 | + line[length] = '\0'; |
| 653 | + |
| 654 | + while (max_rate > 127) { |
| 655 | + max_rate /= 10; |
| 656 | + max_exp++; |
| 657 | + } |
| 658 | + |
| 659 | + while (min_rate > 127) { |
| 660 | + min_rate /= 10; |
| 661 | + min_exp++; |
| 662 | + } |
| 663 | + |
| 664 | + val = readl(eth->base + MTK_QDMA_PAGE) & ~MTK_QTX_CFG_PAGE; |
| 665 | + val |= FIELD_PREP(MTK_QTX_CFG_PAGE, id / MTK_QTX_PER_PAGE); |
| 666 | + writel(val, eth->base + MTK_QDMA_PAGE); |
| 667 | + |
| 668 | + if (eth->soc->txrx.qdma_tx_sch == 4) |
| 669 | + val = FIELD_PREP(MTK_QTX_SCH_TX_SCH_SEL_V2, scheduler); |
| 670 | + else |
| 671 | + val = FIELD_PREP(MTK_QTX_SCH_TX_SCH_SEL, scheduler); |
| 672 | + if (min_enable) |
| 673 | + val |= MTK_QTX_SCH_MIN_RATE_EN; |
| 674 | + val |= FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, min_rate); |
| 675 | + val |= FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, min_exp); |
| 676 | + if (max_enable) |
| 677 | + val |= MTK_QTX_SCH_MAX_RATE_EN; |
| 678 | + val |= FIELD_PREP(MTK_QTX_SCH_MAX_RATE_WGHT, weight); |
| 679 | + val |= FIELD_PREP(MTK_QTX_SCH_MAX_RATE_MAN, max_rate); |
| 680 | + val |= FIELD_PREP(MTK_QTX_SCH_MAX_RATE_EXP, max_exp); |
| 681 | + writel(val, eth->base + MTK_QTX_SCH(id % MTK_QTX_PER_PAGE)); |
| 682 | + |
| 683 | + val = readl(eth->base + MTK_QTX_CFG(id % MTK_QTX_PER_PAGE)); |
| 684 | + val |= FIELD_PREP(MTK_QTX_CFG_HW_RESV_CNT_OFFSET, resv); |
| 685 | + val |= FIELD_PREP(MTK_QTX_CFG_SW_RESV_CNT_OFFSET, resv); |
| 686 | + writel(val, eth->base + MTK_QTX_CFG(id % MTK_QTX_PER_PAGE)); |
| 687 | + |
| 688 | + size = strlen(line); |
| 689 | + *offset += size; |
| 690 | + |
| 691 | + return length; |
| 692 | +} |
| 693 | + |
| 694 | +int mtk_qdma_debugfs_init(struct mtk_eth *eth) |
| 695 | +{ |
| 696 | + static const struct file_operations fops_qos = { |
| 697 | + .open = mtk_qmda_debugfs_open_qos, |
| 698 | + .read = seq_read, |
| 699 | + .llseek = seq_lseek, |
| 700 | + .write = mtk_qmda_debugfs_write_qos, |
| 701 | + .release = single_release, |
| 702 | + }; |
| 703 | + |
| 704 | + static const struct file_operations fops_qos_sched = { |
| 705 | + .open = simple_open, |
| 706 | + .read = mtk_qmda_debugfs_read_qos_sched, |
| 707 | + .write = mtk_qmda_debugfs_write_qos_sched, |
| 708 | + .llseek = default_llseek, |
| 709 | + }; |
| 710 | + |
| 711 | + static const struct file_operations fops_qos_queue = { |
| 712 | + .open = simple_open, |
| 713 | + .read = mtk_qmda_debugfs_read_qos_queue, |
| 714 | + .write = mtk_qmda_debugfs_write_qos_queue, |
| 715 | + .llseek = default_llseek, |
| 716 | + }; |
| 717 | + |
| 718 | + struct dentry *root; |
| 719 | + long i; |
| 720 | + char name[16]; |
| 721 | + |
| 722 | + _eth = eth; |
| 723 | + |
| 724 | + root = debugfs_lookup("mtk_ppe", NULL); |
| 725 | + if (!root) |
| 726 | + return -ENOMEM; |
| 727 | + |
developer | 0a32014 | 2022-09-21 23:18:01 +0800 | [diff] [blame] | 728 | + debugfs_create_file("qos_toggle", S_IRUGO, root, eth, &fops_qos); |
developer | 73cb4d5 | 2022-09-06 15:15:57 +0800 | [diff] [blame] | 729 | + |
| 730 | + for (i = 0; i < eth->soc->txrx.qdma_tx_sch; i++) { |
| 731 | + snprintf(name, sizeof(name), "qdma_sch%ld", i); |
| 732 | + debugfs_create_file(name, S_IRUGO, root, (void *)i, |
| 733 | + &fops_qos_sched); |
| 734 | + } |
| 735 | + |
| 736 | + for (i = 0; i < MTK_QDMA_TX_NUM; i++) { |
| 737 | + snprintf(name, sizeof(name), "qdma_txq%ld", i); |
| 738 | + debugfs_create_file(name, S_IRUGO, root, (void *)i, |
| 739 | + &fops_qos_queue); |
| 740 | + } |
| 741 | + |
| 742 | + return 0; |
| 743 | +} |