blob: 7967ea877db07393be35412de98ade8c18be8dc3 [file] [log] [blame]
developer24455dd2021-10-28 10:55:41 +08001/dts-v1/;
2#include "mt7981.dtsi"
3/ {
4 model = "MediaTek MT7981 RFB";
developera1c200a2022-03-04 20:10:00 +08005 compatible = "mediatek,mt7981-snfi-snand-pcie-2500wan-p5-rfb";
developer24455dd2021-10-28 10:55:41 +08006 chosen {
7 bootargs = "console=ttyS0,115200n1 loglevel=8 \
8 earlycon=uart8250,mmio32,0x11002000";
9 };
10
11 memory {
12 // fpga ddr2: 128MB*2
13 reg = <0 0x40000000 0 0x10000000>;
14 };
15
developer7e6086a2022-05-18 14:50:36 +080016 gpio-keys {
17 compatible = "gpio-keys";
18 reset {
19 label = "reset";
20 linux,code = <KEY_RESTART>;
21 gpios = <&pio 1 GPIO_ACTIVE_LOW>;
22 };
23
24 wps {
25 label = "wps";
26 linux,code = <KEY_WPS_BUTTON>;
27 gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
28 };
29 };
30
developer24455dd2021-10-28 10:55:41 +080031 nmbm_snfi {
32 compatible = "generic,nmbm";
33
34 #address-cells = <1>;
35 #size-cells = <1>;
36
37 lower-mtd-device = <&snand>;
38 forced-create;
39 empty-page-ecc-protected;
40
41 partitions {
42 compatible = "fixed-partitions";
43 #address-cells = <1>;
44 #size-cells = <1>;
45
46 partition@0 {
47 label = "BL2";
48 reg = <0x00000 0x0100000>;
49 read-only;
50 };
51
52 partition@100000 {
53 label = "u-boot-env";
54 reg = <0x0100000 0x0080000>;
55 };
56
57 factory: partition@180000 {
58 label = "Factory";
59 reg = <0x180000 0x0200000>;
60 };
61
62 partition@380000 {
63 label = "FIP";
64 reg = <0x380000 0x0200000>;
65 };
66
67 partition@580000 {
68 label = "ubi";
69 reg = <0x580000 0x4000000>;
70 };
71 };
72 };
73};
74
75&uart0 {
76 status = "okay";
77};
78
79&watchdog {
80 status = "okay";
81};
82
83&eth {
84 status = "okay";
85
86 gmac0: mac@0 {
87 compatible = "mediatek,eth-mac";
88 reg = <0>;
89 phy-mode = "2500base-x";
90
91 fixed-link {
92 speed = <2500>;
93 full-duplex;
94 pause;
95 };
96 };
97
98 mdio: mdio-bus {
99 #address-cells = <1>;
100 #size-cells = <0>;
101
developer32805cd2022-01-06 17:08:06 +0800102 phy5: phy@5 {
103 compatible = "ethernet-phy-id67c9.de0a";
104 reg = <5>;
105 reset-gpios = <&pio 14 1>;
developer8c5a08b2022-05-06 09:10:38 +0800106 reset-assert-us = <600>;
developer32805cd2022-01-06 17:08:06 +0800107 reset-deassert-us = <20000>;
108 phy-mode = "2500base-x";
109 };
developer24455dd2021-10-28 10:55:41 +0800110
111 switch@0 {
112 compatible = "mediatek,mt7531";
113 reg = <31>;
114 reset-gpios = <&pio 39 0>;
115
116 ports {
117 #address-cells = <1>;
118 #size-cells = <0>;
119
120 port@0 {
121 reg = <0>;
122 label = "lan1";
123 };
124
125 port@1 {
126 reg = <1>;
127 label = "lan2";
128 };
129
130 port@2 {
131 reg = <2>;
132 label = "lan3";
133 };
134
135 port@3 {
136 reg = <3>;
137 label = "lan4";
138 };
139
140 port@5 {
141 reg = <5>;
142 label = "wan";
143 phy-mode = "2500base-x";
144
145 fixed-link {
146 speed = <2500>;
147 full-duplex;
148 pause;
149 };
150 };
151
152 port@6 {
153 reg = <6>;
154 label = "cpu";
155 ethernet = <&gmac0>;
156 phy-mode = "2500base-x";
157
158 fixed-link {
159 speed = <2500>;
160 full-duplex;
161 pause;
162 };
163 };
164 };
165 };
166 };
167};
168
169&hnat {
170 mtketh-wan = "wan";
171 mtketh-lan = "lan";
172 mtketh-max-gmac = <1>;
173 status = "okay";
174};
175
176&snand {
177 pinctrl-names = "default";
developer24455dd2021-10-28 10:55:41 +0800178 pinctrl-0 = <&snfi_pins>;
179 status = "okay";
180 mediatek,quad-spi;
developer24455dd2021-10-28 10:55:41 +0800181};
182
183&spi1 {
184 pinctrl-names = "default";
185 pinctrl-0 = <&spic_pins>;
186 status = "disabled";
187};
188
189&pcie {
190 pinctrl-names = "default";
191 pinctrl-0 = <&pcie_pins>;
192 status = "okay";
193};
194
195&pio {
196
197 pcie_pins: pcie-pins {
198 mux {
199 function = "pcie";
200 groups = "pcie_pereset", "pcie_clk", "pcie_wake";
201 };
202 };
203
204 snfi_pins: snfi-pins {
205 mux {
206 function = "flash";
207 groups = "snfi";
208 };
209 };
210
211 spic_pins: spi1-pins {
212 mux {
213 function = "spi";
214 groups = "spi1_1";
215 };
216 };
217};
218
219&xhci {
220 status = "okay";
221};