blob: ea663eb02648d9ef5c80b87321111ada5406e234 [file] [log] [blame]
developer24455dd2021-10-28 10:55:41 +08001/dts-v1/;
2#include "mt7981.dtsi"
3/ {
4 model = "MediaTek MT7981 RFB";
developera1c200a2022-03-04 20:10:00 +08005 compatible = "mediatek,mt7981-snfi-snand-pcie-2500wan-p5-rfb";
developer24455dd2021-10-28 10:55:41 +08006 chosen {
7 bootargs = "console=ttyS0,115200n1 loglevel=8 \
8 earlycon=uart8250,mmio32,0x11002000";
9 };
10
11 memory {
12 // fpga ddr2: 128MB*2
13 reg = <0 0x40000000 0 0x10000000>;
14 };
15
16 nmbm_snfi {
17 compatible = "generic,nmbm";
18
19 #address-cells = <1>;
20 #size-cells = <1>;
21
22 lower-mtd-device = <&snand>;
23 forced-create;
24 empty-page-ecc-protected;
25
26 partitions {
27 compatible = "fixed-partitions";
28 #address-cells = <1>;
29 #size-cells = <1>;
30
31 partition@0 {
32 label = "BL2";
33 reg = <0x00000 0x0100000>;
34 read-only;
35 };
36
37 partition@100000 {
38 label = "u-boot-env";
39 reg = <0x0100000 0x0080000>;
40 };
41
42 factory: partition@180000 {
43 label = "Factory";
44 reg = <0x180000 0x0200000>;
45 };
46
47 partition@380000 {
48 label = "FIP";
49 reg = <0x380000 0x0200000>;
50 };
51
52 partition@580000 {
53 label = "ubi";
54 reg = <0x580000 0x4000000>;
55 };
56 };
57 };
58};
59
60&uart0 {
61 status = "okay";
62};
63
64&watchdog {
65 status = "okay";
66};
67
68&eth {
69 status = "okay";
70
71 gmac0: mac@0 {
72 compatible = "mediatek,eth-mac";
73 reg = <0>;
74 phy-mode = "2500base-x";
75
76 fixed-link {
77 speed = <2500>;
78 full-duplex;
79 pause;
80 };
81 };
82
83 mdio: mdio-bus {
84 #address-cells = <1>;
85 #size-cells = <0>;
86
developer32805cd2022-01-06 17:08:06 +080087 phy5: phy@5 {
88 compatible = "ethernet-phy-id67c9.de0a";
89 reg = <5>;
90 reset-gpios = <&pio 14 1>;
91 reset-deassert-us = <20000>;
92 phy-mode = "2500base-x";
93 };
developer24455dd2021-10-28 10:55:41 +080094
95 switch@0 {
96 compatible = "mediatek,mt7531";
97 reg = <31>;
98 reset-gpios = <&pio 39 0>;
99
100 ports {
101 #address-cells = <1>;
102 #size-cells = <0>;
103
104 port@0 {
105 reg = <0>;
106 label = "lan1";
107 };
108
109 port@1 {
110 reg = <1>;
111 label = "lan2";
112 };
113
114 port@2 {
115 reg = <2>;
116 label = "lan3";
117 };
118
119 port@3 {
120 reg = <3>;
121 label = "lan4";
122 };
123
124 port@5 {
125 reg = <5>;
126 label = "wan";
127 phy-mode = "2500base-x";
128
129 fixed-link {
130 speed = <2500>;
131 full-duplex;
132 pause;
133 };
134 };
135
136 port@6 {
137 reg = <6>;
138 label = "cpu";
139 ethernet = <&gmac0>;
140 phy-mode = "2500base-x";
141
142 fixed-link {
143 speed = <2500>;
144 full-duplex;
145 pause;
146 };
147 };
148 };
149 };
150 };
151};
152
153&hnat {
154 mtketh-wan = "wan";
155 mtketh-lan = "lan";
156 mtketh-max-gmac = <1>;
157 status = "okay";
158};
159
160&snand {
161 pinctrl-names = "default";
developer24455dd2021-10-28 10:55:41 +0800162 pinctrl-0 = <&snfi_pins>;
163 status = "okay";
164 mediatek,quad-spi;
developer24455dd2021-10-28 10:55:41 +0800165};
166
167&spi1 {
168 pinctrl-names = "default";
169 pinctrl-0 = <&spic_pins>;
170 status = "disabled";
171};
172
173&pcie {
174 pinctrl-names = "default";
175 pinctrl-0 = <&pcie_pins>;
176 status = "okay";
177};
178
179&pio {
180
181 pcie_pins: pcie-pins {
182 mux {
183 function = "pcie";
184 groups = "pcie_pereset", "pcie_clk", "pcie_wake";
185 };
186 };
187
188 snfi_pins: snfi-pins {
189 mux {
190 function = "flash";
191 groups = "snfi";
192 };
193 };
194
195 spic_pins: spi1-pins {
196 mux {
197 function = "spi";
198 groups = "spi1_1";
199 };
200 };
201};
202
203&xhci {
204 status = "okay";
205};