developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * MediaTek PCIe host controller driver. |
| 4 | * |
| 5 | * Copyright (c) 2020 MediaTek Inc. |
| 6 | * Author: Jianjun Wang <jianjun.wang@mediatek.com> |
| 7 | */ |
| 8 | |
| 9 | #include <linux/clk.h> |
| 10 | #include <linux/delay.h> |
| 11 | #include <linux/iopoll.h> |
| 12 | #include <linux/irq.h> |
| 13 | #include <linux/irqchip/chained_irq.h> |
| 14 | #include <linux/irqdomain.h> |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/module.h> |
| 17 | #include <linux/msi.h> |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 18 | #include <linux/of_pci.h> |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 19 | #include <linux/pci.h> |
| 20 | #include <linux/phy/phy.h> |
| 21 | #include <linux/platform_device.h> |
| 22 | #include <linux/pm_domain.h> |
| 23 | #include <linux/pm_runtime.h> |
| 24 | #include <linux/reset.h> |
| 25 | |
| 26 | #include "../pci.h" |
| 27 | |
| 28 | #define PCIE_SETTING_REG 0x80 |
| 29 | #define PCIE_PCI_IDS_1 0x9c |
| 30 | #define PCI_CLASS(class) (class << 8) |
| 31 | #define PCIE_RC_MODE BIT(0) |
| 32 | |
| 33 | #define PCIE_CFGNUM_REG 0x140 |
| 34 | #define PCIE_CFG_DEVFN(devfn) ((devfn) & GENMASK(7, 0)) |
| 35 | #define PCIE_CFG_BUS(bus) (((bus) << 8) & GENMASK(15, 8)) |
| 36 | #define PCIE_CFG_BYTE_EN(bytes) (((bytes) << 16) & GENMASK(19, 16)) |
| 37 | #define PCIE_CFG_FORCE_BYTE_EN BIT(20) |
| 38 | #define PCIE_CFG_OFFSET_ADDR 0x1000 |
| 39 | #define PCIE_CFG_HEADER(bus, devfn) \ |
| 40 | (PCIE_CFG_BUS(bus) | PCIE_CFG_DEVFN(devfn)) |
| 41 | |
| 42 | #define PCIE_RST_CTRL_REG 0x148 |
| 43 | #define PCIE_MAC_RSTB BIT(0) |
| 44 | #define PCIE_PHY_RSTB BIT(1) |
| 45 | #define PCIE_BRG_RSTB BIT(2) |
| 46 | #define PCIE_PE_RSTB BIT(3) |
| 47 | |
| 48 | #define PCIE_LTSSM_STATUS_REG 0x150 |
| 49 | #define PCIE_LTSSM_STATE_MASK GENMASK(28, 24) |
| 50 | #define PCIE_LTSSM_STATE(val) ((val & PCIE_LTSSM_STATE_MASK) >> 24) |
| 51 | #define PCIE_LTSSM_STATE_L2_IDLE 0x14 |
| 52 | |
| 53 | #define PCIE_LINK_STATUS_REG 0x154 |
| 54 | #define PCIE_PORT_LINKUP BIT(8) |
| 55 | |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 56 | #define PCIE_MSI_GROUP_NUM 4 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 57 | #define PCIE_MSI_SET_NUM 8 |
| 58 | #define PCIE_MSI_IRQS_PER_SET 32 |
| 59 | #define PCIE_MSI_IRQS_NUM \ |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 60 | (PCIE_MSI_IRQS_PER_SET * PCIE_MSI_SET_NUM) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 61 | |
| 62 | #define PCIE_INT_ENABLE_REG 0x180 |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 63 | #define PCIE_MSI_ENABLE GENMASK(PCIE_MSI_SET_NUM + 8 - 1, 8) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 64 | #define PCIE_MSI_SHIFT 8 |
| 65 | #define PCIE_INTX_SHIFT 24 |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 66 | #define PCIE_INTX_ENABLE \ |
| 67 | GENMASK(PCIE_INTX_SHIFT + PCI_NUM_INTX - 1, PCIE_INTX_SHIFT) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 68 | |
| 69 | #define PCIE_INT_STATUS_REG 0x184 |
| 70 | #define PCIE_MSI_SET_ENABLE_REG 0x190 |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 71 | #define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0) |
| 72 | |
| 73 | #define PCIE_MSI_SET_BASE_REG 0xc00 |
| 74 | #define PCIE_MSI_SET_OFFSET 0x10 |
| 75 | #define PCIE_MSI_SET_STATUS_OFFSET 0x04 |
| 76 | #define PCIE_MSI_SET_ENABLE_OFFSET 0x08 |
developer | 63dcf01 | 2021-09-02 10:14:03 +0800 | [diff] [blame] | 77 | #define PCIE_MSI_SET_GRP1_ENABLE_OFFSET 0x0c |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 78 | |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 79 | #define PCIE_MSI_SET_GRP2_ENABLE_OFFSET 0x1c0 |
| 80 | #define PCIE_MSI_SET_GRP2_OFFSET 0x04 |
| 81 | |
| 82 | #define PCIE_MSI_SET_GRP3_ENABLE_OFFSET 0x1e0 |
| 83 | #define PCIE_MSI_SET_GRP3_OFFSET 0x04 |
| 84 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 85 | #define PCIE_MSI_SET_ADDR_HI_BASE 0xc80 |
| 86 | #define PCIE_MSI_SET_ADDR_HI_OFFSET 0x04 |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 87 | |
| 88 | #define PCIE_ICMD_PM_REG 0x198 |
| 89 | #define PCIE_TURN_OFF_LINK BIT(4) |
| 90 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 91 | #define PCIE_TRANS_TABLE_BASE_REG 0x800 |
| 92 | #define PCIE_ATR_SRC_ADDR_MSB_OFFSET 0x4 |
| 93 | #define PCIE_ATR_TRSL_ADDR_LSB_OFFSET 0x8 |
| 94 | #define PCIE_ATR_TRSL_ADDR_MSB_OFFSET 0xc |
| 95 | #define PCIE_ATR_TRSL_PARAM_OFFSET 0x10 |
| 96 | #define PCIE_ATR_TLB_SET_OFFSET 0x20 |
| 97 | |
| 98 | #define PCIE_MAX_TRANS_TABLES 8 |
| 99 | #define PCIE_ATR_EN BIT(0) |
| 100 | #define PCIE_ATR_SIZE(size) \ |
| 101 | (((((size) - 1) << 1) & GENMASK(6, 1)) | PCIE_ATR_EN) |
| 102 | #define PCIE_ATR_ID(id) ((id) & GENMASK(3, 0)) |
| 103 | #define PCIE_ATR_TYPE_MEM PCIE_ATR_ID(0) |
| 104 | #define PCIE_ATR_TYPE_IO PCIE_ATR_ID(1) |
| 105 | #define PCIE_ATR_TLP_TYPE(type) (((type) << 16) & GENMASK(18, 16)) |
| 106 | #define PCIE_ATR_TLP_TYPE_MEM PCIE_ATR_TLP_TYPE(0) |
| 107 | #define PCIE_ATR_TLP_TYPE_IO PCIE_ATR_TLP_TYPE(2) |
| 108 | |
| 109 | /** |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 110 | * enum mtk_msi_group_type - PCIe controller MSI group type |
| 111 | * @group0_merge_msi: all MSI are merged to group0 |
| 112 | * @group1_direct_msi: all MSI have independent IRQs via group1 |
| 113 | * @group_binding_msi: all MSI are bound to all group |
| 114 | */ |
| 115 | enum mtk_msi_group_type { |
| 116 | group0_merge_msi, |
| 117 | group1_direct_msi, |
| 118 | group_binding_msi, |
| 119 | }; |
| 120 | |
| 121 | /** |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 122 | * struct mtk_msi_set - MSI information for each set |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 123 | * @base: IO mapped register base |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 124 | * @enable: IO mapped enable register address |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 125 | * @msg_addr: MSI message address |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 126 | * @saved_irq_state: IRQ enable state saved at suspend time |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 127 | */ |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 128 | struct mtk_msi_set { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 129 | void __iomem *base; |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 130 | void __iomem *enable[PCIE_MSI_GROUP_NUM]; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 131 | phys_addr_t msg_addr; |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 132 | u32 saved_irq_state[PCIE_MSI_GROUP_NUM]; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 133 | }; |
| 134 | |
| 135 | /** |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 136 | * struct mtk_pcie_irq - PCIe controller interrupt information |
| 137 | * @irq: IRQ interrupt number |
| 138 | * @group: IRQ MSI group number |
| 139 | * @mapped_table: IRQ MSI group mapped table |
| 140 | */ |
| 141 | struct mtk_pcie_irq { |
| 142 | int irq; |
| 143 | int group; |
| 144 | u32 mapped_table; |
| 145 | }; |
| 146 | |
| 147 | /** |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 148 | * struct mtk_pcie_port - PCIe port information |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 149 | * @dev: pointer to PCIe device |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 150 | * @base: IO mapped register base |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 151 | * @reg_base: physical register base |
| 152 | * @mac_reset: MAC reset control |
| 153 | * @phy_reset: PHY reset control |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 154 | * @phy: PHY controller block |
| 155 | * @clks: PCIe clocks |
| 156 | * @num_clks: PCIe clocks count for this port |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 157 | * @max_link_width: PCIe slot max supported link width |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 158 | * @irq: PCIe controller interrupt number |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 159 | * @num_irqs: PCIe irqs count |
| 160 | * @irqs: PCIe controller interrupts information |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 161 | * @saved_irq_state: IRQ enable state saved at suspend time |
| 162 | * @irq_lock: lock protecting IRQ register access |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 163 | * @intx_domain: legacy INTx IRQ domain |
| 164 | * @msi_domain: MSI IRQ domain |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 165 | * @msi_bottom_domain: MSI IRQ bottom domain |
| 166 | * @msi_sets: MSI sets information |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 167 | * @msi_group_type: PCIe controller MSI group type |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 168 | * @lock: lock protecting IRQ bit map |
| 169 | * @msi_irq_in_use: bit map for assigned MSI IRQ |
| 170 | */ |
| 171 | struct mtk_pcie_port { |
| 172 | struct device *dev; |
| 173 | void __iomem *base; |
| 174 | phys_addr_t reg_base; |
| 175 | struct reset_control *mac_reset; |
| 176 | struct reset_control *phy_reset; |
| 177 | struct phy *phy; |
| 178 | struct clk_bulk_data *clks; |
| 179 | int num_clks; |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 180 | int max_link_width; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 181 | |
| 182 | int irq; |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 183 | int num_irqs; |
| 184 | struct mtk_pcie_irq *irqs; |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 185 | u32 saved_irq_state; |
| 186 | raw_spinlock_t irq_lock; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 187 | struct irq_domain *intx_domain; |
| 188 | struct irq_domain *msi_domain; |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 189 | struct irq_domain *msi_bottom_domain; |
| 190 | struct mtk_msi_set msi_sets[PCIE_MSI_SET_NUM]; |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 191 | enum mtk_msi_group_type msi_group_type; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 192 | struct mutex lock; |
| 193 | DECLARE_BITMAP(msi_irq_in_use, PCIE_MSI_IRQS_NUM); |
| 194 | }; |
| 195 | |
| 196 | /** |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 197 | * mtk_pcie_config_tlp_header() - Configure a configuration TLP header |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 198 | * @bus: PCI bus to query |
| 199 | * @devfn: device/function number |
| 200 | * @where: offset in config space |
| 201 | * @size: data size in TLP header |
| 202 | * |
| 203 | * Set byte enable field and device information in configuration TLP header. |
| 204 | */ |
| 205 | static void mtk_pcie_config_tlp_header(struct pci_bus *bus, unsigned int devfn, |
| 206 | int where, int size) |
| 207 | { |
| 208 | struct mtk_pcie_port *port = bus->sysdata; |
| 209 | int bytes; |
| 210 | u32 val; |
| 211 | |
| 212 | bytes = (GENMASK(size - 1, 0) & 0xf) << (where & 0x3); |
| 213 | |
| 214 | val = PCIE_CFG_FORCE_BYTE_EN | PCIE_CFG_BYTE_EN(bytes) | |
| 215 | PCIE_CFG_HEADER(bus->number, devfn); |
| 216 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 217 | writel_relaxed(val, port->base + PCIE_CFGNUM_REG); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 218 | } |
| 219 | |
| 220 | static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus, unsigned int devfn, |
| 221 | int where) |
| 222 | { |
| 223 | struct mtk_pcie_port *port = bus->sysdata; |
| 224 | |
| 225 | return port->base + PCIE_CFG_OFFSET_ADDR + where; |
| 226 | } |
| 227 | |
| 228 | static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn, |
| 229 | int where, int size, u32 *val) |
| 230 | { |
| 231 | mtk_pcie_config_tlp_header(bus, devfn, where, size); |
| 232 | |
| 233 | return pci_generic_config_read32(bus, devfn, where, size, val); |
| 234 | } |
| 235 | |
| 236 | static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn, |
| 237 | int where, int size, u32 val) |
| 238 | { |
| 239 | mtk_pcie_config_tlp_header(bus, devfn, where, size); |
| 240 | |
| 241 | if (size <= 2) |
| 242 | val <<= (where & 0x3) * 8; |
| 243 | |
| 244 | return pci_generic_config_write32(bus, devfn, where, 4, val); |
| 245 | } |
| 246 | |
| 247 | static struct pci_ops mtk_pcie_ops = { |
| 248 | .map_bus = mtk_pcie_map_bus, |
| 249 | .read = mtk_pcie_config_read, |
| 250 | .write = mtk_pcie_config_write, |
| 251 | }; |
| 252 | |
developer | ca1c6b2 | 2023-04-26 19:51:06 +0800 | [diff] [blame] | 253 | /** |
| 254 | * This function will try to find the limitation of link width by finding |
| 255 | * a property called "max-link-width" of the given device node. |
| 256 | * |
| 257 | * @node: device tree node with the max link width information |
| 258 | * |
| 259 | * Returns the associated max link width from DT, or a negative value if the |
| 260 | * required property is not found or is invalid. |
| 261 | */ |
| 262 | int of_pci_get_max_link_width(struct device_node *node) |
| 263 | { |
| 264 | u32 max_link_width = 0; |
| 265 | |
| 266 | if (of_property_read_u32(node, "max-link-width", &max_link_width) || |
| 267 | max_link_width == 0 || max_link_width > 2) |
| 268 | return -EINVAL; |
| 269 | |
| 270 | return max_link_width; |
| 271 | } |
| 272 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 273 | static int mtk_pcie_set_trans_table(struct mtk_pcie_port *port, |
| 274 | resource_size_t cpu_addr, |
| 275 | resource_size_t pci_addr, |
| 276 | resource_size_t size, |
| 277 | unsigned long type, int num) |
| 278 | { |
| 279 | void __iomem *table; |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 280 | u32 val; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 281 | |
| 282 | if (num >= PCIE_MAX_TRANS_TABLES) { |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 283 | dev_err(port->dev, "not enough translate table for addr: %#llx, limited to [%d]\n", |
| 284 | (unsigned long long)cpu_addr, PCIE_MAX_TRANS_TABLES); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 285 | return -ENODEV; |
| 286 | } |
| 287 | |
| 288 | table = port->base + PCIE_TRANS_TABLE_BASE_REG + |
| 289 | num * PCIE_ATR_TLB_SET_OFFSET; |
| 290 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 291 | writel_relaxed(lower_32_bits(cpu_addr) | PCIE_ATR_SIZE(fls(size) - 1), |
| 292 | table); |
| 293 | writel_relaxed(upper_32_bits(cpu_addr), |
| 294 | table + PCIE_ATR_SRC_ADDR_MSB_OFFSET); |
| 295 | writel_relaxed(lower_32_bits(pci_addr), |
| 296 | table + PCIE_ATR_TRSL_ADDR_LSB_OFFSET); |
| 297 | writel_relaxed(upper_32_bits(pci_addr), |
| 298 | table + PCIE_ATR_TRSL_ADDR_MSB_OFFSET); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 299 | |
| 300 | if (type == IORESOURCE_IO) |
| 301 | val = PCIE_ATR_TYPE_IO | PCIE_ATR_TLP_TYPE_IO; |
| 302 | else |
| 303 | val = PCIE_ATR_TYPE_MEM | PCIE_ATR_TLP_TYPE_MEM; |
| 304 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 305 | writel_relaxed(val, table + PCIE_ATR_TRSL_PARAM_OFFSET); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 306 | |
| 307 | return 0; |
| 308 | } |
| 309 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 310 | static void mtk_pcie_enable_msi(struct mtk_pcie_port *port) |
| 311 | { |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 312 | void __iomem *base = port->base + PCIE_MSI_SET_BASE_REG; |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 313 | int i; |
| 314 | u32 val; |
| 315 | |
| 316 | for (i = 0; i < PCIE_MSI_SET_NUM; i++) { |
| 317 | struct mtk_msi_set *msi_set = &port->msi_sets[i]; |
| 318 | |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 319 | msi_set->base = base + i * PCIE_MSI_SET_OFFSET; |
| 320 | msi_set->enable[0] = base + PCIE_MSI_SET_ENABLE_OFFSET + |
| 321 | i * PCIE_MSI_SET_OFFSET; |
| 322 | msi_set->enable[1] = base + PCIE_MSI_SET_GRP1_ENABLE_OFFSET + |
| 323 | i * PCIE_MSI_SET_OFFSET; |
| 324 | msi_set->enable[2] = base + PCIE_MSI_SET_GRP2_ENABLE_OFFSET + |
| 325 | i * PCIE_MSI_SET_GRP2_OFFSET; |
| 326 | msi_set->enable[3] = base + PCIE_MSI_SET_GRP3_ENABLE_OFFSET + |
| 327 | i * PCIE_MSI_SET_GRP3_OFFSET; |
| 328 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 329 | msi_set->msg_addr = port->reg_base + PCIE_MSI_SET_BASE_REG + |
| 330 | i * PCIE_MSI_SET_OFFSET; |
| 331 | |
| 332 | /* Configure the MSI capture address */ |
| 333 | writel_relaxed(lower_32_bits(msi_set->msg_addr), msi_set->base); |
| 334 | writel_relaxed(upper_32_bits(msi_set->msg_addr), |
| 335 | port->base + PCIE_MSI_SET_ADDR_HI_BASE + |
| 336 | i * PCIE_MSI_SET_ADDR_HI_OFFSET); |
| 337 | } |
| 338 | |
| 339 | val = readl_relaxed(port->base + PCIE_MSI_SET_ENABLE_REG); |
| 340 | val |= PCIE_MSI_SET_ENABLE; |
| 341 | writel_relaxed(val, port->base + PCIE_MSI_SET_ENABLE_REG); |
| 342 | |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 343 | val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG); |
| 344 | val |= PCIE_MSI_ENABLE; |
| 345 | writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG); |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 346 | } |
| 347 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 348 | static int mtk_pcie_startup_port(struct mtk_pcie_port *port) |
| 349 | { |
| 350 | struct resource_entry *entry; |
| 351 | struct pci_host_bridge *host = pci_host_bridge_from_priv(port); |
| 352 | unsigned int table_index = 0; |
| 353 | int err; |
| 354 | u32 val; |
| 355 | |
| 356 | /* Set as RC mode */ |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 357 | val = readl_relaxed(port->base + PCIE_SETTING_REG); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 358 | val |= PCIE_RC_MODE; |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 359 | writel_relaxed(val, port->base + PCIE_SETTING_REG); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 360 | |
developer | ca1c6b2 | 2023-04-26 19:51:06 +0800 | [diff] [blame] | 361 | /* Set link width*/ |
| 362 | val = readl_relaxed(port->base + PCIE_SETTING_REG); |
| 363 | if (port->max_link_width == 1) { |
| 364 | val &= ~GENMASK(11, 8); |
| 365 | } else if (port->max_link_width == 2) { |
| 366 | val &= ~GENMASK(11, 8); |
| 367 | val |= BIT(8); |
| 368 | } |
| 369 | writel_relaxed(val, port->base + PCIE_SETTING_REG); |
| 370 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 371 | /* Set class code */ |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 372 | val = readl_relaxed(port->base + PCIE_PCI_IDS_1); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 373 | val &= ~GENMASK(31, 8); |
| 374 | val |= PCI_CLASS(PCI_CLASS_BRIDGE_PCI << 8); |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 375 | writel_relaxed(val, port->base + PCIE_PCI_IDS_1); |
| 376 | |
| 377 | /* Mask all INTx interrupts */ |
| 378 | val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG); |
| 379 | val &= ~PCIE_INTX_ENABLE; |
| 380 | writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 381 | |
| 382 | /* Assert all reset signals */ |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 383 | val = readl_relaxed(port->base + PCIE_RST_CTRL_REG); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 384 | val |= PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB; |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 385 | writel_relaxed(val, port->base + PCIE_RST_CTRL_REG); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 386 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 387 | /* |
| 388 | * Described in PCIe CEM specification setctions 2.2 (PERST# Signal) |
| 389 | * and 2.2.1 (Initial Power-Up (G3 to S0)). |
| 390 | * The deassertion of PERST# should be delayed 100ms (TPVPERL) |
| 391 | * for the power and clock to become stable. |
| 392 | */ |
| 393 | msleep(100); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 394 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 395 | /* De-assert reset signals */ |
| 396 | val &= ~(PCIE_MAC_RSTB | PCIE_PHY_RSTB | PCIE_BRG_RSTB | PCIE_PE_RSTB); |
| 397 | writel_relaxed(val, port->base + PCIE_RST_CTRL_REG); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 398 | |
| 399 | /* Check if the link is up or not */ |
| 400 | err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_REG, val, |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 401 | !!(val & PCIE_PORT_LINKUP), 20, |
| 402 | PCI_PM_D3COLD_WAIT * USEC_PER_MSEC); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 403 | if (err) { |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 404 | val = readl_relaxed(port->base + PCIE_LTSSM_STATUS_REG); |
| 405 | dev_err(port->dev, "PCIe link down, ltssm reg val: %#x\n", val); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 406 | return err; |
| 407 | } |
| 408 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 409 | mtk_pcie_enable_msi(port); |
| 410 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 411 | /* Set PCIe translation windows */ |
| 412 | resource_list_for_each_entry(entry, &host->windows) { |
| 413 | struct resource *res = entry->res; |
| 414 | unsigned long type = resource_type(res); |
| 415 | resource_size_t cpu_addr; |
| 416 | resource_size_t pci_addr; |
| 417 | resource_size_t size; |
| 418 | const char *range_type; |
| 419 | |
| 420 | if (type == IORESOURCE_IO) { |
| 421 | cpu_addr = pci_pio_to_address(res->start); |
| 422 | range_type = "IO"; |
| 423 | } else if (type == IORESOURCE_MEM) { |
| 424 | cpu_addr = res->start; |
| 425 | range_type = "MEM"; |
| 426 | } else { |
| 427 | continue; |
| 428 | } |
| 429 | |
| 430 | pci_addr = res->start - entry->offset; |
| 431 | size = resource_size(res); |
| 432 | err = mtk_pcie_set_trans_table(port, cpu_addr, pci_addr, size, |
| 433 | type, table_index); |
| 434 | if (err) |
| 435 | return err; |
| 436 | |
| 437 | dev_dbg(port->dev, "set %s trans window[%d]: cpu_addr = %#llx, pci_addr = %#llx, size = %#llx\n", |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 438 | range_type, table_index, (unsigned long long)cpu_addr, |
| 439 | (unsigned long long)pci_addr, (unsigned long long)size); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 440 | |
| 441 | table_index++; |
| 442 | } |
| 443 | |
| 444 | return 0; |
| 445 | } |
| 446 | |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 447 | static struct mtk_pcie_irq *mtk_msi_hwirq_get_irqs(struct mtk_pcie_port *port, unsigned long hwirq) |
| 448 | { |
| 449 | int i; |
| 450 | |
| 451 | for (i = 0; i < port->num_irqs; i++) |
| 452 | if (port->irqs[i].mapped_table & BIT(hwirq)) |
| 453 | return &port->irqs[i]; |
| 454 | |
| 455 | return NULL; |
| 456 | } |
| 457 | |
| 458 | static struct mtk_pcie_irq *mtk_msi_irq_get_irqs(struct mtk_pcie_port *port, unsigned int irq) |
| 459 | { |
| 460 | int i; |
| 461 | |
| 462 | for (i = 0; i < port->num_irqs; i++) |
| 463 | if (port->irqs[i].irq == irq) |
| 464 | return &port->irqs[i]; |
| 465 | |
| 466 | return NULL; |
| 467 | } |
| 468 | |
| 469 | static int mtk_pcie_msi_set_affinity(struct irq_data *data, |
developer | 63dcf01 | 2021-09-02 10:14:03 +0800 | [diff] [blame] | 470 | const struct cpumask *mask, bool force) |
| 471 | { |
| 472 | struct mtk_pcie_port *port = data->domain->host_data; |
| 473 | struct irq_data *port_data; |
| 474 | struct irq_chip *port_chip; |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 475 | struct mtk_pcie_irq *irqs; |
| 476 | unsigned long hwirq; |
| 477 | int ret; |
developer | 63dcf01 | 2021-09-02 10:14:03 +0800 | [diff] [blame] | 478 | |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 479 | hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET; |
| 480 | irqs = mtk_msi_hwirq_get_irqs(port, hwirq); |
| 481 | if (IS_ERR_OR_NULL(irqs)) |
| 482 | return -EINVAL; |
developer | 63dcf01 | 2021-09-02 10:14:03 +0800 | [diff] [blame] | 483 | |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 484 | port_data = irq_get_irq_data(irqs->irq); |
developer | 63dcf01 | 2021-09-02 10:14:03 +0800 | [diff] [blame] | 485 | port_chip = irq_data_get_irq_chip(port_data); |
| 486 | if (!port_chip || !port_chip->irq_set_affinity) |
| 487 | return -EINVAL; |
| 488 | |
| 489 | ret = port_chip->irq_set_affinity(port_data, mask, force); |
| 490 | |
| 491 | irq_data_update_effective_affinity(data, mask); |
| 492 | |
| 493 | return ret; |
| 494 | } |
| 495 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 496 | static void mtk_pcie_msi_irq_mask(struct irq_data *data) |
| 497 | { |
| 498 | pci_msi_mask_irq(data); |
| 499 | irq_chip_mask_parent(data); |
| 500 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 501 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 502 | static void mtk_pcie_msi_irq_unmask(struct irq_data *data) |
| 503 | { |
| 504 | pci_msi_unmask_irq(data); |
| 505 | irq_chip_unmask_parent(data); |
| 506 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 507 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 508 | static struct irq_chip mtk_msi_irq_chip = { |
| 509 | .irq_ack = irq_chip_ack_parent, |
| 510 | .irq_mask = mtk_pcie_msi_irq_mask, |
| 511 | .irq_unmask = mtk_pcie_msi_irq_unmask, |
| 512 | .name = "MSI", |
| 513 | }; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 514 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 515 | static struct msi_domain_info mtk_msi_domain_info = { |
| 516 | .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | |
| 517 | MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI), |
| 518 | .chip = &mtk_msi_irq_chip, |
| 519 | }; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 520 | |
| 521 | static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) |
| 522 | { |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 523 | struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data); |
| 524 | struct mtk_pcie_port *port = data->domain->host_data; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 525 | unsigned long hwirq; |
| 526 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 527 | hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET; |
| 528 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 529 | msg->address_hi = upper_32_bits(msi_set->msg_addr); |
| 530 | msg->address_lo = lower_32_bits(msi_set->msg_addr); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 531 | msg->data = hwirq; |
| 532 | dev_dbg(port->dev, "msi#%#lx address_hi %#x address_lo %#x data %d\n", |
| 533 | hwirq, msg->address_hi, msg->address_lo, msg->data); |
| 534 | } |
| 535 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 536 | static void mtk_msi_bottom_irq_ack(struct irq_data *data) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 537 | { |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 538 | struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 539 | unsigned long hwirq; |
| 540 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 541 | hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET; |
| 542 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 543 | writel_relaxed(BIT(hwirq), msi_set->base + PCIE_MSI_SET_STATUS_OFFSET); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 544 | } |
| 545 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 546 | static void mtk_msi_bottom_irq_mask(struct irq_data *data) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 547 | { |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 548 | struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data); |
| 549 | struct mtk_pcie_port *port = data->domain->host_data; |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 550 | struct mtk_pcie_irq *irqs; |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 551 | unsigned long hwirq, flags; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 552 | u32 val; |
| 553 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 554 | hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET; |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 555 | irqs = mtk_msi_hwirq_get_irqs(port, hwirq); |
| 556 | if (IS_ERR_OR_NULL(irqs)) |
| 557 | return; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 558 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 559 | raw_spin_lock_irqsave(&port->irq_lock, flags); |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 560 | val = readl_relaxed(msi_set->enable[irqs->group]); |
| 561 | val &= ~BIT(hwirq); |
| 562 | writel_relaxed(val, msi_set->enable[irqs->group]); |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 563 | raw_spin_unlock_irqrestore(&port->irq_lock, flags); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 564 | } |
| 565 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 566 | static void mtk_msi_bottom_irq_unmask(struct irq_data *data) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 567 | { |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 568 | struct mtk_msi_set *msi_set = irq_data_get_irq_chip_data(data); |
| 569 | struct mtk_pcie_port *port = data->domain->host_data; |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 570 | struct mtk_pcie_irq *irqs; |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 571 | unsigned long hwirq, flags; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 572 | u32 val; |
| 573 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 574 | hwirq = data->hwirq % PCIE_MSI_IRQS_PER_SET; |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 575 | irqs = mtk_msi_hwirq_get_irqs(port, hwirq); |
| 576 | if (IS_ERR_OR_NULL(irqs)) |
| 577 | return; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 578 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 579 | raw_spin_lock_irqsave(&port->irq_lock, flags); |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 580 | val = readl_relaxed(msi_set->enable[irqs->group]); |
| 581 | val |= BIT(hwirq); |
| 582 | writel_relaxed(val, msi_set->enable[irqs->group]); |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 583 | raw_spin_unlock_irqrestore(&port->irq_lock, flags); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 584 | } |
| 585 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 586 | static struct irq_chip mtk_msi_bottom_irq_chip = { |
| 587 | .irq_ack = mtk_msi_bottom_irq_ack, |
| 588 | .irq_mask = mtk_msi_bottom_irq_mask, |
| 589 | .irq_unmask = mtk_msi_bottom_irq_unmask, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 590 | .irq_compose_msi_msg = mtk_compose_msi_msg, |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 591 | .irq_set_affinity = mtk_pcie_msi_set_affinity, |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 592 | .name = "MSI", |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 593 | }; |
| 594 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 595 | static int mtk_msi_bottom_domain_alloc(struct irq_domain *domain, |
| 596 | unsigned int virq, unsigned int nr_irqs, |
| 597 | void *arg) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 598 | { |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 599 | struct mtk_pcie_port *port = domain->host_data; |
| 600 | struct mtk_msi_set *msi_set; |
| 601 | int i, hwirq, set_idx; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 602 | |
| 603 | mutex_lock(&port->lock); |
| 604 | |
| 605 | hwirq = bitmap_find_free_region(port->msi_irq_in_use, PCIE_MSI_IRQS_NUM, |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 606 | order_base_2(nr_irqs)); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 607 | |
| 608 | mutex_unlock(&port->lock); |
| 609 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 610 | if (hwirq < 0) |
| 611 | return -ENOSPC; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 612 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 613 | set_idx = hwirq / PCIE_MSI_IRQS_PER_SET; |
| 614 | msi_set = &port->msi_sets[set_idx]; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 615 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 616 | for (i = 0; i < nr_irqs; i++) |
| 617 | irq_domain_set_info(domain, virq + i, hwirq + i, |
| 618 | &mtk_msi_bottom_irq_chip, msi_set, |
| 619 | handle_edge_irq, NULL, NULL); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 620 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 621 | return 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 622 | } |
| 623 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 624 | static void mtk_msi_bottom_domain_free(struct irq_domain *domain, |
| 625 | unsigned int virq, unsigned int nr_irqs) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 626 | { |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 627 | struct mtk_pcie_port *port = domain->host_data; |
| 628 | struct irq_data *data = irq_domain_get_irq_data(domain, virq); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 629 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 630 | mutex_lock(&port->lock); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 631 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 632 | bitmap_release_region(port->msi_irq_in_use, data->hwirq, |
| 633 | order_base_2(nr_irqs)); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 634 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 635 | mutex_unlock(&port->lock); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 636 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 637 | irq_domain_free_irqs_common(domain, virq, nr_irqs); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 638 | } |
| 639 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 640 | static const struct irq_domain_ops mtk_msi_bottom_domain_ops = { |
| 641 | .alloc = mtk_msi_bottom_domain_alloc, |
| 642 | .free = mtk_msi_bottom_domain_free, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 643 | }; |
| 644 | |
| 645 | static void mtk_intx_mask(struct irq_data *data) |
| 646 | { |
| 647 | struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 648 | unsigned long flags; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 649 | u32 val; |
| 650 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 651 | raw_spin_lock_irqsave(&port->irq_lock, flags); |
| 652 | val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 653 | val &= ~BIT(data->hwirq + PCIE_INTX_SHIFT); |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 654 | writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG); |
| 655 | raw_spin_unlock_irqrestore(&port->irq_lock, flags); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 656 | } |
| 657 | |
| 658 | static void mtk_intx_unmask(struct irq_data *data) |
| 659 | { |
| 660 | struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 661 | unsigned long flags; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 662 | u32 val; |
| 663 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 664 | raw_spin_lock_irqsave(&port->irq_lock, flags); |
| 665 | val = readl_relaxed(port->base + PCIE_INT_ENABLE_REG); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 666 | val |= BIT(data->hwirq + PCIE_INTX_SHIFT); |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 667 | writel_relaxed(val, port->base + PCIE_INT_ENABLE_REG); |
| 668 | raw_spin_unlock_irqrestore(&port->irq_lock, flags); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 669 | } |
| 670 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 671 | /** |
| 672 | * mtk_intx_eoi() - Clear INTx IRQ status at the end of interrupt |
| 673 | * @data: pointer to chip specific data |
| 674 | * |
| 675 | * As an emulated level IRQ, its interrupt status will remain |
| 676 | * until the corresponding de-assert message is received; hence that |
| 677 | * the status can only be cleared when the interrupt has been serviced. |
| 678 | */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 679 | static void mtk_intx_eoi(struct irq_data *data) |
| 680 | { |
| 681 | struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data); |
| 682 | unsigned long hwirq; |
| 683 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 684 | hwirq = data->hwirq + PCIE_INTX_SHIFT; |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 685 | writel_relaxed(BIT(hwirq), port->base + PCIE_INT_STATUS_REG); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 686 | } |
| 687 | |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 688 | static int mtk_pcie_intx_set_affinity(struct irq_data *data, |
| 689 | const struct cpumask *mask, bool force) |
| 690 | { |
| 691 | struct mtk_pcie_port *port = data->domain->host_data; |
| 692 | struct irq_data *port_data; |
| 693 | struct irq_chip *port_chip; |
| 694 | int ret; |
| 695 | |
| 696 | port_data = irq_get_irq_data(port->irq); |
| 697 | port_chip = irq_data_get_irq_chip(port_data); |
| 698 | if (!port_chip || !port_chip->irq_set_affinity) |
| 699 | return -EINVAL; |
| 700 | ret = port_chip->irq_set_affinity(port_data, mask, force); |
| 701 | irq_data_update_effective_affinity(data, mask); |
| 702 | return ret; |
| 703 | } |
| 704 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 705 | static struct irq_chip mtk_intx_irq_chip = { |
| 706 | .irq_mask = mtk_intx_mask, |
| 707 | .irq_unmask = mtk_intx_unmask, |
| 708 | .irq_eoi = mtk_intx_eoi, |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 709 | .irq_set_affinity = mtk_pcie_intx_set_affinity, |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 710 | .name = "INTx", |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 711 | }; |
| 712 | |
| 713 | static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq, |
| 714 | irq_hw_number_t hwirq) |
| 715 | { |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 716 | irq_set_chip_data(irq, domain->host_data); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 717 | irq_set_chip_and_handler_name(irq, &mtk_intx_irq_chip, |
| 718 | handle_fasteoi_irq, "INTx"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 719 | return 0; |
| 720 | } |
| 721 | |
| 722 | static const struct irq_domain_ops intx_domain_ops = { |
| 723 | .map = mtk_pcie_intx_map, |
| 724 | }; |
| 725 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 726 | static int mtk_pcie_init_irq_domains(struct mtk_pcie_port *port) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 727 | { |
| 728 | struct device *dev = port->dev; |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 729 | struct device_node *intc_node, *node = dev->of_node; |
| 730 | int ret; |
| 731 | |
| 732 | raw_spin_lock_init(&port->irq_lock); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 733 | |
| 734 | /* Setup INTx */ |
| 735 | intc_node = of_get_child_by_name(node, "interrupt-controller"); |
| 736 | if (!intc_node) { |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 737 | dev_err(dev, "missing interrupt-controller node\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 738 | return -ENODEV; |
| 739 | } |
| 740 | |
| 741 | port->intx_domain = irq_domain_add_linear(intc_node, PCI_NUM_INTX, |
| 742 | &intx_domain_ops, port); |
| 743 | if (!port->intx_domain) { |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 744 | dev_err(dev, "failed to create INTx IRQ domain\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 745 | return -ENODEV; |
| 746 | } |
| 747 | |
| 748 | /* Setup MSI */ |
| 749 | mutex_init(&port->lock); |
| 750 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 751 | port->msi_bottom_domain = irq_domain_add_linear(node, PCIE_MSI_IRQS_NUM, |
| 752 | &mtk_msi_bottom_domain_ops, port); |
| 753 | if (!port->msi_bottom_domain) { |
| 754 | dev_err(dev, "failed to create MSI bottom domain\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 755 | ret = -ENODEV; |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 756 | goto err_msi_bottom_domain; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 757 | } |
| 758 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 759 | port->msi_domain = pci_msi_create_irq_domain(dev->fwnode, |
| 760 | &mtk_msi_domain_info, |
| 761 | port->msi_bottom_domain); |
| 762 | if (!port->msi_domain) { |
| 763 | dev_err(dev, "failed to create MSI domain\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 764 | ret = -ENODEV; |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 765 | goto err_msi_domain; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 766 | } |
| 767 | |
| 768 | return 0; |
| 769 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 770 | err_msi_domain: |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 771 | irq_domain_remove(port->msi_bottom_domain); |
| 772 | err_msi_bottom_domain: |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 773 | irq_domain_remove(port->intx_domain); |
| 774 | |
| 775 | return ret; |
| 776 | } |
| 777 | |
| 778 | static void mtk_pcie_irq_teardown(struct mtk_pcie_port *port) |
| 779 | { |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 780 | int i; |
| 781 | |
| 782 | for (i = 0; i < port->num_irqs; i++) |
| 783 | irq_set_chained_handler_and_data(port->irqs[i].irq, NULL, NULL); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 784 | |
| 785 | if (port->intx_domain) |
| 786 | irq_domain_remove(port->intx_domain); |
| 787 | |
| 788 | if (port->msi_domain) |
| 789 | irq_domain_remove(port->msi_domain); |
| 790 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 791 | if (port->msi_bottom_domain) |
| 792 | irq_domain_remove(port->msi_bottom_domain); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 793 | |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 794 | for (i = 0; i < port->num_irqs; i++) |
| 795 | irq_dispose_mapping(port->irqs[i].irq); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 796 | } |
| 797 | |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 798 | static void mtk_pcie_msi_handler(struct irq_desc *desc, int set_idx) |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 799 | { |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 800 | struct mtk_pcie_port *port = irq_desc_get_handler_data(desc); |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 801 | struct mtk_msi_set *msi_set = &port->msi_sets[set_idx]; |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 802 | struct mtk_pcie_irq *irqs; |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 803 | unsigned long msi_enable, msi_status; |
| 804 | unsigned int virq; |
| 805 | irq_hw_number_t bit, hwirq; |
| 806 | |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 807 | irqs = mtk_msi_irq_get_irqs(port, irq_desc_get_irq(desc)); |
| 808 | if (IS_ERR_OR_NULL(irqs)) |
| 809 | return; |
| 810 | |
| 811 | msi_enable = readl_relaxed(msi_set->enable[irqs->group]); |
| 812 | msi_enable &= irqs->mapped_table; |
| 813 | if (!msi_enable) |
| 814 | return; |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 815 | |
| 816 | do { |
| 817 | msi_status = readl_relaxed(msi_set->base + |
| 818 | PCIE_MSI_SET_STATUS_OFFSET); |
| 819 | msi_status &= msi_enable; |
| 820 | if (!msi_status) |
| 821 | break; |
| 822 | |
| 823 | for_each_set_bit(bit, &msi_status, PCIE_MSI_IRQS_PER_SET) { |
| 824 | hwirq = bit + set_idx * PCIE_MSI_IRQS_PER_SET; |
| 825 | virq = irq_find_mapping(port->msi_bottom_domain, hwirq); |
| 826 | generic_handle_irq(virq); |
| 827 | } |
| 828 | } while (true); |
| 829 | } |
| 830 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 831 | static void mtk_pcie_irq_handler(struct irq_desc *desc) |
| 832 | { |
| 833 | struct mtk_pcie_port *port = irq_desc_get_handler_data(desc); |
| 834 | struct irq_chip *irqchip = irq_desc_get_chip(desc); |
| 835 | unsigned long status; |
| 836 | unsigned int virq; |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 837 | irq_hw_number_t irq_bit; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 838 | |
| 839 | chained_irq_enter(irqchip, desc); |
| 840 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 841 | status = readl_relaxed(port->base + PCIE_INT_STATUS_REG); |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 842 | |
| 843 | /* INTx handler */ |
| 844 | irq_bit = PCIE_INTX_SHIFT; |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 845 | for_each_set_bit_from(irq_bit, &status, PCI_NUM_INTX + |
| 846 | PCIE_INTX_SHIFT) { |
| 847 | virq = irq_find_mapping(port->intx_domain, |
| 848 | irq_bit - PCIE_INTX_SHIFT); |
| 849 | generic_handle_irq(virq); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 850 | } |
| 851 | |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 852 | /* Group MSI don't trigger INT_STATUS, need to check MSI_SET_STATUS */ |
| 853 | if (port->msi_group_type == group0_merge_msi) { |
| 854 | irq_bit = PCIE_MSI_SHIFT; |
| 855 | for_each_set_bit_from(irq_bit, &status, PCIE_MSI_SET_NUM + |
| 856 | PCIE_MSI_SHIFT) { |
| 857 | mtk_pcie_msi_handler(desc, irq_bit - PCIE_MSI_SHIFT); |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 858 | |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 859 | writel_relaxed(BIT(irq_bit), port->base + |
| 860 | PCIE_INT_STATUS_REG); |
| 861 | } |
| 862 | } else { |
| 863 | for (irq_bit = PCIE_MSI_SHIFT; irq_bit < (PCIE_MSI_SET_NUM + |
| 864 | PCIE_MSI_SHIFT); irq_bit++) { |
| 865 | mtk_pcie_msi_handler(desc, irq_bit - PCIE_MSI_SHIFT); |
| 866 | |
| 867 | writel_relaxed(BIT(irq_bit), port->base + |
| 868 | PCIE_INT_STATUS_REG); |
| 869 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 870 | } |
| 871 | |
| 872 | chained_irq_exit(irqchip, desc); |
| 873 | } |
| 874 | |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 875 | static int mtk_pcie_parse_msi(struct mtk_pcie_port *port) |
developer | 63dcf01 | 2021-09-02 10:14:03 +0800 | [diff] [blame] | 876 | { |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 877 | struct device *dev = port->dev; |
| 878 | struct device_node *node = dev->of_node; |
| 879 | struct platform_device *pdev = to_platform_device(dev); |
| 880 | const char *msi_type; |
| 881 | u32 mask_check = 0, *msimap; |
| 882 | int count, err, i; |
developer | 63dcf01 | 2021-09-02 10:14:03 +0800 | [diff] [blame] | 883 | |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 884 | /* Get MSI group type */ |
| 885 | port->msi_group_type = group0_merge_msi; |
| 886 | if (!of_property_read_string(node, "msi_type", &msi_type)) { |
| 887 | if (!strcmp(msi_type, "direct_msi")) |
| 888 | port->msi_group_type = group1_direct_msi; |
| 889 | if (!strcmp(msi_type, "binding_msi")) |
| 890 | port->msi_group_type = group_binding_msi; |
developer | 63dcf01 | 2021-09-02 10:14:03 +0800 | [diff] [blame] | 891 | } |
| 892 | |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 893 | port->num_irqs = platform_irq_count(pdev); |
| 894 | port->irqs = devm_kzalloc(dev, sizeof(struct mtk_pcie_irq) * port->num_irqs, |
| 895 | GFP_KERNEL); |
| 896 | if (!port->irqs) |
| 897 | return -ENOMEM; |
developer | 63dcf01 | 2021-09-02 10:14:03 +0800 | [diff] [blame] | 898 | |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 899 | /* Merge MSI don't need map table */ |
| 900 | if (port->msi_group_type == group0_merge_msi) { |
| 901 | port->irqs[0].group = 0; |
| 902 | port->irqs[0].mapped_table = GENMASK(31, 0); |
developer | 63dcf01 | 2021-09-02 10:14:03 +0800 | [diff] [blame] | 903 | |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 904 | return 0; |
| 905 | } |
developer | 63dcf01 | 2021-09-02 10:14:03 +0800 | [diff] [blame] | 906 | |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 907 | /* Parse MSI map table from dts */ |
| 908 | count = of_property_count_elems_of_size(node, "msi-map", sizeof(u32)); |
| 909 | if ((count <= 0) || (count / 2 > port->num_irqs)) |
| 910 | return -EINVAL; |
| 911 | msimap = devm_kzalloc(dev, sizeof(u32) * count, GFP_KERNEL); |
| 912 | if (!msimap) |
| 913 | return -ENOMEM; |
developer | 63dcf01 | 2021-09-02 10:14:03 +0800 | [diff] [blame] | 914 | |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 915 | err = of_property_read_u32_array(node, "msi-map", msimap, count); |
| 916 | if (err) |
| 917 | return err; |
| 918 | |
| 919 | for (i = 0; i < (count / 2); i++) { |
| 920 | if ((msimap[i * 2] >= PCIE_MSI_GROUP_NUM) || |
| 921 | (msimap[i * 2 + 1] & mask_check)) { |
| 922 | return -EINVAL; |
| 923 | } |
| 924 | |
| 925 | port->irqs[i].group = msimap[i * 2]; |
| 926 | port->irqs[i].mapped_table = msimap[i * 2 + 1]; |
| 927 | mask_check |= msimap[i * 2 + 1]; |
developer | 63dcf01 | 2021-09-02 10:14:03 +0800 | [diff] [blame] | 928 | } |
| 929 | |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 930 | return 0; |
developer | 63dcf01 | 2021-09-02 10:14:03 +0800 | [diff] [blame] | 931 | } |
| 932 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 933 | static int mtk_pcie_setup_irq(struct mtk_pcie_port *port) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 934 | { |
| 935 | struct device *dev = port->dev; |
| 936 | struct platform_device *pdev = to_platform_device(dev); |
developer | 63dcf01 | 2021-09-02 10:14:03 +0800 | [diff] [blame] | 937 | int err, i; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 938 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 939 | err = mtk_pcie_init_irq_domains(port); |
| 940 | if (err) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 941 | return err; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 942 | |
| 943 | port->irq = platform_get_irq(pdev, 0); |
| 944 | if (port->irq < 0) |
| 945 | return port->irq; |
| 946 | |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 947 | for (i = 0; i < port->num_irqs; i++) { |
| 948 | port->irqs[i].irq = platform_get_irq(pdev, i); |
| 949 | if (port->irqs[i].irq < 0) |
| 950 | return port->irqs[i].irq; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 951 | |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 952 | irq_set_chained_handler_and_data(port->irqs[i].irq, |
| 953 | mtk_pcie_irq_handler, port); |
developer | 63dcf01 | 2021-09-02 10:14:03 +0800 | [diff] [blame] | 954 | } |
| 955 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 956 | return 0; |
| 957 | } |
| 958 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 959 | static int mtk_pcie_parse_port(struct mtk_pcie_port *port) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 960 | { |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 961 | struct device *dev = port->dev; |
| 962 | struct pci_host_bridge *host = pci_host_bridge_from_priv(port); |
| 963 | struct platform_device *pdev = to_platform_device(dev); |
| 964 | struct list_head *windows = &host->windows; |
| 965 | struct resource *regs, *bus; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 966 | int ret; |
| 967 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 968 | ret = pci_parse_request_of_pci_ranges(dev, windows, &bus); |
| 969 | if (ret) { |
| 970 | dev_err(dev, "failed to parse pci ranges\n"); |
| 971 | return ret; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 972 | } |
| 973 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 974 | regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac"); |
| 975 | port->base = devm_ioremap_resource(dev, regs); |
| 976 | if (IS_ERR(port->base)) { |
| 977 | dev_err(dev, "failed to map register base\n"); |
| 978 | return PTR_ERR(port->base); |
| 979 | } |
| 980 | |
| 981 | port->reg_base = regs->start; |
| 982 | |
| 983 | port->phy_reset = devm_reset_control_get_optional_exclusive(dev, "phy"); |
| 984 | if (IS_ERR(port->phy_reset)) { |
| 985 | ret = PTR_ERR(port->phy_reset); |
| 986 | if (ret != -EPROBE_DEFER) |
| 987 | dev_err(dev, "failed to get PHY reset\n"); |
| 988 | |
| 989 | return ret; |
| 990 | } |
| 991 | |
| 992 | port->mac_reset = devm_reset_control_get_optional_exclusive(dev, "mac"); |
| 993 | if (IS_ERR(port->mac_reset)) { |
| 994 | ret = PTR_ERR(port->mac_reset); |
| 995 | if (ret != -EPROBE_DEFER) |
| 996 | dev_err(dev, "failed to get MAC reset\n"); |
| 997 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 998 | return ret; |
| 999 | } |
| 1000 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1001 | port->phy = devm_phy_optional_get(dev, "pcie-phy"); |
| 1002 | if (IS_ERR(port->phy)) { |
| 1003 | ret = PTR_ERR(port->phy); |
| 1004 | if (ret != -EPROBE_DEFER) |
| 1005 | dev_err(dev, "failed to get PHY\n"); |
| 1006 | |
| 1007 | return ret; |
| 1008 | } |
| 1009 | |
| 1010 | port->num_clks = devm_clk_bulk_get_all(dev, &port->clks); |
| 1011 | if (port->num_clks < 0) { |
| 1012 | dev_err(dev, "failed to get clocks\n"); |
| 1013 | return port->num_clks; |
| 1014 | } |
| 1015 | |
developer | ca1c6b2 | 2023-04-26 19:51:06 +0800 | [diff] [blame] | 1016 | port->max_link_width = of_pci_get_max_link_width(dev->of_node); |
| 1017 | if (port->max_link_width < 0) |
| 1018 | dev_err(dev, "failed to get max link width\n"); |
| 1019 | |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 1020 | ret = mtk_pcie_parse_msi(port); |
| 1021 | if (ret) { |
| 1022 | dev_err(dev, "failed to parse msi\n"); |
| 1023 | return ret; |
| 1024 | } |
| 1025 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1026 | return 0; |
| 1027 | } |
| 1028 | |
| 1029 | static int mtk_pcie_power_up(struct mtk_pcie_port *port) |
| 1030 | { |
| 1031 | struct device *dev = port->dev; |
| 1032 | int err; |
| 1033 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1034 | /* PHY power on and enable pipe clock */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1035 | reset_control_deassert(port->phy_reset); |
| 1036 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1037 | err = phy_init(port->phy); |
| 1038 | if (err) { |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1039 | dev_err(dev, "failed to initialize PHY\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1040 | goto err_phy_init; |
| 1041 | } |
| 1042 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1043 | err = phy_power_on(port->phy); |
| 1044 | if (err) { |
| 1045 | dev_err(dev, "failed to power on PHY\n"); |
| 1046 | goto err_phy_on; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1047 | } |
| 1048 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1049 | /* MAC power on and enable transaction layer clocks */ |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1050 | reset_control_deassert(port->mac_reset); |
| 1051 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1052 | pm_runtime_enable(dev); |
| 1053 | pm_runtime_get_sync(dev); |
| 1054 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1055 | err = clk_bulk_prepare_enable(port->num_clks, port->clks); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1056 | if (err) { |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1057 | dev_err(dev, "failed to enable clocks\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1058 | goto err_clk_init; |
| 1059 | } |
| 1060 | |
| 1061 | return 0; |
| 1062 | |
| 1063 | err_clk_init: |
| 1064 | pm_runtime_put_sync(dev); |
| 1065 | pm_runtime_disable(dev); |
| 1066 | reset_control_assert(port->mac_reset); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1067 | phy_power_off(port->phy); |
| 1068 | err_phy_on: |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1069 | phy_exit(port->phy); |
| 1070 | err_phy_init: |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1071 | reset_control_assert(port->phy_reset); |
| 1072 | |
| 1073 | return err; |
| 1074 | } |
| 1075 | |
| 1076 | static void mtk_pcie_power_down(struct mtk_pcie_port *port) |
| 1077 | { |
| 1078 | clk_bulk_disable_unprepare(port->num_clks, port->clks); |
| 1079 | |
| 1080 | pm_runtime_put_sync(port->dev); |
| 1081 | pm_runtime_disable(port->dev); |
| 1082 | reset_control_assert(port->mac_reset); |
| 1083 | |
| 1084 | phy_power_off(port->phy); |
| 1085 | phy_exit(port->phy); |
| 1086 | reset_control_assert(port->phy_reset); |
| 1087 | } |
| 1088 | |
| 1089 | static int mtk_pcie_setup(struct mtk_pcie_port *port) |
| 1090 | { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1091 | int err; |
| 1092 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1093 | err = mtk_pcie_parse_port(port); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1094 | if (err) |
| 1095 | return err; |
| 1096 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1097 | /* Don't touch the hardware registers before power up */ |
| 1098 | err = mtk_pcie_power_up(port); |
| 1099 | if (err) |
| 1100 | return err; |
| 1101 | |
| 1102 | /* Try link up */ |
| 1103 | err = mtk_pcie_startup_port(port); |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1104 | if (err) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1105 | goto err_setup; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1106 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1107 | err = mtk_pcie_setup_irq(port); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1108 | if (err) |
| 1109 | goto err_setup; |
| 1110 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1111 | return 0; |
| 1112 | |
| 1113 | err_setup: |
| 1114 | mtk_pcie_power_down(port); |
| 1115 | |
| 1116 | return err; |
| 1117 | } |
| 1118 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1119 | static int mtk_pcie_probe(struct platform_device *pdev) |
| 1120 | { |
| 1121 | struct device *dev = &pdev->dev; |
| 1122 | struct mtk_pcie_port *port; |
| 1123 | struct pci_host_bridge *host; |
| 1124 | int err; |
| 1125 | |
| 1126 | host = devm_pci_alloc_host_bridge(dev, sizeof(*port)); |
| 1127 | if (!host) |
| 1128 | return -ENOMEM; |
| 1129 | |
| 1130 | port = pci_host_bridge_priv(host); |
| 1131 | |
| 1132 | port->dev = dev; |
| 1133 | platform_set_drvdata(pdev, port); |
| 1134 | |
| 1135 | err = mtk_pcie_setup(port); |
| 1136 | if (err) |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1137 | return err; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1138 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1139 | host->dev.parent = port->dev; |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1140 | host->ops = &mtk_pcie_ops; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1141 | host->map_irq = of_irq_parse_and_map_pci; |
| 1142 | host->swizzle_irq = pci_common_swizzle; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1143 | host->sysdata = port; |
| 1144 | |
| 1145 | err = pci_host_probe(host); |
| 1146 | if (err) { |
| 1147 | mtk_pcie_irq_teardown(port); |
| 1148 | mtk_pcie_power_down(port); |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1149 | return err; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1150 | } |
| 1151 | |
| 1152 | return 0; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1153 | } |
| 1154 | |
| 1155 | static int mtk_pcie_remove(struct platform_device *pdev) |
| 1156 | { |
| 1157 | struct mtk_pcie_port *port = platform_get_drvdata(pdev); |
| 1158 | struct pci_host_bridge *host = pci_host_bridge_from_priv(port); |
| 1159 | |
| 1160 | pci_lock_rescan_remove(); |
| 1161 | pci_stop_root_bus(host->bus); |
| 1162 | pci_remove_root_bus(host->bus); |
| 1163 | pci_unlock_rescan_remove(); |
| 1164 | |
| 1165 | mtk_pcie_irq_teardown(port); |
| 1166 | mtk_pcie_power_down(port); |
| 1167 | |
| 1168 | return 0; |
| 1169 | } |
| 1170 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1171 | static void __maybe_unused mtk_pcie_irq_save(struct mtk_pcie_port *port) |
| 1172 | { |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 1173 | int i, n; |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1174 | |
| 1175 | raw_spin_lock(&port->irq_lock); |
| 1176 | |
| 1177 | port->saved_irq_state = readl_relaxed(port->base + PCIE_INT_ENABLE_REG); |
| 1178 | |
| 1179 | for (i = 0; i < PCIE_MSI_SET_NUM; i++) { |
| 1180 | struct mtk_msi_set *msi_set = &port->msi_sets[i]; |
| 1181 | |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 1182 | for (n = 0; n < PCIE_MSI_GROUP_NUM; n++) |
| 1183 | msi_set->saved_irq_state[n] = readl_relaxed( |
| 1184 | msi_set->enable[n]); |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1185 | } |
| 1186 | |
| 1187 | raw_spin_unlock(&port->irq_lock); |
| 1188 | } |
| 1189 | |
| 1190 | static void __maybe_unused mtk_pcie_irq_restore(struct mtk_pcie_port *port) |
| 1191 | { |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 1192 | int i, n; |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1193 | |
| 1194 | raw_spin_lock(&port->irq_lock); |
| 1195 | |
| 1196 | writel_relaxed(port->saved_irq_state, port->base + PCIE_INT_ENABLE_REG); |
| 1197 | |
| 1198 | for (i = 0; i < PCIE_MSI_SET_NUM; i++) { |
| 1199 | struct mtk_msi_set *msi_set = &port->msi_sets[i]; |
| 1200 | |
developer | 8adc733 | 2022-11-03 16:05:20 +0800 | [diff] [blame] | 1201 | for (n = 0; n < PCIE_MSI_GROUP_NUM; n++) |
| 1202 | writel_relaxed(msi_set->saved_irq_state[n], |
| 1203 | msi_set->enable[n]); |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1204 | } |
| 1205 | |
| 1206 | raw_spin_unlock(&port->irq_lock); |
| 1207 | } |
| 1208 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1209 | static int __maybe_unused mtk_pcie_turn_off_link(struct mtk_pcie_port *port) |
| 1210 | { |
| 1211 | u32 val; |
| 1212 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1213 | val = readl_relaxed(port->base + PCIE_ICMD_PM_REG); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1214 | val |= PCIE_TURN_OFF_LINK; |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1215 | writel_relaxed(val, port->base + PCIE_ICMD_PM_REG); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1216 | |
| 1217 | /* Check the link is L2 */ |
| 1218 | return readl_poll_timeout(port->base + PCIE_LTSSM_STATUS_REG, val, |
| 1219 | (PCIE_LTSSM_STATE(val) == |
| 1220 | PCIE_LTSSM_STATE_L2_IDLE), 20, |
| 1221 | 50 * USEC_PER_MSEC); |
| 1222 | } |
| 1223 | |
| 1224 | static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev) |
| 1225 | { |
| 1226 | struct mtk_pcie_port *port = dev_get_drvdata(dev); |
| 1227 | int err; |
| 1228 | u32 val; |
| 1229 | |
| 1230 | /* Trigger link to L2 state */ |
| 1231 | err = mtk_pcie_turn_off_link(port); |
| 1232 | if (err) { |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1233 | dev_err(port->dev, "cannot enter L2 state\n"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1234 | return err; |
| 1235 | } |
| 1236 | |
| 1237 | /* Pull down the PERST# pin */ |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1238 | val = readl_relaxed(port->base + PCIE_RST_CTRL_REG); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1239 | val |= PCIE_PE_RSTB; |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1240 | writel_relaxed(val, port->base + PCIE_RST_CTRL_REG); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1241 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1242 | dev_dbg(port->dev, "entered L2 states successfully"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1243 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1244 | mtk_pcie_irq_save(port); |
| 1245 | mtk_pcie_power_down(port); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1246 | |
| 1247 | return 0; |
| 1248 | } |
| 1249 | |
| 1250 | static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev) |
| 1251 | { |
| 1252 | struct mtk_pcie_port *port = dev_get_drvdata(dev); |
| 1253 | int err; |
| 1254 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1255 | err = mtk_pcie_power_up(port); |
| 1256 | if (err) |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1257 | return err; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1258 | |
| 1259 | err = mtk_pcie_startup_port(port); |
| 1260 | if (err) { |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1261 | mtk_pcie_power_down(port); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1262 | return err; |
| 1263 | } |
| 1264 | |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1265 | mtk_pcie_irq_restore(port); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1266 | |
| 1267 | return 0; |
| 1268 | } |
| 1269 | |
| 1270 | static const struct dev_pm_ops mtk_pcie_pm_ops = { |
| 1271 | SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq, |
| 1272 | mtk_pcie_resume_noirq) |
| 1273 | }; |
| 1274 | |
| 1275 | static const struct of_device_id mtk_pcie_of_match[] = { |
| 1276 | { .compatible = "mediatek,mt8192-pcie" }, |
developer | 44e30b0 | 2021-07-02 11:12:14 +0800 | [diff] [blame] | 1277 | { .compatible = "mediatek,mt7986-pcie" }, |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1278 | {}, |
| 1279 | }; |
| 1280 | |
| 1281 | static struct platform_driver mtk_pcie_driver = { |
| 1282 | .probe = mtk_pcie_probe, |
| 1283 | .remove = mtk_pcie_remove, |
| 1284 | .driver = { |
| 1285 | .name = "mtk-pcie", |
| 1286 | .of_match_table = mtk_pcie_of_match, |
| 1287 | .pm = &mtk_pcie_pm_ops, |
| 1288 | }, |
| 1289 | }; |
| 1290 | |
| 1291 | module_platform_driver(mtk_pcie_driver); |
| 1292 | MODULE_LICENSE("GPL v2"); |