developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 1 | From 96af4d1381b43bafba252d38c2a344f1011de638 Mon Sep 17 00:00:00 2001 |
| 2 | From: Sam Shih <sam.shih@mediatek.com> |
| 3 | Date: Fri, 2 Jun 2023 13:06:23 +0800 |
| 4 | Subject: [PATCH] |
| 5 | [adv-feature][999-2503-cpufreq-mtk-vbining-add-mt7988-support.patch] |
| 6 | |
| 7 | --- |
| 8 | drivers/cpufreq/mediatek-cpufreq.c | 22 ++++++++++++++++++++++ |
| 9 | 1 file changed, 22 insertions(+) |
| 10 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 11 | diff --git a/drivers/cpufreq/mediatek-cpufreq.c b/drivers/cpufreq/mediatek-cpufreq.c |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 12 | index b23b6d2b4..c22945100 100644 |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 13 | --- a/drivers/cpufreq/mediatek-cpufreq.c |
| 14 | +++ b/drivers/cpufreq/mediatek-cpufreq.c |
| 15 | @@ -15,6 +15,7 @@ |
| 16 | #include <linux/regulator/consumer.h> |
| 17 | #include <linux/slab.h> |
| 18 | #include <linux/thermal.h> |
| 19 | +#include <linux/nvmem-consumer.h> |
| 20 | |
| 21 | #define MIN_VOLT_SHIFT (100000) |
| 22 | #define MAX_VOLT_SHIFT (200000) |
| 23 | @@ -539,6 +540,11 @@ static int mtk_cpufreq_init(struct cpufreq_policy *policy) |
| 24 | struct mtk_cpu_dvfs_info *info; |
| 25 | struct cpufreq_frequency_table *freq_table; |
| 26 | int ret; |
| 27 | + int target_vproc; |
developer | 5951563 | 2022-10-15 16:55:26 +0800 | [diff] [blame] | 28 | + u8 reg_val; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 29 | + struct nvmem_cell *cell; |
| 30 | + size_t len; |
developer | 5951563 | 2022-10-15 16:55:26 +0800 | [diff] [blame] | 31 | + u8 *buf; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 32 | |
| 33 | info = mtk_cpu_dvfs_info_lookup(policy->cpu); |
| 34 | if (!info) { |
| 35 | @@ -547,6 +553,22 @@ static int mtk_cpufreq_init(struct cpufreq_policy *policy) |
| 36 | return -EINVAL; |
| 37 | } |
| 38 | |
| 39 | + cell = nvmem_cell_get(info->cpu_dev, "calibration-data"); |
| 40 | + if (!IS_ERR(cell)) { |
developer | 5951563 | 2022-10-15 16:55:26 +0800 | [diff] [blame] | 41 | + buf = (u8 *)nvmem_cell_read(cell, &len); |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 42 | + nvmem_cell_put(cell); |
| 43 | + if (!IS_ERR(buf)) { |
| 44 | + reg_val = buf[0] & 0x1f; |
| 45 | + pr_debug("%s: read vbinning value: %d\n", __func__, reg_val); |
| 46 | + if (reg_val > 0) { |
| 47 | + target_vproc = 850000 + reg_val * 10000; |
| 48 | + dev_pm_opp_remove(info->cpu_dev, 1800000000); |
| 49 | + dev_pm_opp_add(info->cpu_dev, 1800000000, target_vproc); |
| 50 | + } |
| 51 | + kfree(buf); |
| 52 | + } |
| 53 | + } |
| 54 | + |
| 55 | ret = dev_pm_opp_init_cpufreq_table(info->cpu_dev, &freq_table); |
| 56 | if (ret) { |
| 57 | pr_err("failed to init cpufreq table for cpu%d: %d\n", |
developer | 5d148cb | 2023-06-02 13:08:11 +0800 | [diff] [blame] | 58 | -- |
| 59 | 2.34.1 |
| 60 | |