| commit | 5951563fa1101af485ea46b239fe14de87b8443c | [log] [tgz] |
|---|---|---|
| author | developer <developer@mediatek.com> | Sat Oct 15 16:55:26 2022 +0800 |
| committer | developer <developer@mediatek.com> | Mon Oct 17 20:54:29 2022 +0800 |
| tree | dc9218d15165f15270a0fe209c94436bf98a5a2f | |
| parent | 4323f7e10b01d75bb0108c7282abfbb597c0f936 [diff] [blame] |
[][kernel][mt7988][cpufreq][change u32 variable to u8] [Description] Change u32 variable to u8, we only need read efuse register low 8 bit, u8 variable is enough [Release-log] N/A Change-Id: I2aaeb2b7a42183bf529a16b280bf6ce7b24aa8d0 Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/6637744 Build: srv_hbgsm110
diff --git a/target/linux/mediatek/patches-5.4/0007-cpufreq-mtk-vbining-add-mt7988-support.patch b/target/linux/mediatek/patches-5.4/0007-cpufreq-mtk-vbining-add-mt7988-support.patch index 8e99118..aa31f22 100644 --- a/target/linux/mediatek/patches-5.4/0007-cpufreq-mtk-vbining-add-mt7988-support.patch +++ b/target/linux/mediatek/patches-5.4/0007-cpufreq-mtk-vbining-add-mt7988-support.patch
@@ -15,10 +15,10 @@ struct cpufreq_frequency_table *freq_table; int ret; + int target_vproc; -+ u32 reg_val; ++ u8 reg_val; + struct nvmem_cell *cell; + size_t len; -+ u32 *buf; ++ u8 *buf; info = mtk_cpu_dvfs_info_lookup(policy->cpu); if (!info) { @@ -28,7 +28,7 @@ + cell = nvmem_cell_get(info->cpu_dev, "calibration-data"); + if (!IS_ERR(cell)) { -+ buf = (u32 *)nvmem_cell_read(cell, &len); ++ buf = (u8 *)nvmem_cell_read(cell, &len); + nvmem_cell_put(cell); + if (!IS_ERR(buf)) { + reg_val = buf[0] & 0x1f;