blob: c914bc05f7cc203a554d84ca46ccc228d7376420 [file] [log] [blame]
developerfd40db22021-04-29 10:08:25 +08001/*
2 * Copyright (C) 2018 MediaTek Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
14 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
15 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
16 */
17
18#include <linux/trace_seq.h>
19#include <linux/seq_file.h>
20#include <linux/proc_fs.h>
21#include <linux/u64_stats_sync.h>
22#include <linux/dma-mapping.h>
23#include <linux/netdevice.h>
24#include <linux/ctype.h>
25#include <linux/debugfs.h>
26#include <linux/of_mdio.h>
developer089e8852022-09-28 14:43:46 +080027#include <linux/of_address.h>
developerfd40db22021-04-29 10:08:25 +080028
29#include "mtk_eth_soc.h"
30#include "mtk_eth_dbg.h"
developer8051e042022-04-08 13:26:36 +080031#include "mtk_eth_reset.h"
developerfd40db22021-04-29 10:08:25 +080032
developer77d03a72021-06-06 00:06:00 +080033u32 hw_lro_agg_num_cnt[MTK_HW_LRO_RING_NUM][MTK_HW_LRO_MAX_AGG_CNT + 1];
34u32 hw_lro_agg_size_cnt[MTK_HW_LRO_RING_NUM][16];
35u32 hw_lro_tot_agg_cnt[MTK_HW_LRO_RING_NUM];
36u32 hw_lro_tot_flush_cnt[MTK_HW_LRO_RING_NUM];
37u32 hw_lro_agg_flush_cnt[MTK_HW_LRO_RING_NUM];
38u32 hw_lro_age_flush_cnt[MTK_HW_LRO_RING_NUM];
39u32 hw_lro_seq_flush_cnt[MTK_HW_LRO_RING_NUM];
40u32 hw_lro_timestamp_flush_cnt[MTK_HW_LRO_RING_NUM];
41u32 hw_lro_norule_flush_cnt[MTK_HW_LRO_RING_NUM];
42u32 mtk_hwlro_stats_ebl;
43static struct proc_dir_entry *proc_hw_lro_stats, *proc_hw_lro_auto_tlb;
44typedef int (*mtk_lro_dbg_func) (int par);
45
developerfd40db22021-04-29 10:08:25 +080046struct mtk_eth_debug {
developer089e8852022-09-28 14:43:46 +080047 struct dentry *root;
48 void __iomem *base;
49 int direct_access;
developerfd40db22021-04-29 10:08:25 +080050};
51
52struct mtk_eth *g_eth;
53
54struct mtk_eth_debug eth_debug;
55
developer089e8852022-09-28 14:43:46 +080056int mt798x_iomap(void)
57{
58 struct device_node *np = NULL;
59
60 np = of_find_node_by_name(NULL, "switch0");
61 if (np) {
62 eth_debug.base = of_iomap(np, 0);
63 if (!eth_debug.base) {
64 pr_err("of_iomap failed\n");
65 of_node_put(np);
66 return -ENOMEM;
67 }
68
69 of_node_put(np);
70 eth_debug.direct_access = 1;
71 }
72
73 return 0;
74}
75
76int mt798x_iounmap(void)
77{
78 eth_debug.direct_access = 0;
79 if (eth_debug.base)
80 iounmap(eth_debug.base);
81
82 return 0;
83}
84
developer3957a912021-05-13 16:44:31 +080085void mt7530_mdio_w32(struct mtk_eth *eth, u16 reg, u32 val)
developerfd40db22021-04-29 10:08:25 +080086{
87 mutex_lock(&eth->mii_bus->mdio_lock);
88
developer089e8852022-09-28 14:43:46 +080089 if (eth_debug.direct_access)
90 __raw_writel(val, eth_debug.base + reg);
91 else {
92 _mtk_mdio_write(eth, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
93 _mtk_mdio_write(eth, 0x1f, (reg >> 2) & 0xf, val & 0xffff);
94 _mtk_mdio_write(eth, 0x1f, 0x10, val >> 16);
95 }
developerfd40db22021-04-29 10:08:25 +080096
97 mutex_unlock(&eth->mii_bus->mdio_lock);
98}
99
100u32 mt7530_mdio_r32(struct mtk_eth *eth, u32 reg)
101{
102 u16 high, low;
developer089e8852022-09-28 14:43:46 +0800103 u32 ret;
developerfd40db22021-04-29 10:08:25 +0800104
105 mutex_lock(&eth->mii_bus->mdio_lock);
106
developer089e8852022-09-28 14:43:46 +0800107 if (eth_debug.direct_access) {
108 ret = __raw_readl(eth_debug.base + reg);
109 mutex_unlock(&eth->mii_bus->mdio_lock);
110 return ret;
111 }
developerfd40db22021-04-29 10:08:25 +0800112 _mtk_mdio_write(eth, 0x1f, 0x1f, (reg >> 6) & 0x3ff);
113 low = _mtk_mdio_read(eth, 0x1f, (reg >> 2) & 0xf);
114 high = _mtk_mdio_read(eth, 0x1f, 0x10);
115
116 mutex_unlock(&eth->mii_bus->mdio_lock);
117
118 return (high << 16) | (low & 0xffff);
119}
120
121void mtk_switch_w32(struct mtk_eth *eth, u32 val, unsigned reg)
122{
123 mtk_w32(eth, val, reg + 0x10000);
124}
125EXPORT_SYMBOL(mtk_switch_w32);
126
127u32 mtk_switch_r32(struct mtk_eth *eth, unsigned reg)
128{
129 return mtk_r32(eth, reg + 0x10000);
130}
131EXPORT_SYMBOL(mtk_switch_r32);
132
133static int mtketh_debug_show(struct seq_file *m, void *private)
134{
135 struct mtk_eth *eth = m->private;
136 struct mtk_mac *mac = 0;
developer77d03a72021-06-06 00:06:00 +0800137 int i = 0;
developerfd40db22021-04-29 10:08:25 +0800138
139 for (i = 0 ; i < MTK_MAX_DEVS ; i++) {
140 if (!eth->mac[i] ||
141 of_phy_is_fixed_link(eth->mac[i]->of_node))
142 continue;
143 mac = eth->mac[i];
144#if 0 //FIXME
145 while (j < 30) {
146 d = _mtk_mdio_read(eth, mac->phy_dev->addr, j);
147
148 seq_printf(m, "phy=%d, reg=0x%08x, data=0x%08x\n",
149 mac->phy_dev->addr, j, d);
150 j++;
151 }
152#endif
153 }
154 return 0;
155}
156
157static int mtketh_debug_open(struct inode *inode, struct file *file)
158{
159 return single_open(file, mtketh_debug_show, inode->i_private);
160}
161
162static const struct file_operations mtketh_debug_fops = {
developer089e8852022-09-28 14:43:46 +0800163 .owner = THIS_MODULE,
developerfd40db22021-04-29 10:08:25 +0800164 .open = mtketh_debug_open,
165 .read = seq_read,
166 .llseek = seq_lseek,
167 .release = single_release,
168};
169
170static int mtketh_mt7530sw_debug_show(struct seq_file *m, void *private)
171{
172 struct mtk_eth *eth = m->private;
173 u32 offset, data;
174 int i;
175 struct mt7530_ranges {
176 u32 start;
177 u32 end;
178 } ranges[] = {
179 {0x0, 0xac},
180 {0x1000, 0x10e0},
181 {0x1100, 0x1140},
182 {0x1200, 0x1240},
183 {0x1300, 0x1340},
184 {0x1400, 0x1440},
185 {0x1500, 0x1540},
186 {0x1600, 0x1640},
187 {0x1800, 0x1848},
188 {0x1900, 0x1948},
189 {0x1a00, 0x1a48},
190 {0x1b00, 0x1b48},
191 {0x1c00, 0x1c48},
192 {0x1d00, 0x1d48},
193 {0x1e00, 0x1e48},
194 {0x1f60, 0x1ffc},
195 {0x2000, 0x212c},
196 {0x2200, 0x222c},
197 {0x2300, 0x232c},
198 {0x2400, 0x242c},
199 {0x2500, 0x252c},
200 {0x2600, 0x262c},
201 {0x3000, 0x3014},
202 {0x30c0, 0x30f8},
203 {0x3100, 0x3114},
204 {0x3200, 0x3214},
205 {0x3300, 0x3314},
206 {0x3400, 0x3414},
207 {0x3500, 0x3514},
208 {0x3600, 0x3614},
209 {0x4000, 0x40d4},
210 {0x4100, 0x41d4},
211 {0x4200, 0x42d4},
212 {0x4300, 0x43d4},
213 {0x4400, 0x44d4},
214 {0x4500, 0x45d4},
215 {0x4600, 0x46d4},
216 {0x4f00, 0x461c},
217 {0x7000, 0x7038},
218 {0x7120, 0x7124},
219 {0x7800, 0x7804},
220 {0x7810, 0x7810},
221 {0x7830, 0x7830},
222 {0x7a00, 0x7a7c},
223 {0x7b00, 0x7b04},
224 {0x7e00, 0x7e04},
225 {0x7ffc, 0x7ffc},
226 };
227
228 if (!mt7530_exist(eth))
229 return -EOPNOTSUPP;
230
231 if ((!eth->mac[0] || !of_phy_is_fixed_link(eth->mac[0]->of_node)) &&
232 (!eth->mac[1] || !of_phy_is_fixed_link(eth->mac[1]->of_node))) {
233 seq_puts(m, "no switch found\n");
234 return 0;
235 }
236
237 for (i = 0 ; i < ARRAY_SIZE(ranges) ; i++) {
238 for (offset = ranges[i].start;
239 offset <= ranges[i].end; offset += 4) {
240 data = mt7530_mdio_r32(eth, offset);
241 seq_printf(m, "mt7530 switch reg=0x%08x, data=0x%08x\n",
242 offset, data);
243 }
244 }
245
246 return 0;
247}
248
249static int mtketh_debug_mt7530sw_open(struct inode *inode, struct file *file)
250{
251 return single_open(file, mtketh_mt7530sw_debug_show, inode->i_private);
252}
253
254static const struct file_operations mtketh_debug_mt7530sw_fops = {
developer089e8852022-09-28 14:43:46 +0800255 .owner = THIS_MODULE,
developerfd40db22021-04-29 10:08:25 +0800256 .open = mtketh_debug_mt7530sw_open,
257 .read = seq_read,
258 .llseek = seq_lseek,
259 .release = single_release,
260};
261
262static ssize_t mtketh_mt7530sw_debugfs_write(struct file *file,
263 const char __user *ptr,
264 size_t len, loff_t *off)
265{
266 struct mtk_eth *eth = file->private_data;
267 char buf[32], *token, *p = buf;
developer8b6f2402022-11-28 13:42:34 +0800268 unsigned long reg, value, phy;
developerfd40db22021-04-29 10:08:25 +0800269 int ret;
270
271 if (!mt7530_exist(eth))
272 return -EOPNOTSUPP;
273
274 if (*off != 0)
275 return 0;
276
277 if (len > sizeof(buf) - 1)
278 len = sizeof(buf) - 1;
279
280 ret = strncpy_from_user(buf, ptr, len);
281 if (ret < 0)
282 return ret;
283 buf[len] = '\0';
284
285 token = strsep(&p, " ");
286 if (!token)
287 return -EINVAL;
288 if (kstrtoul(token, 16, (unsigned long *)&phy))
289 return -EINVAL;
290
291 token = strsep(&p, " ");
292 if (!token)
293 return -EINVAL;
294 if (kstrtoul(token, 16, (unsigned long *)&reg))
295 return -EINVAL;
296
297 token = strsep(&p, " ");
298 if (!token)
299 return -EINVAL;
300 if (kstrtoul(token, 16, (unsigned long *)&value))
301 return -EINVAL;
302
303 pr_info("%s:phy=%d, reg=0x%x, val=0x%x\n", __func__,
304 0x1f, reg, value);
305 mt7530_mdio_w32(eth, reg, value);
306 pr_info("%s:phy=%d, reg=0x%x, val=0x%x confirm..\n", __func__,
307 0x1f, reg, mt7530_mdio_r32(eth, reg));
308
309 return len;
310}
311
312static ssize_t mtketh_debugfs_write(struct file *file, const char __user *ptr,
313 size_t len, loff_t *off)
314{
315 struct mtk_eth *eth = file->private_data;
316 char buf[32], *token, *p = buf;
developer8b6f2402022-11-28 13:42:34 +0800317 unsigned long reg, value, phy;
developerfd40db22021-04-29 10:08:25 +0800318 int ret;
319
320 if (*off != 0)
321 return 0;
322
323 if (len > sizeof(buf) - 1)
324 len = sizeof(buf) - 1;
325
326 ret = strncpy_from_user(buf, ptr, len);
327 if (ret < 0)
328 return ret;
329 buf[len] = '\0';
330
331 token = strsep(&p, " ");
332 if (!token)
333 return -EINVAL;
334 if (kstrtoul(token, 16, (unsigned long *)&phy))
335 return -EINVAL;
336
337 token = strsep(&p, " ");
338
339 if (!token)
340 return -EINVAL;
341 if (kstrtoul(token, 16, (unsigned long *)&reg))
342 return -EINVAL;
343
344 token = strsep(&p, " ");
345
346 if (!token)
347 return -EINVAL;
348 if (kstrtoul(token, 16, (unsigned long *)&value))
349 return -EINVAL;
350
351 pr_info("%s:phy=%d, reg=0x%x, val=0x%x\n", __func__,
352 phy, reg, value);
353
354 _mtk_mdio_write(eth, phy, reg, value);
355
356 pr_info("%s:phy=%d, reg=0x%x, val=0x%x confirm..\n", __func__,
357 phy, reg, _mtk_mdio_read(eth, phy, reg));
358
359 return len;
360}
361
362static ssize_t mtketh_debugfs_reset(struct file *file, const char __user *ptr,
363 size_t len, loff_t *off)
364{
365 struct mtk_eth *eth = file->private_data;
developerbd42c172022-07-18 17:51:30 +0800366 char buf[8] = "";
367 int count = len;
368 unsigned long dbg_level = 0;
369
370 len = min(count, sizeof(buf) - 1);
371 if (copy_from_user(buf, ptr, len))
372 return -EFAULT;
373
374 buf[len] = '\0';
375 if (kstrtoul(buf, 0, &dbg_level))
376 return -EINVAL;
developerfd40db22021-04-29 10:08:25 +0800377
developerbd42c172022-07-18 17:51:30 +0800378 switch(dbg_level)
379 {
380 case 0:
381 if (atomic_read(&reset_lock) == 0)
382 atomic_inc(&reset_lock);
383 break;
384 case 1:
developer37482a42022-12-26 13:31:13 +0800385 if (atomic_read(&force) == 0) {
developerbd42c172022-07-18 17:51:30 +0800386 atomic_inc(&force);
developer37482a42022-12-26 13:31:13 +0800387 schedule_work(&eth->pending_work);
388 } else
389 pr_info(" device resetting !!!\n");
developerbd42c172022-07-18 17:51:30 +0800390 break;
391 case 2:
392 if (atomic_read(&reset_lock) == 1)
393 atomic_dec(&reset_lock);
394 break;
developer37482a42022-12-26 13:31:13 +0800395 case 3:
396 if (atomic_read(&force) == 0) {
397 atomic_inc(&force);
398 mtk_reset_flag = MTK_FE_STOP_TRAFFIC;
399 schedule_work(&eth->pending_work);
400 } else
401 pr_info(" device resetting !!!\n");
402 break;
developerbd42c172022-07-18 17:51:30 +0800403 default:
404 pr_info("Usage: echo [level] > /sys/kernel/debug/mtketh/reset\n");
developer37482a42022-12-26 13:31:13 +0800405 pr_info("Commands: [level]\n");
406 pr_info(" 0 disable reset\n");
407 pr_info(" 1 FE and WDMA reset\n");
developerbd42c172022-07-18 17:51:30 +0800408 pr_info(" 2 enable reset\n");
developer37482a42022-12-26 13:31:13 +0800409 pr_info(" 3 FE reset\n");
developerbd42c172022-07-18 17:51:30 +0800410 break;
411 }
412 return count;
developerfd40db22021-04-29 10:08:25 +0800413}
414
415static const struct file_operations fops_reg_w = {
416 .owner = THIS_MODULE,
417 .open = simple_open,
418 .write = mtketh_debugfs_write,
419 .llseek = noop_llseek,
420};
421
422static const struct file_operations fops_eth_reset = {
423 .owner = THIS_MODULE,
424 .open = simple_open,
425 .write = mtketh_debugfs_reset,
426 .llseek = noop_llseek,
427};
428
429static const struct file_operations fops_mt7530sw_reg_w = {
430 .owner = THIS_MODULE,
431 .open = simple_open,
432 .write = mtketh_mt7530sw_debugfs_write,
433 .llseek = noop_llseek,
434};
435
436void mtketh_debugfs_exit(struct mtk_eth *eth)
437{
438 debugfs_remove_recursive(eth_debug.root);
439}
440
441int mtketh_debugfs_init(struct mtk_eth *eth)
442{
443 int ret = 0;
444
445 eth_debug.root = debugfs_create_dir("mtketh", NULL);
446 if (!eth_debug.root) {
447 dev_notice(eth->dev, "%s:err at %d\n", __func__, __LINE__);
448 ret = -ENOMEM;
449 }
450
451 debugfs_create_file("phy_regs", S_IRUGO,
452 eth_debug.root, eth, &mtketh_debug_fops);
453 debugfs_create_file("phy_reg_w", S_IFREG | S_IWUSR,
454 eth_debug.root, eth, &fops_reg_w);
455 debugfs_create_file("reset", S_IFREG | S_IWUSR,
456 eth_debug.root, eth, &fops_eth_reset);
457 if (mt7530_exist(eth)) {
458 debugfs_create_file("mt7530sw_regs", S_IRUGO,
459 eth_debug.root, eth,
460 &mtketh_debug_mt7530sw_fops);
461 debugfs_create_file("mt7530sw_reg_w", S_IFREG | S_IWUSR,
462 eth_debug.root, eth,
463 &fops_mt7530sw_reg_w);
464 }
465 return ret;
466}
467
468void mii_mgr_read_combine(struct mtk_eth *eth, u32 phy_addr, u32 phy_register,
469 u32 *read_data)
470{
471 if (mt7530_exist(eth) && phy_addr == 31)
472 *read_data = mt7530_mdio_r32(eth, phy_register);
473
474 else
developer089e8852022-09-28 14:43:46 +0800475 *read_data = mdiobus_read(eth->mii_bus, phy_addr, phy_register);
developerfd40db22021-04-29 10:08:25 +0800476}
477
developer3957a912021-05-13 16:44:31 +0800478void mii_mgr_write_combine(struct mtk_eth *eth, u16 phy_addr, u16 phy_register,
developerfd40db22021-04-29 10:08:25 +0800479 u32 write_data)
480{
481 if (mt7530_exist(eth) && phy_addr == 31)
482 mt7530_mdio_w32(eth, phy_register, write_data);
483
484 else
developer089e8852022-09-28 14:43:46 +0800485 mdiobus_write(eth->mii_bus, phy_addr, phy_register, write_data);
developerfd40db22021-04-29 10:08:25 +0800486}
487
developer3957a912021-05-13 16:44:31 +0800488static void mii_mgr_read_cl45(struct mtk_eth *eth, u16 port, u16 devad, u16 reg, u16 *data)
developerfd40db22021-04-29 10:08:25 +0800489{
developer089e8852022-09-28 14:43:46 +0800490 *data = mdiobus_read(eth->mii_bus, port, mdiobus_c45_addr(devad, reg));
developerfd40db22021-04-29 10:08:25 +0800491}
492
developer3957a912021-05-13 16:44:31 +0800493static void mii_mgr_write_cl45(struct mtk_eth *eth, u16 port, u16 devad, u16 reg, u16 data)
developerfd40db22021-04-29 10:08:25 +0800494{
developer089e8852022-09-28 14:43:46 +0800495 mdiobus_write(eth->mii_bus, port, mdiobus_c45_addr(devad, reg), data);
developerfd40db22021-04-29 10:08:25 +0800496}
497
498int mtk_do_priv_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
499{
500 struct mtk_mac *mac = netdev_priv(dev);
501 struct mtk_eth *eth = mac->hw;
502 struct mtk_mii_ioctl_data mii;
503 struct mtk_esw_reg reg;
developerba2d1eb2021-05-25 19:26:45 +0800504 u16 val;
developerfd40db22021-04-29 10:08:25 +0800505
506 switch (cmd) {
507 case MTKETH_MII_READ:
508 if (copy_from_user(&mii, ifr->ifr_data, sizeof(mii)))
509 goto err_copy;
510 mii_mgr_read_combine(eth, mii.phy_id, mii.reg_num,
511 &mii.val_out);
512 if (copy_to_user(ifr->ifr_data, &mii, sizeof(mii)))
513 goto err_copy;
514
515 return 0;
516 case MTKETH_MII_WRITE:
517 if (copy_from_user(&mii, ifr->ifr_data, sizeof(mii)))
518 goto err_copy;
519 mii_mgr_write_combine(eth, mii.phy_id, mii.reg_num,
520 mii.val_in);
developerfd40db22021-04-29 10:08:25 +0800521 return 0;
522 case MTKETH_MII_READ_CL45:
523 if (copy_from_user(&mii, ifr->ifr_data, sizeof(mii)))
524 goto err_copy;
developer3957a912021-05-13 16:44:31 +0800525 mii_mgr_read_cl45(eth,
526 mdio_phy_id_prtad(mii.phy_id),
527 mdio_phy_id_devad(mii.phy_id),
528 mii.reg_num,
developerba2d1eb2021-05-25 19:26:45 +0800529 &val);
530 mii.val_out = val;
developerfd40db22021-04-29 10:08:25 +0800531 if (copy_to_user(ifr->ifr_data, &mii, sizeof(mii)))
532 goto err_copy;
533
534 return 0;
535 case MTKETH_MII_WRITE_CL45:
536 if (copy_from_user(&mii, ifr->ifr_data, sizeof(mii)))
537 goto err_copy;
developerba2d1eb2021-05-25 19:26:45 +0800538 val = mii.val_in;
developer3957a912021-05-13 16:44:31 +0800539 mii_mgr_write_cl45(eth,
540 mdio_phy_id_prtad(mii.phy_id),
541 mdio_phy_id_devad(mii.phy_id),
542 mii.reg_num,
developerba2d1eb2021-05-25 19:26:45 +0800543 val);
developerfd40db22021-04-29 10:08:25 +0800544 return 0;
545 case MTKETH_ESW_REG_READ:
546 if (!mt7530_exist(eth))
547 return -EOPNOTSUPP;
548 if (copy_from_user(&reg, ifr->ifr_data, sizeof(reg)))
549 goto err_copy;
550 if (reg.off > REG_ESW_MAX)
551 return -EINVAL;
552 reg.val = mtk_switch_r32(eth, reg.off);
553
554 if (copy_to_user(ifr->ifr_data, &reg, sizeof(reg)))
555 goto err_copy;
556
557 return 0;
558 case MTKETH_ESW_REG_WRITE:
559 if (!mt7530_exist(eth))
560 return -EOPNOTSUPP;
561 if (copy_from_user(&reg, ifr->ifr_data, sizeof(reg)))
562 goto err_copy;
563 if (reg.off > REG_ESW_MAX)
564 return -EINVAL;
565 mtk_switch_w32(eth, reg.val, reg.off);
566
567 return 0;
568 default:
569 break;
570 }
571
572 return -EOPNOTSUPP;
573err_copy:
574 return -EFAULT;
575}
576
developer089e8852022-09-28 14:43:46 +0800577static void gdm_reg_dump_v3(struct mtk_eth *eth, u32 gdm_id, u32 mib_base)
578{
579 pr_info("| GDMA%d_RX_GBCNT : %010u (Rx Good Bytes) |\n",
580 gdm_id, mtk_r32(eth, mib_base));
581 pr_info("| GDMA%d_RX_GPCNT : %010u (Rx Good Pkts) |\n",
582 gdm_id, mtk_r32(eth, mib_base + 0x08));
583 pr_info("| GDMA%d_RX_OERCNT : %010u (overflow error) |\n",
584 gdm_id, mtk_r32(eth, mib_base + 0x10));
585 pr_info("| GDMA%d_RX_FERCNT : %010u (FCS error) |\n",
586 gdm_id, mtk_r32(eth, mib_base + 0x14));
587 pr_info("| GDMA%d_RX_SERCNT : %010u (too short) |\n",
588 gdm_id, mtk_r32(eth, mib_base + 0x18));
589 pr_info("| GDMA%d_RX_LERCNT : %010u (too long) |\n",
590 gdm_id, mtk_r32(eth, mib_base + 0x1C));
591 pr_info("| GDMA%d_RX_CERCNT : %010u (checksum error) |\n",
592 gdm_id, mtk_r32(eth, mib_base + 0x20));
593 pr_info("| GDMA%d_RX_FCCNT : %010u (flow control) |\n",
594 gdm_id, mtk_r32(eth, mib_base + 0x24));
595 pr_info("| GDMA%d_RX_VDPCNT : %010u (VID drop) |\n",
596 gdm_id, mtk_r32(eth, mib_base + 0x28));
597 pr_info("| GDMA%d_RX_PFCCNT : %010u (priority flow control)\n",
598 gdm_id, mtk_r32(eth, mib_base + 0x2C));
599 pr_info("| GDMA%d_TX_GBCNT : %010u (Tx Good Bytes) |\n",
600 gdm_id, mtk_r32(eth, mib_base + 0x40));
601 pr_info("| GDMA%d_TX_GPCNT : %010u (Tx Good Pkts) |\n",
602 gdm_id, mtk_r32(eth, mib_base + 0x48));
603 pr_info("| GDMA%d_TX_SKIPCNT: %010u (abort count) |\n",
604 gdm_id, mtk_r32(eth, mib_base + 0x50));
605 pr_info("| GDMA%d_TX_COLCNT : %010u (collision count)|\n",
606 gdm_id, mtk_r32(eth, mib_base + 0x54));
607 pr_info("| GDMA%d_TX_OERCNT : %010u (overflow error) |\n",
608 gdm_id, mtk_r32(eth, mib_base + 0x58));
609 pr_info("| GDMA%d_TX_FCCNT : %010u (flow control) |\n",
610 gdm_id, mtk_r32(eth, mib_base + 0x60));
611 pr_info("| GDMA%d_TX_PFCCNT : %010u (priority flow control)\n",
612 gdm_id, mtk_r32(eth, mib_base + 0x64));
613 pr_info("| |\n");
614}
615
616static void gdm_reg_dump_v2(struct mtk_eth *eth, u32 gdm_id, u32 mib_base)
617{
618 pr_info("| GDMA%d_RX_GBCNT : %010u (Rx Good Bytes) |\n",
619 gdm_id, mtk_r32(eth, mib_base));
620 pr_info("| GDMA%d_RX_GPCNT : %010u (Rx Good Pkts) |\n",
621 gdm_id, mtk_r32(eth, mib_base + 0x08));
622 pr_info("| GDMA%d_RX_OERCNT : %010u (overflow error) |\n",
623 gdm_id, mtk_r32(eth, mib_base + 0x10));
624 pr_info("| GDMA%d_RX_FERCNT : %010u (FCS error) |\n",
625 gdm_id, mtk_r32(eth, mib_base + 0x14));
626 pr_info("| GDMA%d_RX_SERCNT : %010u (too short) |\n",
627 gdm_id, mtk_r32(eth, mib_base + 0x18));
628 pr_info("| GDMA%d_RX_LERCNT : %010u (too long) |\n",
629 gdm_id, mtk_r32(eth, mib_base + 0x1C));
630 pr_info("| GDMA%d_RX_CERCNT : %010u (checksum error) |\n",
631 gdm_id, mtk_r32(eth, mib_base + 0x20));
632 pr_info("| GDMA%d_RX_FCCNT : %010u (flow control) |\n",
633 gdm_id, mtk_r32(eth, mib_base + 0x24));
634 pr_info("| GDMA%d_TX_SKIPCNT: %010u (abort count) |\n",
635 gdm_id, mtk_r32(eth, mib_base + 0x28));
636 pr_info("| GDMA%d_TX_COLCNT : %010u (collision count) |\n",
637 gdm_id, mtk_r32(eth, mib_base + 0x2C));
638 pr_info("| GDMA%d_TX_GBCNT : %010u (Tx Good Bytes) |\n",
639 gdm_id, mtk_r32(eth, mib_base + 0x30));
640 pr_info("| GDMA%d_TX_GPCNT : %010u (Tx Good Pkts) |\n",
641 gdm_id, mtk_r32(eth, mib_base + 0x38));
642 pr_info("| |\n");
643}
644
645static void gdm_cnt_read(struct mtk_eth *eth)
646{
647 u32 i, mib_base;
648
649 pr_info("\n <<CPU>>\n");
650 pr_info(" |\n");
651 pr_info("+-----------------------------------------------+\n");
652 pr_info("| <<PSE>> |\n");
653 pr_info("+-----------------------------------------------+\n");
654 pr_info(" |\n");
655 pr_info("+-----------------------------------------------+\n");
656 pr_info("| <<GDMA>> |\n");
657
658 for (i = 0; i < MTK_MAC_COUNT; i++) {
659 mib_base = MTK_GDM1_TX_GBCNT + MTK_STAT_OFFSET * i;
660
661 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3))
662 gdm_reg_dump_v3(eth, i + 1, mib_base);
663 else
664 gdm_reg_dump_v2(eth, i + 1, mib_base);
665 }
666
667 pr_info("+-----------------------------------------------+\n");
668}
669
developer9ccff342022-10-13 18:28:54 +0800670void dump_each_port(struct seq_file *seq, struct mtk_eth *eth, u32 base)
671{
672 u32 pkt_cnt = 0;
673 int i = 0;
674
675 for (i = 0; i < 7; i++) {
676 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
677 if ((base == 0x402C) && (i == 6))
678 base = 0x408C;
679 else if ((base == 0x408C) && (i == 6))
680 base = 0x402C;
681 else
682 ;
683 }
684 pkt_cnt = mt7530_mdio_r32(eth, (base) + (i * 0x100));
685 seq_printf(seq, "%8u ", pkt_cnt);
686 }
687 seq_puts(seq, "\n");
688}
689
developerfd40db22021-04-29 10:08:25 +0800690int esw_cnt_read(struct seq_file *seq, void *v)
691{
692 unsigned int pkt_cnt = 0;
693 int i = 0;
694 struct mtk_eth *eth = g_eth;
developerfd40db22021-04-29 10:08:25 +0800695
developer089e8852022-09-28 14:43:46 +0800696 gdm_cnt_read(eth);
developerfd40db22021-04-29 10:08:25 +0800697
698 if (!mt7530_exist(eth))
699 return 0;
700
developer089e8852022-09-28 14:43:46 +0800701 mt798x_iomap();
702
developerfd40db22021-04-29 10:08:25 +0800703 seq_printf(seq, "===================== %8s %8s %8s %8s %8s %8s %8s\n",
704 "Port0", "Port1", "Port2", "Port3", "Port4", "Port5",
705 "Port6");
706 seq_puts(seq, "Tx Drop Packet :");
developer9ccff342022-10-13 18:28:54 +0800707 dump_each_port(seq, eth, 0x4000);
developerfd40db22021-04-29 10:08:25 +0800708 seq_puts(seq, "Tx CRC Error :");
developer9ccff342022-10-13 18:28:54 +0800709 dump_each_port(seq, eth, 0x4004);
developerfd40db22021-04-29 10:08:25 +0800710 seq_puts(seq, "Tx Unicast Packet :");
developer9ccff342022-10-13 18:28:54 +0800711 dump_each_port(seq, eth, 0x4008);
developerfd40db22021-04-29 10:08:25 +0800712 seq_puts(seq, "Tx Multicast Packet :");
developer9ccff342022-10-13 18:28:54 +0800713 dump_each_port(seq, eth, 0x400C);
developerfd40db22021-04-29 10:08:25 +0800714 seq_puts(seq, "Tx Broadcast Packet :");
developer9ccff342022-10-13 18:28:54 +0800715 dump_each_port(seq, eth, 0x4010);
developerfd40db22021-04-29 10:08:25 +0800716 seq_puts(seq, "Tx Collision Event :");
developer9ccff342022-10-13 18:28:54 +0800717 dump_each_port(seq, eth, 0x4014);
developerfd40db22021-04-29 10:08:25 +0800718 seq_puts(seq, "Tx Pause Packet :");
developer9ccff342022-10-13 18:28:54 +0800719 dump_each_port(seq, eth, 0x402C);
developerfd40db22021-04-29 10:08:25 +0800720 seq_puts(seq, "Rx Drop Packet :");
developer9ccff342022-10-13 18:28:54 +0800721 dump_each_port(seq, eth, 0x4060);
developerfd40db22021-04-29 10:08:25 +0800722 seq_puts(seq, "Rx Filtering Packet :");
developer9ccff342022-10-13 18:28:54 +0800723 dump_each_port(seq, eth, 0x4064);
developerfd40db22021-04-29 10:08:25 +0800724 seq_puts(seq, "Rx Unicast Packet :");
developer9ccff342022-10-13 18:28:54 +0800725 dump_each_port(seq, eth, 0x4068);
developerfd40db22021-04-29 10:08:25 +0800726 seq_puts(seq, "Rx Multicast Packet :");
developer9ccff342022-10-13 18:28:54 +0800727 dump_each_port(seq, eth, 0x406C);
developerfd40db22021-04-29 10:08:25 +0800728 seq_puts(seq, "Rx Broadcast Packet :");
developer9ccff342022-10-13 18:28:54 +0800729 dump_each_port(seq, eth, 0x4070);
developerfd40db22021-04-29 10:08:25 +0800730 seq_puts(seq, "Rx Alignment Error :");
developer9ccff342022-10-13 18:28:54 +0800731 dump_each_port(seq, eth, 0x4074);
developerfd40db22021-04-29 10:08:25 +0800732 seq_puts(seq, "Rx CRC Error :");
developer9ccff342022-10-13 18:28:54 +0800733 dump_each_port(seq, eth, 0x4078);
developerfd40db22021-04-29 10:08:25 +0800734 seq_puts(seq, "Rx Undersize Error :");
developer9ccff342022-10-13 18:28:54 +0800735 dump_each_port(seq, eth, 0x407C);
developerfd40db22021-04-29 10:08:25 +0800736 seq_puts(seq, "Rx Fragment Error :");
developer9ccff342022-10-13 18:28:54 +0800737 dump_each_port(seq, eth, 0x4080);
developerfd40db22021-04-29 10:08:25 +0800738 seq_puts(seq, "Rx Oversize Error :");
developer9ccff342022-10-13 18:28:54 +0800739 dump_each_port(seq, eth, 0x4084);
developerfd40db22021-04-29 10:08:25 +0800740 seq_puts(seq, "Rx Jabber Error :");
developer9ccff342022-10-13 18:28:54 +0800741 dump_each_port(seq, eth, 0x4088);
developerfd40db22021-04-29 10:08:25 +0800742 seq_puts(seq, "Rx Pause Packet :");
developer9ccff342022-10-13 18:28:54 +0800743 dump_each_port(seq, eth, 0x408C);
developerfd40db22021-04-29 10:08:25 +0800744 mt7530_mdio_w32(eth, 0x4fe0, 0xf0);
745 mt7530_mdio_w32(eth, 0x4fe0, 0x800000f0);
746
747 seq_puts(seq, "\n");
748
developer089e8852022-09-28 14:43:46 +0800749 mt798x_iounmap();
750
developerfd40db22021-04-29 10:08:25 +0800751 return 0;
752}
753
754static int switch_count_open(struct inode *inode, struct file *file)
755{
756 return single_open(file, esw_cnt_read, 0);
757}
758
759static const struct file_operations switch_count_fops = {
760 .owner = THIS_MODULE,
761 .open = switch_count_open,
762 .read = seq_read,
763 .llseek = seq_lseek,
764 .release = single_release
765};
766
developer8051e042022-04-08 13:26:36 +0800767static struct proc_dir_entry *proc_tx_ring, *proc_hwtx_ring, *proc_rx_ring;
developerfd40db22021-04-29 10:08:25 +0800768
769int tx_ring_read(struct seq_file *seq, void *v)
770{
developere9356982022-07-04 09:03:20 +0800771 struct mtk_eth *eth = g_eth;
developerfd40db22021-04-29 10:08:25 +0800772 struct mtk_tx_ring *ring = &g_eth->tx_ring;
developere9356982022-07-04 09:03:20 +0800773 struct mtk_tx_dma_v2 *tx_ring;
developerfd40db22021-04-29 10:08:25 +0800774 int i = 0;
775
developerfd40db22021-04-29 10:08:25 +0800776 seq_printf(seq, "free count = %d\n", (int)atomic_read(&ring->free_count));
777 seq_printf(seq, "cpu next free: %d\n", (int)(ring->next_free - ring->dma));
778 seq_printf(seq, "cpu last free: %d\n", (int)(ring->last_free - ring->dma));
779 for (i = 0; i < MTK_DMA_SIZE; i++) {
developer8b6f2402022-11-28 13:42:34 +0800780 dma_addr_t tmp = ring->phys +
781 i * (dma_addr_t)eth->soc->txrx.txd_size;
developere9356982022-07-04 09:03:20 +0800782
783 tx_ring = ring->dma + i * eth->soc->txrx.txd_size;
developerfd40db22021-04-29 10:08:25 +0800784
785 seq_printf(seq, "%d (%pad): %08x %08x %08x %08x", i, &tmp,
developere9356982022-07-04 09:03:20 +0800786 tx_ring->txd1, tx_ring->txd2,
787 tx_ring->txd3, tx_ring->txd4);
788
developer089e8852022-09-28 14:43:46 +0800789 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ||
790 MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
developere9356982022-07-04 09:03:20 +0800791 seq_printf(seq, " %08x %08x %08x %08x",
792 tx_ring->txd5, tx_ring->txd6,
793 tx_ring->txd7, tx_ring->txd8);
794 }
795
developerfd40db22021-04-29 10:08:25 +0800796 seq_printf(seq, "\n");
797 }
798
developerfd40db22021-04-29 10:08:25 +0800799 return 0;
800}
801
802static int tx_ring_open(struct inode *inode, struct file *file)
803{
804 return single_open(file, tx_ring_read, NULL);
805}
806
807static const struct file_operations tx_ring_fops = {
808 .owner = THIS_MODULE,
809 .open = tx_ring_open,
810 .read = seq_read,
811 .llseek = seq_lseek,
812 .release = single_release
813};
814
developer8051e042022-04-08 13:26:36 +0800815int hwtx_ring_read(struct seq_file *seq, void *v)
816{
817 struct mtk_eth *eth = g_eth;
developere9356982022-07-04 09:03:20 +0800818 struct mtk_tx_dma_v2 *hwtx_ring;
developer8051e042022-04-08 13:26:36 +0800819 int i = 0;
820
developer8051e042022-04-08 13:26:36 +0800821 for (i = 0; i < MTK_DMA_SIZE; i++) {
developer8b6f2402022-11-28 13:42:34 +0800822 dma_addr_t addr = eth->phy_scratch_ring +
823 i * (dma_addr_t)eth->soc->txrx.txd_size;
developere9356982022-07-04 09:03:20 +0800824
825 hwtx_ring = eth->scratch_ring + i * eth->soc->txrx.txd_size;
developer8051e042022-04-08 13:26:36 +0800826
827 seq_printf(seq, "%d (%pad): %08x %08x %08x %08x", i, &addr,
developere9356982022-07-04 09:03:20 +0800828 hwtx_ring->txd1, hwtx_ring->txd2,
829 hwtx_ring->txd3, hwtx_ring->txd4);
830
developer089e8852022-09-28 14:43:46 +0800831 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ||
832 MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
developere9356982022-07-04 09:03:20 +0800833 seq_printf(seq, " %08x %08x %08x %08x",
834 hwtx_ring->txd5, hwtx_ring->txd6,
835 hwtx_ring->txd7, hwtx_ring->txd8);
836 }
837
developer8051e042022-04-08 13:26:36 +0800838 seq_printf(seq, "\n");
839 }
840
developer8051e042022-04-08 13:26:36 +0800841 return 0;
842}
843
844static int hwtx_ring_open(struct inode *inode, struct file *file)
845{
846 return single_open(file, hwtx_ring_read, NULL);
847}
848
849static const struct file_operations hwtx_ring_fops = {
850 .owner = THIS_MODULE,
851 .open = hwtx_ring_open,
852 .read = seq_read,
853 .llseek = seq_lseek,
854 .release = single_release
855};
856
developerfd40db22021-04-29 10:08:25 +0800857int rx_ring_read(struct seq_file *seq, void *v)
858{
developere9356982022-07-04 09:03:20 +0800859 struct mtk_eth *eth = g_eth;
developerfd40db22021-04-29 10:08:25 +0800860 struct mtk_rx_ring *ring = &g_eth->rx_ring[0];
developere9356982022-07-04 09:03:20 +0800861 struct mtk_rx_dma_v2 *rx_ring;
developerfd40db22021-04-29 10:08:25 +0800862 int i = 0;
863
developerfd40db22021-04-29 10:08:25 +0800864 seq_printf(seq, "next to read: %d\n",
865 NEXT_DESP_IDX(ring->calc_idx, MTK_DMA_SIZE));
866 for (i = 0; i < MTK_DMA_SIZE; i++) {
developere9356982022-07-04 09:03:20 +0800867 rx_ring = ring->dma + i * eth->soc->txrx.rxd_size;
868
developerfd40db22021-04-29 10:08:25 +0800869 seq_printf(seq, "%d: %08x %08x %08x %08x", i,
developere9356982022-07-04 09:03:20 +0800870 rx_ring->rxd1, rx_ring->rxd2,
871 rx_ring->rxd3, rx_ring->rxd4);
872
developer089e8852022-09-28 14:43:46 +0800873 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ||
874 MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
developere9356982022-07-04 09:03:20 +0800875 seq_printf(seq, " %08x %08x %08x %08x",
876 rx_ring->rxd5, rx_ring->rxd6,
877 rx_ring->rxd7, rx_ring->rxd8);
878 }
879
developerfd40db22021-04-29 10:08:25 +0800880 seq_printf(seq, "\n");
881 }
882
developerfd40db22021-04-29 10:08:25 +0800883 return 0;
884}
885
886static int rx_ring_open(struct inode *inode, struct file *file)
887{
888 return single_open(file, rx_ring_read, NULL);
889}
890
891static const struct file_operations rx_ring_fops = {
892 .owner = THIS_MODULE,
893 .open = rx_ring_open,
894 .read = seq_read,
895 .llseek = seq_lseek,
896 .release = single_release
897};
898
developer77f3fd42021-10-05 15:16:05 +0800899static inline u32 mtk_dbg_r32(u32 reg)
900{
901 void __iomem *virt_reg;
902 u32 val;
903
904 virt_reg = ioremap(reg, 32);
905 val = __raw_readl(virt_reg);
906 iounmap(virt_reg);
907
908 return val;
909}
910
developerfd40db22021-04-29 10:08:25 +0800911int dbg_regs_read(struct seq_file *seq, void *v)
912{
913 struct mtk_eth *eth = g_eth;
914
developer77f3fd42021-10-05 15:16:05 +0800915 seq_puts(seq, " <<DEBUG REG DUMP>>\n");
916
917 seq_printf(seq, "| FE_INT_STA : %08x |\n",
developer8051e042022-04-08 13:26:36 +0800918 mtk_r32(eth, MTK_FE_INT_STATUS));
developer089e8852022-09-28 14:43:46 +0800919 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ||
920 MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3))
developer77f3fd42021-10-05 15:16:05 +0800921 seq_printf(seq, "| FE_INT_STA2 : %08x |\n",
developer8051e042022-04-08 13:26:36 +0800922 mtk_r32(eth, MTK_FE_INT_STATUS2));
developer77f3fd42021-10-05 15:16:05 +0800923
developerfd40db22021-04-29 10:08:25 +0800924 seq_printf(seq, "| PSE_FQFC_CFG : %08x |\n",
925 mtk_r32(eth, MTK_PSE_FQFC_CFG));
926 seq_printf(seq, "| PSE_IQ_STA1 : %08x |\n",
927 mtk_r32(eth, MTK_PSE_IQ_STA(0)));
928 seq_printf(seq, "| PSE_IQ_STA2 : %08x |\n",
929 mtk_r32(eth, MTK_PSE_IQ_STA(1)));
930
developer089e8852022-09-28 14:43:46 +0800931 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ||
932 MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
developerfd40db22021-04-29 10:08:25 +0800933 seq_printf(seq, "| PSE_IQ_STA3 : %08x |\n",
934 mtk_r32(eth, MTK_PSE_IQ_STA(2)));
935 seq_printf(seq, "| PSE_IQ_STA4 : %08x |\n",
936 mtk_r32(eth, MTK_PSE_IQ_STA(3)));
developer77f3fd42021-10-05 15:16:05 +0800937 seq_printf(seq, "| PSE_IQ_STA5 : %08x |\n",
938 mtk_r32(eth, MTK_PSE_IQ_STA(4)));
developer089e8852022-09-28 14:43:46 +0800939 seq_printf(seq, "| PSE_IQ_STA6 : %08x |\n",
940 mtk_r32(eth, MTK_PSE_IQ_STA(5)));
941 seq_printf(seq, "| PSE_IQ_STA7 : %08x |\n",
942 mtk_r32(eth, MTK_PSE_IQ_STA(6)));
943 seq_printf(seq, "| PSE_IQ_STA8 : %08x |\n",
944 mtk_r32(eth, MTK_PSE_IQ_STA(7)));
developerfd40db22021-04-29 10:08:25 +0800945 }
946
947 seq_printf(seq, "| PSE_OQ_STA1 : %08x |\n",
948 mtk_r32(eth, MTK_PSE_OQ_STA(0)));
949 seq_printf(seq, "| PSE_OQ_STA2 : %08x |\n",
950 mtk_r32(eth, MTK_PSE_OQ_STA(1)));
951
developer089e8852022-09-28 14:43:46 +0800952 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ||
953 MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
developerfd40db22021-04-29 10:08:25 +0800954 seq_printf(seq, "| PSE_OQ_STA3 : %08x |\n",
955 mtk_r32(eth, MTK_PSE_OQ_STA(2)));
956 seq_printf(seq, "| PSE_OQ_STA4 : %08x |\n",
957 mtk_r32(eth, MTK_PSE_OQ_STA(3)));
developer77f3fd42021-10-05 15:16:05 +0800958 seq_printf(seq, "| PSE_OQ_STA5 : %08x |\n",
959 mtk_r32(eth, MTK_PSE_OQ_STA(4)));
developer089e8852022-09-28 14:43:46 +0800960 seq_printf(seq, "| PSE_OQ_STA6 : %08x |\n",
961 mtk_r32(eth, MTK_PSE_OQ_STA(5)));
962 seq_printf(seq, "| PSE_OQ_STA7 : %08x |\n",
963 mtk_r32(eth, MTK_PSE_OQ_STA(6)));
964 seq_printf(seq, "| PSE_OQ_STA8 : %08x |\n",
965 mtk_r32(eth, MTK_PSE_OQ_STA(7)));
developerfd40db22021-04-29 10:08:25 +0800966 }
967
developer77f3fd42021-10-05 15:16:05 +0800968 seq_printf(seq, "| PDMA_CRX_IDX : %08x |\n",
969 mtk_r32(eth, MTK_PRX_CRX_IDX0));
970 seq_printf(seq, "| PDMA_DRX_IDX : %08x |\n",
971 mtk_r32(eth, MTK_PRX_DRX_IDX0));
972 seq_printf(seq, "| QDMA_CTX_IDX : %08x |\n",
973 mtk_r32(eth, MTK_QTX_CTX_PTR));
974 seq_printf(seq, "| QDMA_DTX_IDX : %08x |\n",
975 mtk_r32(eth, MTK_QTX_DTX_PTR));
developerfd40db22021-04-29 10:08:25 +0800976 seq_printf(seq, "| QDMA_FQ_CNT : %08x |\n",
977 mtk_r32(eth, MTK_QDMA_FQ_CNT));
developer089e8852022-09-28 14:43:46 +0800978 seq_printf(seq, "| QDMA_FWD_CNT : %08x |\n",
979 mtk_r32(eth, MTK_QDMA_FWD_CNT));
980 seq_printf(seq, "| QDMA_FSM : %08x |\n",
981 mtk_r32(eth, MTK_QDMA_FSM));
developerfd40db22021-04-29 10:08:25 +0800982 seq_printf(seq, "| FE_PSE_FREE : %08x |\n",
983 mtk_r32(eth, MTK_FE_PSE_FREE));
984 seq_printf(seq, "| FE_DROP_FQ : %08x |\n",
985 mtk_r32(eth, MTK_FE_DROP_FQ));
986 seq_printf(seq, "| FE_DROP_FC : %08x |\n",
987 mtk_r32(eth, MTK_FE_DROP_FC));
988 seq_printf(seq, "| FE_DROP_PPE : %08x |\n",
989 mtk_r32(eth, MTK_FE_DROP_PPE));
990 seq_printf(seq, "| GDM1_IG_CTRL : %08x |\n",
991 mtk_r32(eth, MTK_GDMA_FWD_CFG(0)));
992 seq_printf(seq, "| GDM2_IG_CTRL : %08x |\n",
993 mtk_r32(eth, MTK_GDMA_FWD_CFG(1)));
developer089e8852022-09-28 14:43:46 +0800994 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
995 seq_printf(seq, "| GDM3_IG_CTRL : %08x |\n",
996 mtk_r32(eth, MTK_GDMA_FWD_CFG(2)));
997 }
developerfd40db22021-04-29 10:08:25 +0800998 seq_printf(seq, "| MAC_P1_MCR : %08x |\n",
999 mtk_r32(eth, MTK_MAC_MCR(0)));
1000 seq_printf(seq, "| MAC_P2_MCR : %08x |\n",
1001 mtk_r32(eth, MTK_MAC_MCR(1)));
developer089e8852022-09-28 14:43:46 +08001002 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
1003 seq_printf(seq, "| MAC_P3_MCR : %08x |\n",
1004 mtk_r32(eth, MTK_MAC_MCR(2)));
1005 }
developer77f3fd42021-10-05 15:16:05 +08001006 seq_printf(seq, "| MAC_P1_FSM : %08x |\n",
1007 mtk_r32(eth, MTK_MAC_FSM(0)));
1008 seq_printf(seq, "| MAC_P2_FSM : %08x |\n",
1009 mtk_r32(eth, MTK_MAC_FSM(1)));
developer089e8852022-09-28 14:43:46 +08001010 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
1011 seq_printf(seq, "| MAC_P3_FSM : %08x |\n",
1012 mtk_r32(eth, MTK_MAC_FSM(2)));
1013 }
developerfd40db22021-04-29 10:08:25 +08001014
developer089e8852022-09-28 14:43:46 +08001015 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ||
1016 MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
developerfd40db22021-04-29 10:08:25 +08001017 seq_printf(seq, "| FE_CDM1_FSM : %08x |\n",
1018 mtk_r32(eth, MTK_FE_CDM1_FSM));
1019 seq_printf(seq, "| FE_CDM2_FSM : %08x |\n",
1020 mtk_r32(eth, MTK_FE_CDM2_FSM));
developer77f3fd42021-10-05 15:16:05 +08001021 seq_printf(seq, "| FE_CDM3_FSM : %08x |\n",
1022 mtk_r32(eth, MTK_FE_CDM3_FSM));
1023 seq_printf(seq, "| FE_CDM4_FSM : %08x |\n",
1024 mtk_r32(eth, MTK_FE_CDM4_FSM));
developer089e8852022-09-28 14:43:46 +08001025 seq_printf(seq, "| FE_CDM5_FSM : %08x |\n",
1026 mtk_r32(eth, MTK_FE_CDM5_FSM));
1027 seq_printf(seq, "| FE_CDM6_FSM : %08x |\n",
1028 mtk_r32(eth, MTK_FE_CDM6_FSM));
developerfd40db22021-04-29 10:08:25 +08001029 seq_printf(seq, "| FE_GDM1_FSM : %08x |\n",
1030 mtk_r32(eth, MTK_FE_GDM1_FSM));
1031 seq_printf(seq, "| FE_GDM2_FSM : %08x |\n",
1032 mtk_r32(eth, MTK_FE_GDM2_FSM));
developer77f3fd42021-10-05 15:16:05 +08001033 seq_printf(seq, "| SGMII_EFUSE : %08x |\n",
1034 mtk_dbg_r32(MTK_SGMII_EFUSE));
1035 seq_printf(seq, "| SGMII0_RX_CNT : %08x |\n",
1036 mtk_dbg_r32(MTK_SGMII_FALSE_CARRIER_CNT(0)));
1037 seq_printf(seq, "| SGMII1_RX_CNT : %08x |\n",
1038 mtk_dbg_r32(MTK_SGMII_FALSE_CARRIER_CNT(1)));
1039 seq_printf(seq, "| WED_RTQM_GLO : %08x |\n",
1040 mtk_dbg_r32(MTK_WED_RTQM_GLO_CFG));
developerfd40db22021-04-29 10:08:25 +08001041 }
1042
developer8051e042022-04-08 13:26:36 +08001043 mtk_w32(eth, 0xffffffff, MTK_FE_INT_STATUS);
developer089e8852022-09-28 14:43:46 +08001044 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ||
1045 MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3))
developer8051e042022-04-08 13:26:36 +08001046 mtk_w32(eth, 0xffffffff, MTK_FE_INT_STATUS2);
developer77f3fd42021-10-05 15:16:05 +08001047
developerfd40db22021-04-29 10:08:25 +08001048 return 0;
1049}
1050
1051static int dbg_regs_open(struct inode *inode, struct file *file)
1052{
1053 return single_open(file, dbg_regs_read, 0);
1054}
1055
1056static const struct file_operations dbg_regs_fops = {
1057 .owner = THIS_MODULE,
1058 .open = dbg_regs_open,
1059 .read = seq_read,
1060 .llseek = seq_lseek,
developer77d03a72021-06-06 00:06:00 +08001061 .release = single_release
1062};
1063
developere9356982022-07-04 09:03:20 +08001064void hw_lro_stats_update(u32 ring_no, struct mtk_rx_dma_v2 *rxd)
developer77d03a72021-06-06 00:06:00 +08001065{
developere9356982022-07-04 09:03:20 +08001066 struct mtk_eth *eth = g_eth;
developer77d03a72021-06-06 00:06:00 +08001067 u32 idx, agg_cnt, agg_size;
1068
developer089e8852022-09-28 14:43:46 +08001069 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ||
1070 MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
developere9356982022-07-04 09:03:20 +08001071 idx = ring_no - 4;
1072 agg_cnt = RX_DMA_GET_AGG_CNT_V2(rxd->rxd6);
1073 } else {
1074 idx = ring_no - 1;
1075 agg_cnt = RX_DMA_GET_AGG_CNT(rxd->rxd2);
1076 }
developer77d03a72021-06-06 00:06:00 +08001077
developer8b6f2402022-11-28 13:42:34 +08001078 if (idx >= MTK_HW_LRO_RING_NUM)
1079 return;
1080
developer77d03a72021-06-06 00:06:00 +08001081 agg_size = RX_DMA_GET_PLEN0(rxd->rxd2);
1082
1083 hw_lro_agg_size_cnt[idx][agg_size / 5000]++;
1084 hw_lro_agg_num_cnt[idx][agg_cnt]++;
1085 hw_lro_tot_flush_cnt[idx]++;
1086 hw_lro_tot_agg_cnt[idx] += agg_cnt;
1087}
1088
developere9356982022-07-04 09:03:20 +08001089void hw_lro_flush_stats_update(u32 ring_no, struct mtk_rx_dma_v2 *rxd)
developer77d03a72021-06-06 00:06:00 +08001090{
developere9356982022-07-04 09:03:20 +08001091 struct mtk_eth *eth = g_eth;
developer77d03a72021-06-06 00:06:00 +08001092 u32 idx, flush_reason;
1093
developer089e8852022-09-28 14:43:46 +08001094 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ||
1095 MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
developere9356982022-07-04 09:03:20 +08001096 idx = ring_no - 4;
1097 flush_reason = RX_DMA_GET_FLUSH_RSN_V2(rxd->rxd6);
1098 } else {
1099 idx = ring_no - 1;
1100 flush_reason = RX_DMA_GET_REV(rxd->rxd2);
1101 }
developer77d03a72021-06-06 00:06:00 +08001102
developer8b6f2402022-11-28 13:42:34 +08001103 if (idx >= MTK_HW_LRO_RING_NUM)
1104 return;
1105
developer77d03a72021-06-06 00:06:00 +08001106 if ((flush_reason & 0x7) == MTK_HW_LRO_AGG_FLUSH)
1107 hw_lro_agg_flush_cnt[idx]++;
1108 else if ((flush_reason & 0x7) == MTK_HW_LRO_AGE_FLUSH)
1109 hw_lro_age_flush_cnt[idx]++;
1110 else if ((flush_reason & 0x7) == MTK_HW_LRO_NOT_IN_SEQ_FLUSH)
1111 hw_lro_seq_flush_cnt[idx]++;
1112 else if ((flush_reason & 0x7) == MTK_HW_LRO_TIMESTAMP_FLUSH)
1113 hw_lro_timestamp_flush_cnt[idx]++;
1114 else if ((flush_reason & 0x7) == MTK_HW_LRO_NON_RULE_FLUSH)
1115 hw_lro_norule_flush_cnt[idx]++;
1116}
1117
1118ssize_t hw_lro_stats_write(struct file *file, const char __user *buffer,
1119 size_t count, loff_t *data)
1120{
1121 memset(hw_lro_agg_num_cnt, 0, sizeof(hw_lro_agg_num_cnt));
1122 memset(hw_lro_agg_size_cnt, 0, sizeof(hw_lro_agg_size_cnt));
1123 memset(hw_lro_tot_agg_cnt, 0, sizeof(hw_lro_tot_agg_cnt));
1124 memset(hw_lro_tot_flush_cnt, 0, sizeof(hw_lro_tot_flush_cnt));
1125 memset(hw_lro_agg_flush_cnt, 0, sizeof(hw_lro_agg_flush_cnt));
1126 memset(hw_lro_age_flush_cnt, 0, sizeof(hw_lro_age_flush_cnt));
1127 memset(hw_lro_seq_flush_cnt, 0, sizeof(hw_lro_seq_flush_cnt));
1128 memset(hw_lro_timestamp_flush_cnt, 0,
1129 sizeof(hw_lro_timestamp_flush_cnt));
1130 memset(hw_lro_norule_flush_cnt, 0, sizeof(hw_lro_norule_flush_cnt));
1131
1132 pr_info("clear hw lro cnt table\n");
1133
1134 return count;
1135}
1136
1137int hw_lro_stats_read_v1(struct seq_file *seq, void *v)
1138{
1139 int i;
1140
1141 seq_puts(seq, "HW LRO statistic dump:\n");
1142
1143 /* Agg number count */
1144 seq_puts(seq, "Cnt: RING1 | RING2 | RING3 | Total\n");
1145 for (i = 0; i <= MTK_HW_LRO_MAX_AGG_CNT; i++) {
1146 seq_printf(seq, " %d : %d %d %d %d\n",
1147 i, hw_lro_agg_num_cnt[0][i],
1148 hw_lro_agg_num_cnt[1][i], hw_lro_agg_num_cnt[2][i],
1149 hw_lro_agg_num_cnt[0][i] + hw_lro_agg_num_cnt[1][i] +
1150 hw_lro_agg_num_cnt[2][i]);
1151 }
1152
1153 /* Total agg count */
1154 seq_puts(seq, "Total agg: RING1 | RING2 | RING3 | Total\n");
1155 seq_printf(seq, " %d %d %d %d\n",
1156 hw_lro_tot_agg_cnt[0], hw_lro_tot_agg_cnt[1],
1157 hw_lro_tot_agg_cnt[2],
1158 hw_lro_tot_agg_cnt[0] + hw_lro_tot_agg_cnt[1] +
1159 hw_lro_tot_agg_cnt[2]);
1160
1161 /* Total flush count */
1162 seq_puts(seq, "Total flush: RING1 | RING2 | RING3 | Total\n");
1163 seq_printf(seq, " %d %d %d %d\n",
1164 hw_lro_tot_flush_cnt[0], hw_lro_tot_flush_cnt[1],
1165 hw_lro_tot_flush_cnt[2],
1166 hw_lro_tot_flush_cnt[0] + hw_lro_tot_flush_cnt[1] +
1167 hw_lro_tot_flush_cnt[2]);
1168
1169 /* Avg agg count */
1170 seq_puts(seq, "Avg agg: RING1 | RING2 | RING3 | Total\n");
1171 seq_printf(seq, " %d %d %d %d\n",
1172 (hw_lro_tot_flush_cnt[0]) ?
1173 hw_lro_tot_agg_cnt[0] / hw_lro_tot_flush_cnt[0] : 0,
1174 (hw_lro_tot_flush_cnt[1]) ?
1175 hw_lro_tot_agg_cnt[1] / hw_lro_tot_flush_cnt[1] : 0,
1176 (hw_lro_tot_flush_cnt[2]) ?
1177 hw_lro_tot_agg_cnt[2] / hw_lro_tot_flush_cnt[2] : 0,
1178 (hw_lro_tot_flush_cnt[0] + hw_lro_tot_flush_cnt[1] +
1179 hw_lro_tot_flush_cnt[2]) ?
1180 ((hw_lro_tot_agg_cnt[0] + hw_lro_tot_agg_cnt[1] +
1181 hw_lro_tot_agg_cnt[2]) / (hw_lro_tot_flush_cnt[0] +
1182 hw_lro_tot_flush_cnt[1] + hw_lro_tot_flush_cnt[2])) : 0);
1183
1184 /* Statistics of aggregation size counts */
1185 seq_puts(seq, "HW LRO flush pkt len:\n");
1186 seq_puts(seq, " Length | RING1 | RING2 | RING3 | Total\n");
1187 for (i = 0; i < 15; i++) {
1188 seq_printf(seq, "%d~%d: %d %d %d %d\n", i * 5000,
1189 (i + 1) * 5000, hw_lro_agg_size_cnt[0][i],
1190 hw_lro_agg_size_cnt[1][i], hw_lro_agg_size_cnt[2][i],
1191 hw_lro_agg_size_cnt[0][i] +
1192 hw_lro_agg_size_cnt[1][i] +
1193 hw_lro_agg_size_cnt[2][i]);
1194 }
1195
1196 seq_puts(seq, "Flush reason: RING1 | RING2 | RING3 | Total\n");
1197 seq_printf(seq, "AGG timeout: %d %d %d %d\n",
1198 hw_lro_agg_flush_cnt[0], hw_lro_agg_flush_cnt[1],
1199 hw_lro_agg_flush_cnt[2],
1200 (hw_lro_agg_flush_cnt[0] + hw_lro_agg_flush_cnt[1] +
1201 hw_lro_agg_flush_cnt[2]));
1202
1203 seq_printf(seq, "AGE timeout: %d %d %d %d\n",
1204 hw_lro_age_flush_cnt[0], hw_lro_age_flush_cnt[1],
1205 hw_lro_age_flush_cnt[2],
1206 (hw_lro_age_flush_cnt[0] + hw_lro_age_flush_cnt[1] +
1207 hw_lro_age_flush_cnt[2]));
1208
1209 seq_printf(seq, "Not in-sequence: %d %d %d %d\n",
1210 hw_lro_seq_flush_cnt[0], hw_lro_seq_flush_cnt[1],
1211 hw_lro_seq_flush_cnt[2],
1212 (hw_lro_seq_flush_cnt[0] + hw_lro_seq_flush_cnt[1] +
1213 hw_lro_seq_flush_cnt[2]));
1214
1215 seq_printf(seq, "Timestamp: %d %d %d %d\n",
1216 hw_lro_timestamp_flush_cnt[0],
1217 hw_lro_timestamp_flush_cnt[1],
1218 hw_lro_timestamp_flush_cnt[2],
1219 (hw_lro_timestamp_flush_cnt[0] +
1220 hw_lro_timestamp_flush_cnt[1] +
1221 hw_lro_timestamp_flush_cnt[2]));
1222
1223 seq_printf(seq, "No LRO rule: %d %d %d %d\n",
1224 hw_lro_norule_flush_cnt[0],
1225 hw_lro_norule_flush_cnt[1],
1226 hw_lro_norule_flush_cnt[2],
1227 (hw_lro_norule_flush_cnt[0] +
1228 hw_lro_norule_flush_cnt[1] +
1229 hw_lro_norule_flush_cnt[2]));
1230
1231 return 0;
1232}
1233
1234int hw_lro_stats_read_v2(struct seq_file *seq, void *v)
1235{
1236 int i;
1237
1238 seq_puts(seq, "HW LRO statistic dump:\n");
1239
1240 /* Agg number count */
1241 seq_puts(seq, "Cnt: RING4 | RING5 | RING6 | RING7 Total\n");
1242 for (i = 0; i <= MTK_HW_LRO_MAX_AGG_CNT; i++) {
1243 seq_printf(seq,
1244 " %d : %d %d %d %d %d\n",
1245 i, hw_lro_agg_num_cnt[0][i], hw_lro_agg_num_cnt[1][i],
1246 hw_lro_agg_num_cnt[2][i], hw_lro_agg_num_cnt[3][i],
1247 hw_lro_agg_num_cnt[0][i] + hw_lro_agg_num_cnt[1][i] +
1248 hw_lro_agg_num_cnt[2][i] + hw_lro_agg_num_cnt[3][i]);
1249 }
1250
1251 /* Total agg count */
1252 seq_puts(seq, "Total agg: RING4 | RING5 | RING6 | RING7 Total\n");
1253 seq_printf(seq, " %d %d %d %d %d\n",
1254 hw_lro_tot_agg_cnt[0], hw_lro_tot_agg_cnt[1],
1255 hw_lro_tot_agg_cnt[2], hw_lro_tot_agg_cnt[3],
1256 hw_lro_tot_agg_cnt[0] + hw_lro_tot_agg_cnt[1] +
1257 hw_lro_tot_agg_cnt[2] + hw_lro_tot_agg_cnt[3]);
1258
1259 /* Total flush count */
1260 seq_puts(seq, "Total flush: RING4 | RING5 | RING6 | RING7 Total\n");
1261 seq_printf(seq, " %d %d %d %d %d\n",
1262 hw_lro_tot_flush_cnt[0], hw_lro_tot_flush_cnt[1],
1263 hw_lro_tot_flush_cnt[2], hw_lro_tot_flush_cnt[3],
1264 hw_lro_tot_flush_cnt[0] + hw_lro_tot_flush_cnt[1] +
1265 hw_lro_tot_flush_cnt[2] + hw_lro_tot_flush_cnt[3]);
1266
1267 /* Avg agg count */
1268 seq_puts(seq, "Avg agg: RING4 | RING5 | RING6 | RING7 Total\n");
1269 seq_printf(seq, " %d %d %d %d %d\n",
1270 (hw_lro_tot_flush_cnt[0]) ?
1271 hw_lro_tot_agg_cnt[0] / hw_lro_tot_flush_cnt[0] : 0,
1272 (hw_lro_tot_flush_cnt[1]) ?
1273 hw_lro_tot_agg_cnt[1] / hw_lro_tot_flush_cnt[1] : 0,
1274 (hw_lro_tot_flush_cnt[2]) ?
1275 hw_lro_tot_agg_cnt[2] / hw_lro_tot_flush_cnt[2] : 0,
1276 (hw_lro_tot_flush_cnt[3]) ?
1277 hw_lro_tot_agg_cnt[3] / hw_lro_tot_flush_cnt[3] : 0,
1278 (hw_lro_tot_flush_cnt[0] + hw_lro_tot_flush_cnt[1] +
1279 hw_lro_tot_flush_cnt[2] + hw_lro_tot_flush_cnt[3]) ?
1280 ((hw_lro_tot_agg_cnt[0] + hw_lro_tot_agg_cnt[1] +
1281 hw_lro_tot_agg_cnt[2] + hw_lro_tot_agg_cnt[3]) /
1282 (hw_lro_tot_flush_cnt[0] + hw_lro_tot_flush_cnt[1] +
1283 hw_lro_tot_flush_cnt[2] + hw_lro_tot_flush_cnt[3])) : 0);
1284
1285 /* Statistics of aggregation size counts */
1286 seq_puts(seq, "HW LRO flush pkt len:\n");
1287 seq_puts(seq, " Length | RING4 | RING5 | RING6 | RING7 Total\n");
1288 for (i = 0; i < 15; i++) {
1289 seq_printf(seq, "%d~%d: %d %d %d %d %d\n",
1290 i * 5000, (i + 1) * 5000,
1291 hw_lro_agg_size_cnt[0][i], hw_lro_agg_size_cnt[1][i],
1292 hw_lro_agg_size_cnt[2][i], hw_lro_agg_size_cnt[3][i],
1293 hw_lro_agg_size_cnt[0][i] +
1294 hw_lro_agg_size_cnt[1][i] +
1295 hw_lro_agg_size_cnt[2][i] +
1296 hw_lro_agg_size_cnt[3][i]);
1297 }
1298
1299 seq_puts(seq, "Flush reason: RING4 | RING5 | RING6 | RING7 Total\n");
1300 seq_printf(seq, "AGG timeout: %d %d %d %d %d\n",
1301 hw_lro_agg_flush_cnt[0], hw_lro_agg_flush_cnt[1],
1302 hw_lro_agg_flush_cnt[2], hw_lro_agg_flush_cnt[3],
1303 (hw_lro_agg_flush_cnt[0] + hw_lro_agg_flush_cnt[1] +
1304 hw_lro_agg_flush_cnt[2] + hw_lro_agg_flush_cnt[3]));
1305
1306 seq_printf(seq, "AGE timeout: %d %d %d %d %d\n",
1307 hw_lro_age_flush_cnt[0], hw_lro_age_flush_cnt[1],
1308 hw_lro_age_flush_cnt[2], hw_lro_age_flush_cnt[3],
1309 (hw_lro_age_flush_cnt[0] + hw_lro_age_flush_cnt[1] +
1310 hw_lro_age_flush_cnt[2] + hw_lro_age_flush_cnt[3]));
1311
1312 seq_printf(seq, "Not in-sequence: %d %d %d %d %d\n",
1313 hw_lro_seq_flush_cnt[0], hw_lro_seq_flush_cnt[1],
1314 hw_lro_seq_flush_cnt[2], hw_lro_seq_flush_cnt[3],
1315 (hw_lro_seq_flush_cnt[0] + hw_lro_seq_flush_cnt[1] +
1316 hw_lro_seq_flush_cnt[2] + hw_lro_seq_flush_cnt[3]));
1317
1318 seq_printf(seq, "Timestamp: %d %d %d %d %d\n",
1319 hw_lro_timestamp_flush_cnt[0],
1320 hw_lro_timestamp_flush_cnt[1],
1321 hw_lro_timestamp_flush_cnt[2],
1322 hw_lro_timestamp_flush_cnt[3],
1323 (hw_lro_timestamp_flush_cnt[0] +
1324 hw_lro_timestamp_flush_cnt[1] +
1325 hw_lro_timestamp_flush_cnt[2] +
1326 hw_lro_timestamp_flush_cnt[3]));
1327
1328 seq_printf(seq, "No LRO rule: %d %d %d %d %d\n",
1329 hw_lro_norule_flush_cnt[0],
1330 hw_lro_norule_flush_cnt[1],
1331 hw_lro_norule_flush_cnt[2],
1332 hw_lro_norule_flush_cnt[3],
1333 (hw_lro_norule_flush_cnt[0] +
1334 hw_lro_norule_flush_cnt[1] +
1335 hw_lro_norule_flush_cnt[2] +
1336 hw_lro_norule_flush_cnt[3]));
1337
1338 return 0;
1339}
1340
1341int hw_lro_stats_read_wrapper(struct seq_file *seq, void *v)
1342{
1343 struct mtk_eth *eth = g_eth;
1344
developer089e8852022-09-28 14:43:46 +08001345 if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2) ||
1346 MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3))
developer77d03a72021-06-06 00:06:00 +08001347 hw_lro_stats_read_v2(seq, v);
1348 else
1349 hw_lro_stats_read_v1(seq, v);
1350
1351 return 0;
1352}
1353
1354static int hw_lro_stats_open(struct inode *inode, struct file *file)
1355{
1356 return single_open(file, hw_lro_stats_read_wrapper, NULL);
1357}
1358
1359static const struct file_operations hw_lro_stats_fops = {
1360 .owner = THIS_MODULE,
1361 .open = hw_lro_stats_open,
1362 .read = seq_read,
1363 .llseek = seq_lseek,
1364 .write = hw_lro_stats_write,
developerfd40db22021-04-29 10:08:25 +08001365 .release = single_release
1366};
1367
developer77d03a72021-06-06 00:06:00 +08001368int hwlro_agg_cnt_ctrl(int cnt)
1369{
1370 int i;
1371
1372 for (i = 1; i <= MTK_HW_LRO_RING_NUM; i++)
1373 SET_PDMA_RXRING_MAX_AGG_CNT(g_eth, i, cnt);
1374
1375 return 0;
1376}
1377
1378int hwlro_agg_time_ctrl(int time)
1379{
1380 int i;
1381
1382 for (i = 1; i <= MTK_HW_LRO_RING_NUM; i++)
1383 SET_PDMA_RXRING_AGG_TIME(g_eth, i, time);
1384
1385 return 0;
1386}
1387
1388int hwlro_age_time_ctrl(int time)
1389{
1390 int i;
1391
1392 for (i = 1; i <= MTK_HW_LRO_RING_NUM; i++)
1393 SET_PDMA_RXRING_AGE_TIME(g_eth, i, time);
1394
1395 return 0;
1396}
1397
1398int hwlro_threshold_ctrl(int bandwidth)
1399{
1400 SET_PDMA_LRO_BW_THRESHOLD(g_eth, bandwidth);
1401
1402 return 0;
1403}
1404
1405int hwlro_ring_enable_ctrl(int enable)
1406{
1407 int i;
1408
1409 pr_info("[%s] %s HW LRO rings\n", __func__, (enable) ? "Enable" : "Disable");
1410
1411 for (i = 1; i <= MTK_HW_LRO_RING_NUM; i++)
1412 SET_PDMA_RXRING_VALID(g_eth, i, enable);
1413
1414 return 0;
1415}
1416
1417int hwlro_stats_enable_ctrl(int enable)
1418{
1419 pr_info("[%s] %s HW LRO statistics\n", __func__, (enable) ? "Enable" : "Disable");
1420 mtk_hwlro_stats_ebl = enable;
1421
1422 return 0;
1423}
1424
1425static const mtk_lro_dbg_func lro_dbg_func[] = {
1426 [0] = hwlro_agg_cnt_ctrl,
1427 [1] = hwlro_agg_time_ctrl,
1428 [2] = hwlro_age_time_ctrl,
1429 [3] = hwlro_threshold_ctrl,
1430 [4] = hwlro_ring_enable_ctrl,
1431 [5] = hwlro_stats_enable_ctrl,
1432};
1433
1434ssize_t hw_lro_auto_tlb_write(struct file *file, const char __user *buffer,
1435 size_t count, loff_t *data)
1436{
1437 char buf[32];
1438 char *p_buf;
1439 char *p_token = NULL;
1440 char *p_delimiter = " \t";
1441 long x = 0, y = 0;
developer4c32b7a2021-11-13 16:46:43 +08001442 u32 len = count;
developer77d03a72021-06-06 00:06:00 +08001443 int ret;
1444
1445 if (len >= sizeof(buf)) {
1446 pr_info("Input handling fail!\n");
developer77d03a72021-06-06 00:06:00 +08001447 return -1;
1448 }
1449
1450 if (copy_from_user(buf, buffer, len))
1451 return -EFAULT;
1452
1453 buf[len] = '\0';
1454
1455 p_buf = buf;
1456 p_token = strsep(&p_buf, p_delimiter);
1457 if (!p_token)
1458 x = 0;
1459 else
1460 ret = kstrtol(p_token, 10, &x);
1461
1462 p_token = strsep(&p_buf, "\t\n ");
1463 if (p_token)
1464 ret = kstrtol(p_token, 10, &y);
1465
1466 if (lro_dbg_func[x] && (ARRAY_SIZE(lro_dbg_func) > x))
1467 (*lro_dbg_func[x]) (y);
1468
1469 return count;
1470}
1471
1472void hw_lro_auto_tlb_dump_v1(struct seq_file *seq, u32 index)
1473{
1474 int i;
1475 struct mtk_lro_alt_v1 alt;
1476 __be32 addr;
1477 u32 tlb_info[9];
1478 u32 dw_len, cnt, priority;
1479 u32 entry;
1480
1481 if (index > 4)
1482 index = index - 1;
1483 entry = (index * 9) + 1;
1484
1485 /* read valid entries of the auto-learn table */
1486 mtk_w32(g_eth, entry, MTK_FE_ALT_CF8);
1487
1488 for (i = 0; i < 9; i++)
1489 tlb_info[i] = mtk_r32(g_eth, MTK_FE_ALT_SEQ_CFC);
1490
1491 memcpy(&alt, tlb_info, sizeof(struct mtk_lro_alt_v1));
1492
1493 dw_len = alt.alt_info7.dw_len;
1494 cnt = alt.alt_info6.cnt;
1495
1496 if (mtk_r32(g_eth, MTK_PDMA_LRO_CTRL_DW0) & MTK_LRO_ALT_PKT_CNT_MODE)
1497 priority = cnt; /* packet count */
1498 else
1499 priority = dw_len; /* byte count */
1500
1501 /* dump valid entries of the auto-learn table */
1502 if (index >= 4)
1503 seq_printf(seq, "\n===== TABLE Entry: %d (Act) =====\n", index);
1504 else
1505 seq_printf(seq, "\n===== TABLE Entry: %d (LRU) =====\n", index);
1506
1507 if (alt.alt_info8.ipv4) {
1508 addr = htonl(alt.alt_info1.sip0);
1509 seq_printf(seq, "SIP = %pI4 (IPv4)\n", &addr);
1510 } else {
1511 seq_printf(seq, "SIP = %08X:%08X:%08X:%08X (IPv6)\n",
1512 alt.alt_info4.sip3, alt.alt_info3.sip2,
1513 alt.alt_info2.sip1, alt.alt_info1.sip0);
1514 }
1515
1516 seq_printf(seq, "DIP_ID = %d\n", alt.alt_info8.dip_id);
1517 seq_printf(seq, "TCP SPORT = %d | TCP DPORT = %d\n",
1518 alt.alt_info0.stp, alt.alt_info0.dtp);
1519 seq_printf(seq, "VLAN_VID_VLD = %d\n", alt.alt_info6.vlan_vid_vld);
1520 seq_printf(seq, "VLAN1 = %d | VLAN2 = %d | VLAN3 = %d | VLAN4 =%d\n",
1521 (alt.alt_info5.vlan_vid0 & 0xfff),
1522 ((alt.alt_info5.vlan_vid0 >> 12) & 0xfff),
1523 ((alt.alt_info6.vlan_vid1 << 8) |
1524 ((alt.alt_info5.vlan_vid0 >> 24) & 0xfff)),
1525 ((alt.alt_info6.vlan_vid1 >> 4) & 0xfff));
1526 seq_printf(seq, "TPUT = %d | FREQ = %d\n", dw_len, cnt);
1527 seq_printf(seq, "PRIORITY = %d\n", priority);
1528}
1529
1530void hw_lro_auto_tlb_dump_v2(struct seq_file *seq, u32 index)
1531{
1532 int i;
1533 struct mtk_lro_alt_v2 alt;
1534 u32 score = 0, ipv4 = 0;
1535 u32 ipv6[4] = { 0 };
1536 u32 tlb_info[12];
1537
1538 /* read valid entries of the auto-learn table */
1539 mtk_w32(g_eth, index << MTK_LRO_ALT_INDEX_OFFSET, MTK_LRO_ALT_DBG);
1540
1541 for (i = 0; i < 11; i++)
1542 tlb_info[i] = mtk_r32(g_eth, MTK_LRO_ALT_DBG_DATA);
1543
1544 memcpy(&alt, tlb_info, sizeof(struct mtk_lro_alt_v2));
1545
1546 if (mtk_r32(g_eth, MTK_PDMA_LRO_CTRL_DW0) & MTK_LRO_ALT_PKT_CNT_MODE)
1547 score = 1; /* packet count */
1548 else
1549 score = 0; /* byte count */
1550
1551 /* dump valid entries of the auto-learn table */
1552 if (alt.alt_info0.valid) {
1553 if (index < 5)
1554 seq_printf(seq,
1555 "\n===== TABLE Entry: %d (onging) =====\n",
1556 index);
1557 else
1558 seq_printf(seq,
1559 "\n===== TABLE Entry: %d (candidate) =====\n",
1560 index);
1561
1562 if (alt.alt_info1.v4_valid) {
1563 ipv4 = (alt.alt_info4.sip0_h << 23) |
1564 alt.alt_info5.sip0_l;
1565 seq_printf(seq, "SIP = 0x%x: (IPv4)\n", ipv4);
1566
1567 ipv4 = (alt.alt_info8.dip0_h << 23) |
1568 alt.alt_info9.dip0_l;
1569 seq_printf(seq, "DIP = 0x%x: (IPv4)\n", ipv4);
1570 } else if (alt.alt_info1.v6_valid) {
1571 ipv6[3] = (alt.alt_info1.sip3_h << 23) |
1572 (alt.alt_info2.sip3_l << 9);
1573 ipv6[2] = (alt.alt_info2.sip2_h << 23) |
1574 (alt.alt_info3.sip2_l << 9);
1575 ipv6[1] = (alt.alt_info3.sip1_h << 23) |
1576 (alt.alt_info4.sip1_l << 9);
1577 ipv6[0] = (alt.alt_info4.sip0_h << 23) |
1578 (alt.alt_info5.sip0_l << 9);
1579 seq_printf(seq, "SIP = 0x%x:0x%x:0x%x:0x%x (IPv6)\n",
1580 ipv6[3], ipv6[2], ipv6[1], ipv6[0]);
1581
1582 ipv6[3] = (alt.alt_info5.dip3_h << 23) |
1583 (alt.alt_info6.dip3_l << 9);
1584 ipv6[2] = (alt.alt_info6.dip2_h << 23) |
1585 (alt.alt_info7.dip2_l << 9);
1586 ipv6[1] = (alt.alt_info7.dip1_h << 23) |
1587 (alt.alt_info8.dip1_l << 9);
1588 ipv6[0] = (alt.alt_info8.dip0_h << 23) |
1589 (alt.alt_info9.dip0_l << 9);
1590 seq_printf(seq, "DIP = 0x%x:0x%x:0x%x:0x%x (IPv6)\n",
1591 ipv6[3], ipv6[2], ipv6[1], ipv6[0]);
1592 }
1593
1594 seq_printf(seq, "TCP SPORT = %d | TCP DPORT = %d\n",
1595 (alt.alt_info9.sp_h << 7) | (alt.alt_info10.sp_l),
1596 alt.alt_info10.dp);
1597 }
1598}
1599
1600int hw_lro_auto_tlb_read(struct seq_file *seq, void *v)
1601{
1602 int i;
1603 u32 reg_val;
1604 u32 reg_op1, reg_op2, reg_op3, reg_op4;
1605 u32 agg_cnt, agg_time, age_time;
1606
1607 seq_puts(seq, "Usage of /proc/mtketh/hw_lro_auto_tlb:\n");
1608 seq_puts(seq, "echo [function] [setting] > /proc/mtketh/hw_lro_auto_tlb\n");
1609 seq_puts(seq, "Functions:\n");
1610 seq_puts(seq, "[0] = hwlro_agg_cnt_ctrl\n");
1611 seq_puts(seq, "[1] = hwlro_agg_time_ctrl\n");
1612 seq_puts(seq, "[2] = hwlro_age_time_ctrl\n");
1613 seq_puts(seq, "[3] = hwlro_threshold_ctrl\n");
1614 seq_puts(seq, "[4] = hwlro_ring_enable_ctrl\n");
1615 seq_puts(seq, "[5] = hwlro_stats_enable_ctrl\n\n");
1616
developer089e8852022-09-28 14:43:46 +08001617 if (MTK_HAS_CAPS(g_eth->soc->caps, MTK_NETSYS_V2) ||
1618 MTK_HAS_CAPS(g_eth->soc->caps, MTK_NETSYS_V3)) {
developer77d03a72021-06-06 00:06:00 +08001619 for (i = 1; i <= 8; i++)
1620 hw_lro_auto_tlb_dump_v2(seq, i);
1621 } else {
1622 /* Read valid entries of the auto-learn table */
1623 mtk_w32(g_eth, 0, MTK_FE_ALT_CF8);
1624 reg_val = mtk_r32(g_eth, MTK_FE_ALT_SEQ_CFC);
1625
1626 seq_printf(seq,
1627 "HW LRO Auto-learn Table: (MTK_FE_ALT_SEQ_CFC=0x%x)\n",
1628 reg_val);
1629
1630 for (i = 7; i >= 0; i--) {
1631 if (reg_val & (1 << i))
1632 hw_lro_auto_tlb_dump_v1(seq, i);
1633 }
1634 }
1635
1636 /* Read the agg_time/age_time/agg_cnt of LRO rings */
1637 seq_puts(seq, "\nHW LRO Ring Settings\n");
1638
1639 for (i = 1; i <= MTK_HW_LRO_RING_NUM; i++) {
1640 reg_op1 = mtk_r32(g_eth, MTK_LRO_CTRL_DW1_CFG(i));
1641 reg_op2 = mtk_r32(g_eth, MTK_LRO_CTRL_DW2_CFG(i));
1642 reg_op3 = mtk_r32(g_eth, MTK_LRO_CTRL_DW3_CFG(i));
1643 reg_op4 = mtk_r32(g_eth, MTK_PDMA_LRO_CTRL_DW2);
1644
1645 agg_cnt =
1646 ((reg_op3 & 0x3) << 6) |
1647 ((reg_op2 >> MTK_LRO_RING_AGG_CNT_L_OFFSET) & 0x3f);
1648 agg_time = (reg_op2 >> MTK_LRO_RING_AGG_TIME_OFFSET) & 0xffff;
1649 age_time =
1650 ((reg_op2 & 0x3f) << 10) |
1651 ((reg_op1 >> MTK_LRO_RING_AGE_TIME_L_OFFSET) & 0x3ff);
1652 seq_printf(seq,
1653 "Ring[%d]: MAX_AGG_CNT=%d, AGG_TIME=%d, AGE_TIME=%d, Threshold=%d\n",
developer089e8852022-09-28 14:43:46 +08001654 (MTK_HAS_CAPS(g_eth->soc->caps, MTK_NETSYS_V1)) ? i : i+3,
developer77d03a72021-06-06 00:06:00 +08001655 agg_cnt, agg_time, age_time, reg_op4);
1656 }
1657
1658 seq_puts(seq, "\n");
1659
1660 return 0;
1661}
1662
1663static int hw_lro_auto_tlb_open(struct inode *inode, struct file *file)
1664{
1665 return single_open(file, hw_lro_auto_tlb_read, NULL);
1666}
1667
1668static const struct file_operations hw_lro_auto_tlb_fops = {
1669 .owner = THIS_MODULE,
1670 .open = hw_lro_auto_tlb_open,
1671 .read = seq_read,
1672 .llseek = seq_lseek,
1673 .write = hw_lro_auto_tlb_write,
1674 .release = single_release
1675};
developerfd40db22021-04-29 10:08:25 +08001676
developer8051e042022-04-08 13:26:36 +08001677int reset_event_read(struct seq_file *seq, void *v)
1678{
1679 struct mtk_eth *eth = g_eth;
1680 struct mtk_reset_event reset_event = eth->reset_event;
1681
1682 seq_printf(seq, "[Event] [Count]\n");
1683 seq_printf(seq, " FQ Empty: %d\n",
1684 reset_event.count[MTK_EVENT_FQ_EMPTY]);
1685 seq_printf(seq, " TSO Fail: %d\n",
1686 reset_event.count[MTK_EVENT_TSO_FAIL]);
1687 seq_printf(seq, " TSO Illegal: %d\n",
1688 reset_event.count[MTK_EVENT_TSO_ILLEGAL]);
1689 seq_printf(seq, " TSO Align: %d\n",
1690 reset_event.count[MTK_EVENT_TSO_ALIGN]);
1691 seq_printf(seq, " RFIFO OV: %d\n",
1692 reset_event.count[MTK_EVENT_RFIFO_OV]);
1693 seq_printf(seq, " RFIFO UF: %d\n",
1694 reset_event.count[MTK_EVENT_RFIFO_UF]);
1695 seq_printf(seq, " Force: %d\n",
1696 reset_event.count[MTK_EVENT_FORCE]);
1697 seq_printf(seq, "----------------------------\n");
1698 seq_printf(seq, " Warm Cnt: %d\n",
1699 reset_event.count[MTK_EVENT_WARM_CNT]);
1700 seq_printf(seq, " Cold Cnt: %d\n",
1701 reset_event.count[MTK_EVENT_COLD_CNT]);
1702 seq_printf(seq, " Total Cnt: %d\n",
1703 reset_event.count[MTK_EVENT_TOTAL_CNT]);
1704
1705 return 0;
1706}
1707
1708static int reset_event_open(struct inode *inode, struct file *file)
1709{
1710 return single_open(file, reset_event_read, 0);
1711}
1712
1713ssize_t reset_event_write(struct file *file, const char __user *buffer,
1714 size_t count, loff_t *data)
1715{
1716 struct mtk_eth *eth = g_eth;
1717 struct mtk_reset_event *reset_event = &eth->reset_event;
1718
1719 memset(reset_event, 0, sizeof(struct mtk_reset_event));
1720 pr_info("MTK reset event counter is cleared !\n");
1721
1722 return count;
1723}
1724
1725static const struct file_operations reset_event_fops = {
1726 .owner = THIS_MODULE,
1727 .open = reset_event_open,
1728 .read = seq_read,
1729 .llseek = seq_lseek,
1730 .write = reset_event_write,
1731 .release = single_release
1732};
1733
1734
developerfd40db22021-04-29 10:08:25 +08001735struct proc_dir_entry *proc_reg_dir;
developer8051e042022-04-08 13:26:36 +08001736static struct proc_dir_entry *proc_esw_cnt, *proc_dbg_regs, *proc_reset_event;
developerfd40db22021-04-29 10:08:25 +08001737
1738int debug_proc_init(struct mtk_eth *eth)
1739{
1740 g_eth = eth;
1741
1742 if (!proc_reg_dir)
1743 proc_reg_dir = proc_mkdir(PROCREG_DIR, NULL);
1744
1745 proc_tx_ring =
1746 proc_create(PROCREG_TXRING, 0, proc_reg_dir, &tx_ring_fops);
1747 if (!proc_tx_ring)
1748 pr_notice("!! FAIL to create %s PROC !!\n", PROCREG_TXRING);
1749
developer8051e042022-04-08 13:26:36 +08001750 proc_hwtx_ring =
1751 proc_create(PROCREG_HWTXRING, 0, proc_reg_dir, &hwtx_ring_fops);
1752 if (!proc_hwtx_ring)
1753 pr_notice("!! FAIL to create %s PROC !!\n", PROCREG_HWTXRING);
1754
developerfd40db22021-04-29 10:08:25 +08001755 proc_rx_ring =
1756 proc_create(PROCREG_RXRING, 0, proc_reg_dir, &rx_ring_fops);
1757 if (!proc_rx_ring)
1758 pr_notice("!! FAIL to create %s PROC !!\n", PROCREG_RXRING);
1759
1760 proc_esw_cnt =
1761 proc_create(PROCREG_ESW_CNT, 0, proc_reg_dir, &switch_count_fops);
1762 if (!proc_esw_cnt)
1763 pr_notice("!! FAIL to create %s PROC !!\n", PROCREG_ESW_CNT);
1764
1765 proc_dbg_regs =
1766 proc_create(PROCREG_DBG_REGS, 0, proc_reg_dir, &dbg_regs_fops);
1767 if (!proc_dbg_regs)
1768 pr_notice("!! FAIL to create %s PROC !!\n", PROCREG_DBG_REGS);
1769
developer77d03a72021-06-06 00:06:00 +08001770 if (g_eth->hwlro) {
1771 proc_hw_lro_stats =
1772 proc_create(PROCREG_HW_LRO_STATS, 0, proc_reg_dir,
1773 &hw_lro_stats_fops);
1774 if (!proc_hw_lro_stats)
1775 pr_info("!! FAIL to create %s PROC !!\n", PROCREG_HW_LRO_STATS);
1776
1777 proc_hw_lro_auto_tlb =
1778 proc_create(PROCREG_HW_LRO_AUTO_TLB, 0, proc_reg_dir,
1779 &hw_lro_auto_tlb_fops);
1780 if (!proc_hw_lro_auto_tlb)
1781 pr_info("!! FAIL to create %s PROC !!\n",
1782 PROCREG_HW_LRO_AUTO_TLB);
1783 }
1784
developer8051e042022-04-08 13:26:36 +08001785 proc_reset_event =
1786 proc_create(PROCREG_RESET_EVENT, 0, proc_reg_dir, &reset_event_fops);
1787 if (!proc_reset_event)
1788 pr_notice("!! FAIL to create %s PROC !!\n", PROCREG_RESET_EVENT);
1789
developerfd40db22021-04-29 10:08:25 +08001790 return 0;
1791}
1792
1793void debug_proc_exit(void)
1794{
1795 if (proc_tx_ring)
1796 remove_proc_entry(PROCREG_TXRING, proc_reg_dir);
developer8051e042022-04-08 13:26:36 +08001797 if (proc_hwtx_ring)
1798 remove_proc_entry(PROCREG_HWTXRING, proc_reg_dir);
developerfd40db22021-04-29 10:08:25 +08001799 if (proc_rx_ring)
1800 remove_proc_entry(PROCREG_RXRING, proc_reg_dir);
1801
1802 if (proc_esw_cnt)
1803 remove_proc_entry(PROCREG_ESW_CNT, proc_reg_dir);
1804
1805 if (proc_reg_dir)
1806 remove_proc_entry(PROCREG_DIR, 0);
1807
1808 if (proc_dbg_regs)
1809 remove_proc_entry(PROCREG_DBG_REGS, proc_reg_dir);
developer77d03a72021-06-06 00:06:00 +08001810
1811 if (g_eth->hwlro) {
1812 if (proc_hw_lro_stats)
1813 remove_proc_entry(PROCREG_HW_LRO_STATS, proc_reg_dir);
1814
1815 if (proc_hw_lro_auto_tlb)
1816 remove_proc_entry(PROCREG_HW_LRO_AUTO_TLB, proc_reg_dir);
1817 }
developer8051e042022-04-08 13:26:36 +08001818
1819 if (proc_reset_event)
1820 remove_proc_entry(PROCREG_RESET_EVENT, proc_reg_dir);
developerfd40db22021-04-29 10:08:25 +08001821}
1822