developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0 OR MIT) |
| 2 | /* |
| 3 | * Copyright (C) 2021 MediaTek Inc. |
| 4 | * Author: Sam.Shih <sam.shih@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | #include "mt7988.dtsi" |
| 9 | |
| 10 | / { |
| 11 | model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB"; |
| 12 | compatible = "mediatek,mt7988a-dsa-10g-spim-snand", |
| 13 | /* Reserve this for DVFS if creating new dts */ |
| 14 | "mediatek,mt7988"; |
| 15 | |
| 16 | chosen { |
| 17 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 18 | earlycon=uart8250,mmio32,0x11000000 \ |
| 19 | pci=pcie_bus_perf"; |
| 20 | }; |
| 21 | |
| 22 | memory { |
| 23 | reg = <0 0x40000000 0 0x10000000>; |
| 24 | }; |
| 25 | |
| 26 | nmbm_spim_nand { |
| 27 | compatible = "generic,nmbm"; |
| 28 | |
| 29 | #address-cells = <1>; |
| 30 | #size-cells = <1>; |
| 31 | |
| 32 | lower-mtd-device = <&spi_nand>; |
| 33 | forced-create; |
| 34 | |
| 35 | partitions { |
| 36 | compatible = "fixed-partitions"; |
| 37 | #address-cells = <1>; |
| 38 | #size-cells = <1>; |
| 39 | |
| 40 | partition@0 { |
| 41 | label = "BL2"; |
| 42 | reg = <0x00000 0x0100000>; |
| 43 | read-only; |
| 44 | }; |
| 45 | |
| 46 | partition@100000 { |
| 47 | label = "u-boot-env"; |
| 48 | reg = <0x0100000 0x0080000>; |
| 49 | }; |
| 50 | |
| 51 | factory: partition@180000 { |
| 52 | label = "Factory"; |
| 53 | reg = <0x180000 0x0400000>; |
| 54 | }; |
| 55 | |
| 56 | partition@580000 { |
| 57 | label = "FIP"; |
| 58 | reg = <0x580000 0x0200000>; |
| 59 | }; |
| 60 | |
| 61 | partition@780000 { |
| 62 | label = "ubi"; |
developer | baa8f60 | 2022-12-07 17:07:51 +0800 | [diff] [blame] | 63 | reg = <0x780000 0x7080000>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 64 | }; |
| 65 | }; |
| 66 | }; |
| 67 | |
| 68 | wsys_adie: wsys_adie@0 { |
| 69 | // fpga cases need to manual change adie_id / sku_type for dvt only |
| 70 | compatible = "mediatek,rebb-mt7988-adie"; |
| 71 | adie_id = <7976>; |
| 72 | sku_type = <3000>; |
| 73 | }; |
developer | 3594afb | 2022-10-25 13:22:53 +0800 | [diff] [blame] | 74 | |
| 75 | sound_wm8960 { |
| 76 | compatible = "mediatek,mt79xx-wm8960-machine"; |
| 77 | mediatek,platform = <&afe>; |
| 78 | audio-routing = "Headphone", "HP_L", |
| 79 | "Headphone", "HP_R", |
| 80 | "LINPUT1", "AMIC", |
| 81 | "RINPUT1", "AMIC"; |
| 82 | mediatek,audio-codec = <&wm8960>; |
| 83 | status = "disabled"; |
| 84 | }; |
| 85 | |
| 86 | sound_si3218x { |
| 87 | compatible = "mediatek,mt79xx-si3218x-machine"; |
| 88 | mediatek,platform = <&afe>; |
| 89 | mediatek,ext-codec = <&proslic_spi>; |
| 90 | status = "disabled"; |
| 91 | }; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 92 | }; |
| 93 | |
| 94 | &fan { |
| 95 | pwms = <&pwm 0 50000 0>; |
| 96 | status = "okay"; |
| 97 | }; |
| 98 | |
developer | 3594afb | 2022-10-25 13:22:53 +0800 | [diff] [blame] | 99 | &afe { |
| 100 | pinctrl-names = "default"; |
| 101 | pinctrl-0 = <&pcm_pins>; |
| 102 | status = "okay"; |
| 103 | }; |
| 104 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 105 | &pwm { |
| 106 | status = "okay"; |
| 107 | }; |
| 108 | |
| 109 | &uart0 { |
| 110 | status = "okay"; |
| 111 | }; |
| 112 | |
developer | bb0d2de | 2023-04-17 18:27:06 +0800 | [diff] [blame] | 113 | &uart1 { |
| 114 | pinctrl-names = "default"; |
| 115 | pinctrl-0 = <&uart1_pins>; |
| 116 | status = "okay"; |
| 117 | }; |
| 118 | |
developer | 86e69ba | 2022-12-26 12:05:48 +0800 | [diff] [blame] | 119 | &i2c0 { |
| 120 | pinctrl-names = "default"; |
| 121 | pinctrl-0 = <&i2c0_pins>; |
| 122 | status = "okay"; |
| 123 | |
| 124 | rt5190a_64: rt5190a@64 { |
| 125 | compatible = "richtek,rt5190a"; |
| 126 | reg = <0x64>; |
| 127 | /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/ |
| 128 | vin2-supply = <&rt5190_buck1>; |
| 129 | vin3-supply = <&rt5190_buck1>; |
| 130 | vin4-supply = <&rt5190_buck1>; |
| 131 | |
| 132 | regulators { |
| 133 | rt5190_buck1: buck1 { |
| 134 | regulator-name = "rt5190a-buck1"; |
| 135 | regulator-min-microvolt = <5090000>; |
| 136 | regulator-max-microvolt = <5090000>; |
| 137 | regulator-allowed-modes = |
| 138 | <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>; |
| 139 | regulator-boot-on; |
| 140 | }; |
| 141 | buck2 { |
| 142 | regulator-name = "vcore"; |
| 143 | regulator-min-microvolt = <600000>; |
| 144 | regulator-max-microvolt = <1400000>; |
| 145 | regulator-boot-on; |
| 146 | }; |
| 147 | buck3 { |
| 148 | regulator-name = "proc"; |
| 149 | regulator-min-microvolt = <600000>; |
| 150 | regulator-max-microvolt = <1400000>; |
| 151 | regulator-boot-on; |
| 152 | }; |
| 153 | buck4 { |
| 154 | regulator-name = "rt5190a-buck4"; |
| 155 | regulator-min-microvolt = <850000>; |
| 156 | regulator-max-microvolt = <850000>; |
| 157 | regulator-allowed-modes = |
| 158 | <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>; |
| 159 | regulator-boot-on; |
| 160 | }; |
| 161 | ldo { |
| 162 | regulator-name = "rt5190a-ldo"; |
| 163 | regulator-min-microvolt = <1200000>; |
| 164 | regulator-max-microvolt = <1200000>; |
| 165 | regulator-boot-on; |
| 166 | }; |
| 167 | }; |
| 168 | }; |
| 169 | }; |
| 170 | |
developer | 3594afb | 2022-10-25 13:22:53 +0800 | [diff] [blame] | 171 | &i2c1 { |
| 172 | pinctrl-names = "default"; |
| 173 | pinctrl-0 = <&i2c1_pins>; |
| 174 | status = "okay"; |
| 175 | |
| 176 | wm8960: wm8960@1a { |
| 177 | compatible = "wlf,wm8960"; |
| 178 | reg = <0x1a>; |
| 179 | }; |
developer | f9d3103 | 2023-03-03 20:54:33 +0800 | [diff] [blame] | 180 | |
| 181 | dps368: dps368@77 { |
| 182 | compatible = "infineon,dps310"; |
| 183 | reg = <0x77>; |
| 184 | }; |
developer | 3594afb | 2022-10-25 13:22:53 +0800 | [diff] [blame] | 185 | }; |
| 186 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 187 | &spi0 { |
| 188 | pinctrl-names = "default"; |
| 189 | pinctrl-0 = <&spi0_flash_pins>; |
| 190 | status = "okay"; |
| 191 | |
| 192 | spi_nand: spi_nand@0 { |
| 193 | #address-cells = <1>; |
| 194 | #size-cells = <1>; |
| 195 | compatible = "spi-nand"; |
| 196 | spi-cal-enable; |
| 197 | spi-cal-mode = "read-data"; |
| 198 | spi-cal-datalen = <7>; |
| 199 | spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>; |
| 200 | spi-cal-addrlen = <5>; |
| 201 | spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>; |
| 202 | reg = <0>; |
| 203 | spi-max-frequency = <52000000>; |
developer | 5fb8060 | 2023-05-02 18:54:53 +0800 | [diff] [blame] | 204 | spi-tx-bus-width = <4>; |
| 205 | spi-rx-bus-width = <4>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 206 | }; |
| 207 | }; |
| 208 | |
| 209 | &spi1 { |
| 210 | pinctrl-names = "default"; |
| 211 | /* pin shared with snfi */ |
| 212 | pinctrl-0 = <&spic_pins>; |
| 213 | status = "disabled"; |
developer | 3594afb | 2022-10-25 13:22:53 +0800 | [diff] [blame] | 214 | |
| 215 | proslic_spi: proslic_spi@0 { |
| 216 | compatible = "silabs,proslic_spi"; |
| 217 | reg = <0>; |
| 218 | spi-max-frequency = <10000000>; |
| 219 | spi-cpha = <1>; |
| 220 | spi-cpol = <1>; |
| 221 | channel_count = <1>; |
| 222 | debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */ |
| 223 | reset_gpio = <&pio 54 0>; |
| 224 | ig,enable-spi = <1>; /* 1: Enable, 0: Disable */ |
| 225 | }; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 226 | }; |
| 227 | |
| 228 | &pcie0 { |
| 229 | pinctrl-names = "default"; |
| 230 | pinctrl-0 = <&pcie0_pins>; |
| 231 | status = "okay"; |
| 232 | }; |
| 233 | |
| 234 | &pcie1 { |
| 235 | pinctrl-names = "default"; |
| 236 | pinctrl-0 = <&pcie1_pins>; |
| 237 | status = "okay"; |
| 238 | }; |
| 239 | |
| 240 | &pcie2 { |
| 241 | pinctrl-names = "default"; |
| 242 | pinctrl-0 = <&pcie2_pins>; |
| 243 | status = "disabled"; |
| 244 | }; |
| 245 | |
| 246 | &pcie3 { |
| 247 | pinctrl-names = "default"; |
| 248 | pinctrl-0 = <&pcie3_pins>; |
| 249 | status = "okay"; |
| 250 | }; |
| 251 | |
| 252 | &pio { |
developer | 24ba51c | 2022-11-15 11:22:46 +0800 | [diff] [blame] | 253 | mdio0_pins: mdio0-pins { |
| 254 | mux { |
| 255 | function = "mdio"; |
| 256 | groups = "mdc_mdio0"; |
| 257 | }; |
| 258 | |
| 259 | conf { |
| 260 | groups = "mdc_mdio0"; |
| 261 | drive-strength = <MTK_DRIVE_8mA>; |
| 262 | }; |
| 263 | }; |
| 264 | |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame] | 265 | gbe0_led0_pins: gbe0-pins { |
developer | 447cb00 | 2023-04-06 17:54:54 +0800 | [diff] [blame] | 266 | mux { |
| 267 | function = "led"; |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame] | 268 | groups = "gbe0_led0"; |
developer | 447cb00 | 2023-04-06 17:54:54 +0800 | [diff] [blame] | 269 | }; |
| 270 | }; |
| 271 | |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame] | 272 | gbe1_led0_pins: gbe1-pins { |
| 273 | mux { |
| 274 | function = "led"; |
| 275 | groups = "gbe1_led0"; |
| 276 | }; |
| 277 | }; |
| 278 | |
| 279 | gbe2_led0_pins: gbe2-pins { |
| 280 | mux { |
| 281 | function = "led"; |
| 282 | groups = "gbe2_led0"; |
| 283 | }; |
| 284 | }; |
| 285 | |
| 286 | gbe3_led0_pins: gbe3-pins { |
| 287 | mux { |
| 288 | function = "led"; |
| 289 | groups = "gbe3_led0"; |
| 290 | }; |
| 291 | }; |
| 292 | |
developer | 86e69ba | 2022-12-26 12:05:48 +0800 | [diff] [blame] | 293 | i2c0_pins: i2c0-pins-g0 { |
| 294 | mux { |
| 295 | function = "i2c"; |
| 296 | groups = "i2c0_1"; |
| 297 | }; |
| 298 | }; |
| 299 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 300 | pcie0_pins: pcie0-pins { |
| 301 | mux { |
| 302 | function = "pcie"; |
| 303 | groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", |
| 304 | "pcie_wake_n0_0"; |
| 305 | }; |
| 306 | }; |
| 307 | |
| 308 | pcie1_pins: pcie1-pins { |
| 309 | mux { |
| 310 | function = "pcie"; |
| 311 | groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", |
| 312 | "pcie_wake_n1_0"; |
| 313 | }; |
| 314 | }; |
| 315 | |
| 316 | pcie2_pins: pcie2-pins { |
| 317 | mux { |
| 318 | function = "pcie"; |
| 319 | groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", |
| 320 | "pcie_wake_n2_0"; |
| 321 | }; |
| 322 | }; |
| 323 | |
| 324 | pcie3_pins: pcie3-pins { |
| 325 | mux { |
| 326 | function = "pcie"; |
| 327 | groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", |
| 328 | "pcie_wake_n3_0"; |
| 329 | }; |
| 330 | }; |
| 331 | |
| 332 | spi0_flash_pins: spi0-pins { |
| 333 | mux { |
| 334 | function = "spi"; |
| 335 | groups = "spi0", "spi0_wp_hold"; |
| 336 | }; |
| 337 | }; |
| 338 | |
| 339 | spic_pins: spi1-pins { |
| 340 | mux { |
| 341 | function = "spi"; |
developer | 3594afb | 2022-10-25 13:22:53 +0800 | [diff] [blame] | 342 | groups = "spi1"; |
| 343 | }; |
| 344 | }; |
| 345 | |
| 346 | i2c1_pins: i2c1-pins { |
| 347 | mux { |
| 348 | function = "i2c"; |
| 349 | groups = "i2c1_0"; |
| 350 | }; |
| 351 | }; |
| 352 | |
| 353 | i2s_pins: i2s-pins { |
| 354 | mux { |
| 355 | function = "audio"; |
| 356 | groups = "i2s"; |
| 357 | }; |
| 358 | }; |
| 359 | |
| 360 | pcm_pins: pcm-pins { |
| 361 | mux { |
| 362 | function = "audio"; |
| 363 | groups = "pcm"; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 364 | }; |
| 365 | }; |
developer | bb0d2de | 2023-04-17 18:27:06 +0800 | [diff] [blame] | 366 | |
| 367 | uart1_pins: uart1-pins { |
| 368 | mux { |
| 369 | function = "uart"; |
| 370 | groups = "uart1_2"; |
| 371 | }; |
| 372 | }; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 373 | }; |
| 374 | |
| 375 | &watchdog { |
| 376 | status = "disabled"; |
| 377 | }; |
| 378 | |
| 379 | ð { |
developer | 24ba51c | 2022-11-15 11:22:46 +0800 | [diff] [blame] | 380 | pinctrl-names = "default"; |
developer | 941468f | 2023-04-10 15:21:02 +0800 | [diff] [blame] | 381 | pinctrl-0 = <&mdio0_pins>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 382 | status = "okay"; |
| 383 | |
| 384 | gmac0: mac@0 { |
| 385 | compatible = "mediatek,eth-mac"; |
| 386 | reg = <0>; |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 387 | mac-type = "xgdm"; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 388 | phy-mode = "10gbase-kr"; |
| 389 | |
| 390 | fixed-link { |
developer | f0145c9 | 2023-03-23 23:16:17 +0800 | [diff] [blame] | 391 | speed = <10000>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 392 | full-duplex; |
| 393 | pause; |
| 394 | }; |
| 395 | }; |
| 396 | |
| 397 | gmac1: mac@1 { |
| 398 | compatible = "mediatek,eth-mac"; |
| 399 | reg = <1>; |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 400 | mac-type = "xgdm"; |
developer | f0145c9 | 2023-03-23 23:16:17 +0800 | [diff] [blame] | 401 | phy-mode = "usxgmii"; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 402 | phy-handle = <&phy0>; |
| 403 | }; |
| 404 | |
| 405 | gmac2: mac@2 { |
| 406 | compatible = "mediatek,eth-mac"; |
| 407 | reg = <2>; |
developer | 30e13e7 | 2022-11-03 10:21:24 +0800 | [diff] [blame] | 408 | mac-type = "xgdm"; |
developer | f0145c9 | 2023-03-23 23:16:17 +0800 | [diff] [blame] | 409 | phy-mode = "usxgmii"; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 410 | phy-handle = <&phy1>; |
| 411 | }; |
| 412 | |
| 413 | mdio: mdio-bus { |
| 414 | #address-cells = <1>; |
| 415 | #size-cells = <0>; |
developer | c4d8da7 | 2023-03-16 14:37:28 +0800 | [diff] [blame] | 416 | clock-frequency = <10500000>; |
developer | 24ba51c | 2022-11-15 11:22:46 +0800 | [diff] [blame] | 417 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 418 | phy0: ethernet-phy@0 { |
| 419 | reg = <0>; |
| 420 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | 6067807 | 2022-11-23 15:52:54 +0800 | [diff] [blame] | 421 | reset-gpios = <&pio 72 1>; |
developer | 265607f | 2023-03-01 18:37:46 +0800 | [diff] [blame] | 422 | reset-assert-us = <100000>; |
| 423 | reset-deassert-us = <221000>; |
developer | 301205c | 2023-05-24 15:39:32 +0800 | [diff] [blame^] | 424 | mdi-reversal = /bits/ 16 <1>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 425 | }; |
| 426 | |
| 427 | phy1: ethernet-phy@8 { |
| 428 | reg = <8>; |
| 429 | compatible = "ethernet-phy-ieee802.3-c45"; |
developer | 6067807 | 2022-11-23 15:52:54 +0800 | [diff] [blame] | 430 | reset-gpios = <&pio 71 1>; |
developer | 265607f | 2023-03-01 18:37:46 +0800 | [diff] [blame] | 431 | reset-assert-us = <100000>; |
| 432 | reset-deassert-us = <221000>; |
developer | 301205c | 2023-05-24 15:39:32 +0800 | [diff] [blame^] | 433 | mdi-reversal = /bits/ 16 <1>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 434 | }; |
| 435 | |
| 436 | switch@0 { |
| 437 | compatible = "mediatek,mt7988"; |
| 438 | reg = <31>; |
| 439 | ports { |
| 440 | #address-cells = <1>; |
| 441 | #size-cells = <0>; |
| 442 | |
| 443 | port@0 { |
| 444 | reg = <0>; |
| 445 | label = "lan0"; |
developer | a36549c | 2022-10-04 16:26:13 +0800 | [diff] [blame] | 446 | phy-mode = "gmii"; |
| 447 | phy-handle = <&sphy0>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 448 | }; |
| 449 | |
| 450 | port@1 { |
| 451 | reg = <1>; |
| 452 | label = "lan1"; |
developer | a36549c | 2022-10-04 16:26:13 +0800 | [diff] [blame] | 453 | phy-mode = "gmii"; |
| 454 | phy-handle = <&sphy1>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 455 | }; |
| 456 | |
| 457 | port@2 { |
| 458 | reg = <2>; |
| 459 | label = "lan2"; |
developer | a36549c | 2022-10-04 16:26:13 +0800 | [diff] [blame] | 460 | phy-mode = "gmii"; |
| 461 | phy-handle = <&sphy2>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 462 | }; |
| 463 | |
| 464 | port@3 { |
| 465 | reg = <3>; |
| 466 | label = "lan3"; |
developer | a36549c | 2022-10-04 16:26:13 +0800 | [diff] [blame] | 467 | phy-mode = "gmii"; |
| 468 | phy-handle = <&sphy3>; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 469 | }; |
| 470 | |
| 471 | port@6 { |
| 472 | reg = <6>; |
| 473 | label = "cpu"; |
| 474 | ethernet = <&gmac0>; |
| 475 | phy-mode = "10gbase-kr"; |
| 476 | |
| 477 | fixed-link { |
| 478 | speed = <10000>; |
| 479 | full-duplex; |
| 480 | pause; |
| 481 | }; |
| 482 | }; |
| 483 | }; |
developer | a36549c | 2022-10-04 16:26:13 +0800 | [diff] [blame] | 484 | |
| 485 | mdio { |
| 486 | compatible = "mediatek,dsa-slave-mdio"; |
| 487 | #address-cells = <1>; |
| 488 | #size-cells = <0>; |
| 489 | |
| 490 | sphy0: switch_phy0@0 { |
| 491 | compatible = "ethernet-phy-id03a2.9481"; |
| 492 | reg = <0>; |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame] | 493 | pinctrl-names = "gbe-led"; |
| 494 | pinctrl-0 = <&gbe0_led0_pins>; |
developer | a36549c | 2022-10-04 16:26:13 +0800 | [diff] [blame] | 495 | nvmem-cells = <&phy_calibration_p0>; |
| 496 | nvmem-cell-names = "phy-cal-data"; |
| 497 | }; |
| 498 | |
| 499 | sphy1: switch_phy1@1 { |
| 500 | compatible = "ethernet-phy-id03a2.9481"; |
| 501 | reg = <1>; |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame] | 502 | pinctrl-names = "gbe-led"; |
| 503 | pinctrl-0 = <&gbe1_led0_pins>; |
developer | a36549c | 2022-10-04 16:26:13 +0800 | [diff] [blame] | 504 | nvmem-cells = <&phy_calibration_p1>; |
| 505 | nvmem-cell-names = "phy-cal-data"; |
| 506 | }; |
| 507 | |
| 508 | sphy2: switch_phy2@2 { |
| 509 | compatible = "ethernet-phy-id03a2.9481"; |
| 510 | reg = <2>; |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame] | 511 | pinctrl-names = "gbe-led"; |
| 512 | pinctrl-0 = <&gbe2_led0_pins>; |
developer | a36549c | 2022-10-04 16:26:13 +0800 | [diff] [blame] | 513 | nvmem-cells = <&phy_calibration_p2>; |
| 514 | nvmem-cell-names = "phy-cal-data"; |
| 515 | }; |
| 516 | |
| 517 | sphy3: switch_phy3@3 { |
| 518 | compatible = "ethernet-phy-id03a2.9481"; |
| 519 | reg = <3>; |
developer | caca1df | 2023-05-17 10:54:49 +0800 | [diff] [blame] | 520 | pinctrl-names = "gbe-led"; |
| 521 | pinctrl-0 = <&gbe3_led0_pins>; |
developer | a36549c | 2022-10-04 16:26:13 +0800 | [diff] [blame] | 522 | nvmem-cells = <&phy_calibration_p3>; |
| 523 | nvmem-cell-names = "phy-cal-data"; |
| 524 | }; |
| 525 | }; |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 526 | }; |
| 527 | }; |
| 528 | }; |
| 529 | |
| 530 | &hnat { |
| 531 | mtketh-wan = "eth1"; |
| 532 | mtketh-lan = "lan"; |
| 533 | mtketh-lan2 = "eth2"; |
| 534 | mtketh-max-gmac = <3>; |
| 535 | status = "okay"; |
| 536 | }; |
developer | de8a106 | 2023-01-31 17:00:33 +0800 | [diff] [blame] | 537 | |
| 538 | &slot0 { |
| 539 | mt7996@0,0 { |
| 540 | reg = <0x0000 0 0 0 0>; |
| 541 | device_type = "pci"; |
| 542 | mediatek,mtd-eeprom = <&factory 0x0>; |
| 543 | }; |
| 544 | }; |