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developer2cdaeb12022-10-04 20:25:05 +08001// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 * Author: Sam.Shih <sam.shih@mediatek.com>
5 */
6
7/dts-v1/;
8#include "mt7988.dtsi"
9
10/ {
11 model = "MediaTek MT7988A DSA 10G SPIM-NAND RFB";
12 compatible = "mediatek,mt7988a-dsa-10g-spim-snand",
13 /* Reserve this for DVFS if creating new dts */
14 "mediatek,mt7988";
15
16 chosen {
17 bootargs = "console=ttyS0,115200n1 loglevel=8 \
18 earlycon=uart8250,mmio32,0x11000000 \
19 pci=pcie_bus_perf";
20 };
21
22 memory {
23 reg = <0 0x40000000 0 0x10000000>;
24 };
25
26 nmbm_spim_nand {
27 compatible = "generic,nmbm";
28
29 #address-cells = <1>;
30 #size-cells = <1>;
31
32 lower-mtd-device = <&spi_nand>;
33 forced-create;
34
35 partitions {
36 compatible = "fixed-partitions";
37 #address-cells = <1>;
38 #size-cells = <1>;
39
40 partition@0 {
41 label = "BL2";
42 reg = <0x00000 0x0100000>;
43 read-only;
44 };
45
46 partition@100000 {
47 label = "u-boot-env";
48 reg = <0x0100000 0x0080000>;
49 };
50
51 factory: partition@180000 {
52 label = "Factory";
53 reg = <0x180000 0x0400000>;
54 };
55
56 partition@580000 {
57 label = "FIP";
58 reg = <0x580000 0x0200000>;
59 };
60
61 partition@780000 {
62 label = "ubi";
developerbaa8f602022-12-07 17:07:51 +080063 reg = <0x780000 0x7080000>;
developer2cdaeb12022-10-04 20:25:05 +080064 };
65 };
66 };
67
68 wsys_adie: wsys_adie@0 {
69 // fpga cases need to manual change adie_id / sku_type for dvt only
70 compatible = "mediatek,rebb-mt7988-adie";
71 adie_id = <7976>;
72 sku_type = <3000>;
73 };
developer3594afb2022-10-25 13:22:53 +080074
75 sound_wm8960 {
76 compatible = "mediatek,mt79xx-wm8960-machine";
77 mediatek,platform = <&afe>;
78 audio-routing = "Headphone", "HP_L",
79 "Headphone", "HP_R",
80 "LINPUT1", "AMIC",
81 "RINPUT1", "AMIC";
82 mediatek,audio-codec = <&wm8960>;
83 status = "disabled";
84 };
85
86 sound_si3218x {
87 compatible = "mediatek,mt79xx-si3218x-machine";
88 mediatek,platform = <&afe>;
89 mediatek,ext-codec = <&proslic_spi>;
90 status = "disabled";
91 };
developer2cdaeb12022-10-04 20:25:05 +080092};
93
94&fan {
95 pwms = <&pwm 0 50000 0>;
96 status = "okay";
97};
98
developer3594afb2022-10-25 13:22:53 +080099&afe {
100 pinctrl-names = "default";
101 pinctrl-0 = <&pcm_pins>;
102 status = "okay";
103};
104
developer2cdaeb12022-10-04 20:25:05 +0800105&pwm {
106 status = "okay";
107};
108
109&uart0 {
110 status = "okay";
111};
112
developer86e69ba2022-12-26 12:05:48 +0800113&i2c0 {
114 pinctrl-names = "default";
115 pinctrl-0 = <&i2c0_pins>;
116 status = "okay";
117
118 rt5190a_64: rt5190a@64 {
119 compatible = "richtek,rt5190a";
120 reg = <0x64>;
121 /*interrupts-extended = <&gpio26 0 IRQ_TYPE_LEVEL_LOW>;*/
122 vin2-supply = <&rt5190_buck1>;
123 vin3-supply = <&rt5190_buck1>;
124 vin4-supply = <&rt5190_buck1>;
125
126 regulators {
127 rt5190_buck1: buck1 {
128 regulator-name = "rt5190a-buck1";
129 regulator-min-microvolt = <5090000>;
130 regulator-max-microvolt = <5090000>;
131 regulator-allowed-modes =
132 <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
133 regulator-boot-on;
134 };
135 buck2 {
136 regulator-name = "vcore";
137 regulator-min-microvolt = <600000>;
138 regulator-max-microvolt = <1400000>;
139 regulator-boot-on;
140 };
141 buck3 {
142 regulator-name = "proc";
143 regulator-min-microvolt = <600000>;
144 regulator-max-microvolt = <1400000>;
145 regulator-boot-on;
146 };
147 buck4 {
148 regulator-name = "rt5190a-buck4";
149 regulator-min-microvolt = <850000>;
150 regulator-max-microvolt = <850000>;
151 regulator-allowed-modes =
152 <RT5190A_OPMODE_AUTO RT5190A_OPMODE_FPWM>;
153 regulator-boot-on;
154 };
155 ldo {
156 regulator-name = "rt5190a-ldo";
157 regulator-min-microvolt = <1200000>;
158 regulator-max-microvolt = <1200000>;
159 regulator-boot-on;
160 };
161 };
162 };
163};
164
developer3594afb2022-10-25 13:22:53 +0800165&i2c1 {
166 pinctrl-names = "default";
167 pinctrl-0 = <&i2c1_pins>;
168 status = "okay";
169
170 wm8960: wm8960@1a {
171 compatible = "wlf,wm8960";
172 reg = <0x1a>;
173 };
developerf9d31032023-03-03 20:54:33 +0800174
175 dps368: dps368@77 {
176 compatible = "infineon,dps310";
177 reg = <0x77>;
178 };
developer3594afb2022-10-25 13:22:53 +0800179};
180
developer2cdaeb12022-10-04 20:25:05 +0800181&spi0 {
182 pinctrl-names = "default";
183 pinctrl-0 = <&spi0_flash_pins>;
184 status = "okay";
185
186 spi_nand: spi_nand@0 {
187 #address-cells = <1>;
188 #size-cells = <1>;
189 compatible = "spi-nand";
190 spi-cal-enable;
191 spi-cal-mode = "read-data";
192 spi-cal-datalen = <7>;
193 spi-cal-data = /bits/ 8 <0x53 0x50 0x49 0x4E 0x41 0x4E 0x44>;
194 spi-cal-addrlen = <5>;
195 spi-cal-addr = /bits/ 32 <0x0 0x0 0x0 0x0 0x0>;
196 reg = <0>;
197 spi-max-frequency = <52000000>;
198 spi-tx-buswidth = <4>;
199 spi-rx-buswidth = <4>;
200 };
201};
202
203&spi1 {
204 pinctrl-names = "default";
205 /* pin shared with snfi */
206 pinctrl-0 = <&spic_pins>;
207 status = "disabled";
developer3594afb2022-10-25 13:22:53 +0800208
209 proslic_spi: proslic_spi@0 {
210 compatible = "silabs,proslic_spi";
211 reg = <0>;
212 spi-max-frequency = <10000000>;
213 spi-cpha = <1>;
214 spi-cpol = <1>;
215 channel_count = <1>;
216 debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */
217 reset_gpio = <&pio 54 0>;
218 ig,enable-spi = <1>; /* 1: Enable, 0: Disable */
219 };
developer2cdaeb12022-10-04 20:25:05 +0800220};
221
222&pcie0 {
223 pinctrl-names = "default";
224 pinctrl-0 = <&pcie0_pins>;
225 status = "okay";
226};
227
228&pcie1 {
229 pinctrl-names = "default";
230 pinctrl-0 = <&pcie1_pins>;
231 status = "okay";
232};
233
234&pcie2 {
235 pinctrl-names = "default";
236 pinctrl-0 = <&pcie2_pins>;
237 status = "disabled";
238};
239
240&pcie3 {
241 pinctrl-names = "default";
242 pinctrl-0 = <&pcie3_pins>;
243 status = "okay";
244};
245
246&pio {
developer24ba51c2022-11-15 11:22:46 +0800247 mdio0_pins: mdio0-pins {
248 mux {
249 function = "mdio";
250 groups = "mdc_mdio0";
251 };
252
253 conf {
254 groups = "mdc_mdio0";
255 drive-strength = <MTK_DRIVE_8mA>;
256 };
257 };
258
developer447cb002023-04-06 17:54:54 +0800259 gbe_led0_pins: gbe-pins {
260 mux {
261 function = "led";
262 groups = "gbe_led0";
263 };
264 };
265
developer86e69ba2022-12-26 12:05:48 +0800266 i2c0_pins: i2c0-pins-g0 {
267 mux {
268 function = "i2c";
269 groups = "i2c0_1";
270 };
271 };
272
developer2cdaeb12022-10-04 20:25:05 +0800273 pcie0_pins: pcie0-pins {
274 mux {
275 function = "pcie";
276 groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0",
277 "pcie_wake_n0_0";
278 };
279 };
280
281 pcie1_pins: pcie1-pins {
282 mux {
283 function = "pcie";
284 groups = "pcie_2l_1_pereset", "pcie_clk_req_n1",
285 "pcie_wake_n1_0";
286 };
287 };
288
289 pcie2_pins: pcie2-pins {
290 mux {
291 function = "pcie";
292 groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0",
293 "pcie_wake_n2_0";
294 };
295 };
296
297 pcie3_pins: pcie3-pins {
298 mux {
299 function = "pcie";
300 groups = "pcie_1l_1_pereset", "pcie_clk_req_n3",
301 "pcie_wake_n3_0";
302 };
303 };
304
305 spi0_flash_pins: spi0-pins {
306 mux {
307 function = "spi";
308 groups = "spi0", "spi0_wp_hold";
309 };
310 };
311
312 spic_pins: spi1-pins {
313 mux {
314 function = "spi";
developer3594afb2022-10-25 13:22:53 +0800315 groups = "spi1";
316 };
317 };
318
319 i2c1_pins: i2c1-pins {
320 mux {
321 function = "i2c";
322 groups = "i2c1_0";
323 };
324 };
325
326 i2s_pins: i2s-pins {
327 mux {
328 function = "audio";
329 groups = "i2s";
330 };
331 };
332
333 pcm_pins: pcm-pins {
334 mux {
335 function = "audio";
336 groups = "pcm";
developer2cdaeb12022-10-04 20:25:05 +0800337 };
338 };
339};
340
341&watchdog {
342 status = "disabled";
343};
344
345&eth {
developer24ba51c2022-11-15 11:22:46 +0800346 pinctrl-names = "default";
developer447cb002023-04-06 17:54:54 +0800347 pinctrl-0 = <&mdio0_pins>, <&gbe_led0_pins>;
developer2cdaeb12022-10-04 20:25:05 +0800348 status = "okay";
349
350 gmac0: mac@0 {
351 compatible = "mediatek,eth-mac";
352 reg = <0>;
developer30e13e72022-11-03 10:21:24 +0800353 mac-type = "xgdm";
developer2cdaeb12022-10-04 20:25:05 +0800354 phy-mode = "10gbase-kr";
355
356 fixed-link {
developerf0145c92023-03-23 23:16:17 +0800357 speed = <10000>;
developer2cdaeb12022-10-04 20:25:05 +0800358 full-duplex;
359 pause;
360 };
361 };
362
363 gmac1: mac@1 {
364 compatible = "mediatek,eth-mac";
365 reg = <1>;
developer30e13e72022-11-03 10:21:24 +0800366 mac-type = "xgdm";
developerf0145c92023-03-23 23:16:17 +0800367 phy-mode = "usxgmii";
developer2cdaeb12022-10-04 20:25:05 +0800368 phy-handle = <&phy0>;
369 };
370
371 gmac2: mac@2 {
372 compatible = "mediatek,eth-mac";
373 reg = <2>;
developer30e13e72022-11-03 10:21:24 +0800374 mac-type = "xgdm";
developerf0145c92023-03-23 23:16:17 +0800375 phy-mode = "usxgmii";
developer2cdaeb12022-10-04 20:25:05 +0800376 phy-handle = <&phy1>;
377 };
378
379 mdio: mdio-bus {
380 #address-cells = <1>;
381 #size-cells = <0>;
developerc4d8da72023-03-16 14:37:28 +0800382 clock-frequency = <10500000>;
developer24ba51c2022-11-15 11:22:46 +0800383
developer2cdaeb12022-10-04 20:25:05 +0800384 phy0: ethernet-phy@0 {
385 reg = <0>;
386 compatible = "ethernet-phy-ieee802.3-c45";
developer60678072022-11-23 15:52:54 +0800387 reset-gpios = <&pio 72 1>;
developer265607f2023-03-01 18:37:46 +0800388 reset-assert-us = <100000>;
389 reset-deassert-us = <221000>;
developer2cdaeb12022-10-04 20:25:05 +0800390 };
391
392 phy1: ethernet-phy@8 {
393 reg = <8>;
394 compatible = "ethernet-phy-ieee802.3-c45";
developer60678072022-11-23 15:52:54 +0800395 reset-gpios = <&pio 71 1>;
developer265607f2023-03-01 18:37:46 +0800396 reset-assert-us = <100000>;
397 reset-deassert-us = <221000>;
developer2cdaeb12022-10-04 20:25:05 +0800398 };
399
400 switch@0 {
401 compatible = "mediatek,mt7988";
402 reg = <31>;
403 ports {
404 #address-cells = <1>;
405 #size-cells = <0>;
406
407 port@0 {
408 reg = <0>;
409 label = "lan0";
developera36549c2022-10-04 16:26:13 +0800410 phy-mode = "gmii";
411 phy-handle = <&sphy0>;
developer2cdaeb12022-10-04 20:25:05 +0800412 };
413
414 port@1 {
415 reg = <1>;
416 label = "lan1";
developera36549c2022-10-04 16:26:13 +0800417 phy-mode = "gmii";
418 phy-handle = <&sphy1>;
developer2cdaeb12022-10-04 20:25:05 +0800419 };
420
421 port@2 {
422 reg = <2>;
423 label = "lan2";
developera36549c2022-10-04 16:26:13 +0800424 phy-mode = "gmii";
425 phy-handle = <&sphy2>;
developer2cdaeb12022-10-04 20:25:05 +0800426 };
427
428 port@3 {
429 reg = <3>;
430 label = "lan3";
developera36549c2022-10-04 16:26:13 +0800431 phy-mode = "gmii";
432 phy-handle = <&sphy3>;
developer2cdaeb12022-10-04 20:25:05 +0800433 };
434
435 port@6 {
436 reg = <6>;
437 label = "cpu";
438 ethernet = <&gmac0>;
439 phy-mode = "10gbase-kr";
440
441 fixed-link {
442 speed = <10000>;
443 full-duplex;
444 pause;
445 };
446 };
447 };
developera36549c2022-10-04 16:26:13 +0800448
449 mdio {
450 compatible = "mediatek,dsa-slave-mdio";
451 #address-cells = <1>;
452 #size-cells = <0>;
453
454 sphy0: switch_phy0@0 {
455 compatible = "ethernet-phy-id03a2.9481";
456 reg = <0>;
457 phy-mode = "gmii";
458 rext = "efuse";
459 tx_r50 = "efuse";
460 nvmem-cells = <&phy_calibration_p0>;
461 nvmem-cell-names = "phy-cal-data";
462 };
463
464 sphy1: switch_phy1@1 {
465 compatible = "ethernet-phy-id03a2.9481";
466 reg = <1>;
467 phy-mode = "gmii";
468 rext = "efuse";
469 tx_r50 = "efuse";
470 nvmem-cells = <&phy_calibration_p1>;
471 nvmem-cell-names = "phy-cal-data";
472 };
473
474 sphy2: switch_phy2@2 {
475 compatible = "ethernet-phy-id03a2.9481";
476 reg = <2>;
477 phy-mode = "gmii";
478 rext = "efuse";
479 tx_r50 = "efuse";
480 nvmem-cells = <&phy_calibration_p2>;
481 nvmem-cell-names = "phy-cal-data";
482 };
483
484 sphy3: switch_phy3@3 {
485 compatible = "ethernet-phy-id03a2.9481";
486 reg = <3>;
487 phy-mode = "gmii";
488 rext = "efuse";
489 tx_r50 = "efuse";
490 nvmem-cells = <&phy_calibration_p3>;
491 nvmem-cell-names = "phy-cal-data";
492 };
493 };
developer2cdaeb12022-10-04 20:25:05 +0800494 };
495 };
496};
497
498&hnat {
499 mtketh-wan = "eth1";
500 mtketh-lan = "lan";
501 mtketh-lan2 = "eth2";
502 mtketh-max-gmac = <3>;
503 status = "okay";
504};
developerde8a1062023-01-31 17:00:33 +0800505
506&slot0 {
507 mt7996@0,0 {
508 reg = <0x0000 0 0 0 0>;
509 device_type = "pci";
510 mediatek,mtd-eeprom = <&factory 0x0>;
511 };
512};