developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020 MediaTek Inc. |
| 3 | * Author: Sam.Shih <sam.shih@mediatek.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
| 15 | #include <dt-bindings/interrupt-controller/irq.h> |
| 16 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 17 | #include <dt-bindings/phy/phy.h> |
| 18 | #include <dt-bindings/reset/ti-syscon.h> |
developer | 2df324b | 2021-06-24 10:21:45 +0800 | [diff] [blame^] | 19 | #include <dt-bindings/clock/mt7986-clk.h> |
| 20 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 21 | / { |
| 22 | compatible = "mediatek,mt7986b-rfb"; |
| 23 | interrupt-parent = <&gic>; |
| 24 | #address-cells = <2>; |
| 25 | #size-cells = <2>; |
| 26 | cpus { |
| 27 | #address-cells = <1>; |
| 28 | #size-cells = <0>; |
| 29 | cpu@0 { |
| 30 | device_type = "cpu"; |
| 31 | compatible = "arm,cortex-a53"; |
| 32 | enable-method = "psci"; |
| 33 | reg = <0x0>; |
| 34 | }; |
| 35 | |
| 36 | cpu@1 { |
| 37 | device_type = "cpu"; |
| 38 | compatible = "arm,cortex-a53"; |
| 39 | enable-method = "psci"; |
| 40 | reg = <0x1>; |
| 41 | }; |
| 42 | |
| 43 | cpu@2 { |
| 44 | device_type = "cpu"; |
| 45 | compatible = "arm,cortex-a53"; |
| 46 | enable-method = "psci"; |
| 47 | reg = <0x2>; |
| 48 | }; |
| 49 | |
| 50 | cpu@3 { |
| 51 | device_type = "cpu"; |
| 52 | enable-method = "psci"; |
| 53 | compatible = "arm,cortex-a53"; |
| 54 | reg = <0x3>; |
| 55 | }; |
| 56 | }; |
| 57 | |
| 58 | wed: wed@15010000 { |
| 59 | compatible = "mediatek,wed"; |
| 60 | wed_num = <2>; |
| 61 | /* add this property for wed get the pci slot number. */ |
| 62 | pci_slot_map = <0>, <1>; |
| 63 | reg = <0 0x15010000 0 0x1000>, |
| 64 | <0 0x15011000 0 0x1000>; |
| 65 | interrupt-parent = <&gic>; |
| 66 | interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, |
| 67 | <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| 68 | }; |
| 69 | |
| 70 | wed2: wed2@15011000 { |
| 71 | compatible = "mediatek,wed2"; |
| 72 | wed_num = <2>; |
| 73 | reg = <0 0x15010000 0 0x1000>, |
| 74 | <0 0x15011000 0 0x1000>; |
| 75 | interrupt-parent = <&gic>; |
| 76 | interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, |
| 77 | <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| 78 | }; |
| 79 | |
| 80 | wdma: wdma@15104800 { |
| 81 | compatible = "mediatek,wed-wdma"; |
| 82 | reg = <0 0x15104800 0 0x400>, |
| 83 | <0 0x15104c00 0 0x400>; |
| 84 | }; |
| 85 | |
| 86 | ap2woccif: ap2woccif@151A5000 { |
| 87 | compatible = "mediatek,ap2woccif"; |
| 88 | reg = <0 0x151A5000 0 0x1000>, |
| 89 | <0 0x151AD000 0 0x1000>; |
| 90 | interrupt-parent = <&gic>; |
| 91 | interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, |
| 92 | <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; |
| 93 | }; |
| 94 | |
| 95 | wocpu0_ilm: wocpu0_ilm@151E0000 { |
| 96 | compatible = "mediatek,wocpu0_ilm"; |
| 97 | reg = <0 0x151E0000 0 0x8000>; |
| 98 | }; |
| 99 | |
| 100 | wocpu1_ilm: wocpu1_ilm@151F0000 { |
| 101 | compatible = "mediatek,wocpu1_ilm"; |
| 102 | reg = <0 0x151F0000 0 0x8000>; |
| 103 | }; |
| 104 | |
| 105 | wocpu_dlm: wocpu_dlm@151E8000 { |
| 106 | compatible = "mediatek,wocpu_dlm"; |
| 107 | reg = <0 0x151E8000 0 0x2000>, |
| 108 | <0 0x151F8000 0 0x2000>; |
| 109 | |
| 110 | resets = <ðsysrst 0>; |
| 111 | reset-names = "wocpu_rst"; |
| 112 | }; |
| 113 | |
| 114 | cpu_boot: wocpu_boot@15194000 { |
| 115 | compatible = "mediatek,wocpu_boot"; |
| 116 | reg = <0 0x15194000 0 0x1000>; |
| 117 | }; |
| 118 | |
| 119 | reserved-memory { |
| 120 | #address-cells = <2>; |
| 121 | #size-cells = <2>; |
| 122 | ranges; |
| 123 | |
| 124 | /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ |
| 125 | secmon_reserved: secmon@43000000 { |
| 126 | reg = <0 0x43000000 0 0x30000>; |
| 127 | no-map; |
| 128 | }; |
| 129 | |
| 130 | wmcpu_emi: wmcpu-reserved@4FC00000 { |
| 131 | compatible = "mediatek,wmcpu-reserved"; |
| 132 | no-map; |
| 133 | reg = <0 0x4FC00000 0 0x00100000>; |
| 134 | }; |
| 135 | |
| 136 | wocpu0_emi: wocpu0_emi@4FD00000 { |
| 137 | compatible = "mediatek,wocpu0_emi"; |
| 138 | no-map; |
| 139 | reg = <0 0x4FD00000 0 0x40000>; |
| 140 | shared = <0>; |
| 141 | }; |
| 142 | |
| 143 | wocpu1_emi: wocpu1_emi@4FD80000 { |
| 144 | compatible = "mediatek,wocpu1_emi"; |
| 145 | no-map; |
| 146 | reg = <0 0x4FD40000 0 0x40000>; |
| 147 | shared = <0>; |
| 148 | }; |
| 149 | |
| 150 | wocpu_data: wocpu_data@4FE00000 { |
| 151 | compatible = "mediatek,wocpu_data"; |
| 152 | no-map; |
| 153 | reg = <0 0x4FD80000 0 0x200000>; |
| 154 | shared = <1>; |
| 155 | }; |
| 156 | }; |
| 157 | |
| 158 | psci { |
| 159 | compatible = "arm,psci-0.2"; |
| 160 | method = "smc"; |
| 161 | }; |
| 162 | |
developer | 2df324b | 2021-06-24 10:21:45 +0800 | [diff] [blame^] | 163 | clk40m: oscillator@0 { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 164 | compatible = "fixed-clock"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 165 | #clock-cells = <0>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 166 | clock-frequency = <40000000>; |
developer | 2df324b | 2021-06-24 10:21:45 +0800 | [diff] [blame^] | 167 | clock-output-names = "clkxtal"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 168 | }; |
| 169 | |
developer | 2df324b | 2021-06-24 10:21:45 +0800 | [diff] [blame^] | 170 | system_clk: dummy_system_clk { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 171 | compatible = "fixed-clock"; |
| 172 | clock-frequency = <40000000>; |
| 173 | #clock-cells = <0>; |
| 174 | }; |
| 175 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 176 | timer { |
| 177 | compatible = "arm,armv8-timer"; |
| 178 | interrupt-parent = <&gic>; |
developer | f39022a | 2021-05-06 13:31:52 +0800 | [diff] [blame] | 179 | clock-frequency = <13000000>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 180 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| 181 | <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| 182 | <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| 183 | <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
developer | 2df324b | 2021-06-24 10:21:45 +0800 | [diff] [blame^] | 184 | }; |
| 185 | |
| 186 | infracfg_ao: infracfg_ao@10001000 { |
| 187 | compatible = "mediatek,mt7986-infracfg_ao", "syscon"; |
| 188 | reg = <0 0x10001000 0 0x68>; |
| 189 | #clock-cells = <1>; |
| 190 | }; |
| 191 | |
| 192 | infracfg: infracfg@10001040 { |
| 193 | compatible = "mediatek,mt7986-infracfg", "syscon"; |
| 194 | reg = <0 0x1000106c 0 0x1000>; |
| 195 | #clock-cells = <1>; |
| 196 | }; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 197 | |
developer | 2df324b | 2021-06-24 10:21:45 +0800 | [diff] [blame^] | 198 | topckgen: topckgen@1001B000 { |
| 199 | compatible = "mediatek,mt7986-topckgen", "syscon"; |
| 200 | reg = <0 0x1001B000 0 0x1000>; |
| 201 | #clock-cells = <1>; |
| 202 | }; |
| 203 | |
| 204 | apmixedsys: apmixedsys@1001E000 { |
| 205 | compatible = "mediatek,mt7986-apmixedsys", "syscon"; |
| 206 | reg = <0 0x1001E000 0 0x1000>; |
| 207 | #clock-cells = <1>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 208 | }; |
| 209 | |
| 210 | watchdog: watchdog@1001c000 { |
| 211 | compatible = "mediatek,mt7622-wdt", |
| 212 | "mediatek,mt6589-wdt"; |
| 213 | reg = <0 0x1001c000 0 0x1000>; |
| 214 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
| 215 | #reset-cells = <1>; |
| 216 | }; |
| 217 | |
| 218 | gic: interrupt-controller@c000000 { |
| 219 | compatible = "arm,gic-v3"; |
| 220 | #interrupt-cells = <3>; |
| 221 | interrupt-parent = <&gic>; |
| 222 | interrupt-controller; |
| 223 | reg = <0 0x0c000000 0 0x40000>, /* GICD */ |
| 224 | <0 0x0c080000 0 0x200000>; /* GICR */ |
| 225 | |
| 226 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| 227 | }; |
| 228 | |
developer | 2df324b | 2021-06-24 10:21:45 +0800 | [diff] [blame^] | 229 | pwm: pwm@10048000 { |
| 230 | compatible = "mediatek,mt7986-pwm"; |
| 231 | reg = <0 0x10048000 0 0x1000>; |
| 232 | #clock-cells = <1>; |
| 233 | #pwm-cells = <2>; |
| 234 | interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; |
| 235 | clocks = <&infracfg CK_INFRA_PWM>, |
| 236 | <&infracfg_ao CK_INFRA_PWM_BSEL>, |
| 237 | <&infracfg_ao CK_INFRA_PWM1_CK>, |
| 238 | <&infracfg_ao CK_INFRA_PWM2_CK>; |
| 239 | assigned-clocks = <&topckgen CK_TOP_PWM_SEL>, |
| 240 | <&infracfg_ao CK_INFRA_PWM_BSEL>, |
| 241 | <&infracfg_ao CK_INFRA_PWM1_SEL>, |
| 242 | <&infracfg_ao CK_INFRA_PWM2_SEL>; |
| 243 | assigned-clock-parents = <&topckgen CK_TOP_CB_M_D4>, |
| 244 | <&infracfg CK_INFRA_PWM>, |
| 245 | <&infracfg CK_INFRA_PWM>, |
| 246 | <&infracfg CK_INFRA_PWM>; |
| 247 | clock-names = "top", "main", "pwm1", "pwm2"; |
| 248 | status = "disabled"; |
| 249 | }; |
| 250 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 251 | uart0: serial@11002000 { |
| 252 | compatible = "mediatek,mt7986-uart", |
| 253 | "mediatek,mt6577-uart"; |
| 254 | reg = <0 0x11002000 0 0x400>; |
| 255 | interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; |
developer | 2df324b | 2021-06-24 10:21:45 +0800 | [diff] [blame^] | 256 | clocks = <&infracfg_ao CK_INFRA_UART0_CK>; |
| 257 | assigned-clocks = <&topckgen CK_TOP_UART_SEL>, |
| 258 | <&infracfg_ao CK_INFRA_UART0_SEL>; |
| 259 | assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, |
| 260 | <&infracfg CK_INFRA_UART>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 261 | status = "disabled"; |
| 262 | }; |
| 263 | |
| 264 | uart1: serial@11003000 { |
| 265 | compatible = "mediatek,mt7986-uart", |
| 266 | "mediatek,mt6577-uart"; |
| 267 | reg = <0 0x11003000 0 0x400>; |
| 268 | interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; |
developer | 2df324b | 2021-06-24 10:21:45 +0800 | [diff] [blame^] | 269 | clocks = <&infracfg_ao CK_INFRA_UART1_CK>; |
| 270 | assigned-clocks = <&infracfg_ao CK_INFRA_UART1_SEL>; |
| 271 | assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 272 | status = "disabled"; |
| 273 | }; |
| 274 | |
| 275 | uart2: serial@11004000 { |
| 276 | compatible = "mediatek,mt7986-uart", |
| 277 | "mediatek,mt6577-uart"; |
| 278 | reg = <0 0x11004000 0 0x400>; |
| 279 | interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
developer | 2df324b | 2021-06-24 10:21:45 +0800 | [diff] [blame^] | 280 | clocks = <&infracfg_ao CK_INFRA_UART2_CK>; |
| 281 | assigned-clocks = <&infracfg_ao CK_INFRA_UART2_SEL>; |
| 282 | assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 283 | status = "disabled"; |
| 284 | }; |
| 285 | |
developer | 2df324b | 2021-06-24 10:21:45 +0800 | [diff] [blame^] | 286 | i2c0: i2c@11008000 { |
| 287 | compatible = "mediatek,mt7986-i2c"; |
| 288 | reg = <0 0x11008000 0 0x90>, |
| 289 | <0 0x10217080 0 0x80>; |
| 290 | interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; |
| 291 | clock-div = <16>; |
| 292 | clocks = <&infracfg_ao CK_INFRA_I2CO_CK>, |
| 293 | <&infracfg_ao CK_INFRA_AP_DMA_CK>; |
| 294 | clock-names = "main", "dma"; |
| 295 | #address-cells = <1>; |
| 296 | #size-cells = <0>; |
| 297 | status = "disabled"; |
| 298 | }; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 299 | |
developer | 3e91642 | 2021-05-27 16:40:29 +0800 | [diff] [blame] | 300 | crypto: crypto@10320000 { |
| 301 | compatible = "inside-secure,safexcel-eip97"; |
| 302 | reg = <0 0x10320000 0 0x40000>; |
| 303 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| 304 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| 305 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| 306 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; |
| 307 | interrupt-names = "ring0", "ring1", "ring2", "ring3"; |
| 308 | }; |
| 309 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 310 | pio: pinctrl@1001f000 { |
| 311 | compatible = "mediatek,mt7986-pinctrl"; |
| 312 | reg = <0 0x1001f000 0 0x1000>, |
| 313 | <0 0x11c30000 0 0x1000>, |
| 314 | <0 0x11c40000 0 0x1000>, |
| 315 | <0 0x11e20000 0 0x1000>, |
| 316 | <0 0x11e30000 0 0x1000>, |
| 317 | <0 0x11f00000 0 0x1000>, |
| 318 | <0 0x11f10000 0 0x1000>, |
| 319 | <0 0x1000b000 0 0x1000>; |
| 320 | reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rb_base", |
| 321 | "iocfg_lt_base", "iocfg_lb_base", "iocfg_tr_base", |
| 322 | "iocfg_tl_base", "eint"; |
| 323 | gpio-controller; |
| 324 | #gpio-cells = <2>; |
| 325 | gpio-ranges = <&pio 0 0 100>; |
| 326 | interrupt-controller; |
developer | a7f8fa4 | 2021-06-07 16:46:34 +0800 | [diff] [blame] | 327 | interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 328 | interrupt-parent = <&gic>; |
| 329 | #interrupt-cells = <2>; |
| 330 | }; |
| 331 | |
| 332 | ethsys: syscon@15000000 { |
| 333 | #address-cells = <1>; |
| 334 | #size-cells = <1>; |
developer | 2df324b | 2021-06-24 10:21:45 +0800 | [diff] [blame^] | 335 | compatible = "mediatek,mt7986-ethsys_ck", |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 336 | "syscon"; |
| 337 | reg = <0 0x15000000 0 0x1000>; |
| 338 | #clock-cells = <1>; |
| 339 | #reset-cells = <1>; |
| 340 | |
| 341 | ethsysrst: reset-controller { |
| 342 | compatible = "ti,syscon-reset"; |
| 343 | #reset-cells = <1>; |
| 344 | ti,reset-bits = <0x34 4 0x34 4 0x34 4 (ASSERT_SET | DEASSERT_CLEAR | STATUS_SET)>; |
| 345 | }; |
| 346 | }; |
| 347 | |
| 348 | eth: ethernet@15100000 { |
| 349 | compatible = "mediatek,mt7986-eth"; |
| 350 | reg = <0 0x15100000 0 0x80000>; |
| 351 | interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, |
| 352 | <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, |
| 353 | <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, |
| 354 | <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; |
developer | 2df324b | 2021-06-24 10:21:45 +0800 | [diff] [blame^] | 355 | clocks = <ðsys CK_ETH_FE_EN>, |
| 356 | <ðsys CK_ETH_GP2_EN>, |
| 357 | <ðsys CK_ETH_GP1_EN>, |
| 358 | <ðsys CK_ETH_WOCPU1_EN>, |
| 359 | <ðsys CK_ETH_WOCPU0_EN>, |
| 360 | <ðsys CK_SGM0_TX_EN>, |
| 361 | <ðsys CK_SGM0_RX_EN>, |
| 362 | <ðsys CK_SGM0_CK0_EN>, |
| 363 | <ðsys CK_SGM0_CDR_CK0_EN>, |
| 364 | <ðsys CK_SGM1_TX_EN>, |
| 365 | <ðsys CK_SGM1_RX_EN>, |
| 366 | <ðsys CK_SGM1_CK1_EN>, |
| 367 | <ðsys CK_SGM1_CDR_CK1_EN>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 368 | clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0", |
| 369 | "sgmii_tx250m", "sgmii_rx250m", |
| 370 | "sgmii_cdr_ref", "sgmii_cdr_fb", |
| 371 | "sgmii2_tx250m", "sgmii2_rx250m", |
| 372 | "sgmii2_cdr_ref", "sgmii2_cdr_fb"; |
developer | 2df324b | 2021-06-24 10:21:45 +0800 | [diff] [blame^] | 373 | assigned-clocks = <&topckgen CK_TOP_NETSYS_2X_SEL>, |
| 374 | <&topckgen CK_TOP_SGM_325M_SEL>; |
| 375 | assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_800M>, |
| 376 | <&topckgen CK_TOP_CB_SGM_325M>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 377 | mediatek,ethsys = <ðsys>; |
| 378 | mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; |
| 379 | #reset-cells = <1>; |
| 380 | #address-cells = <1>; |
| 381 | #size-cells = <0>; |
| 382 | status = "disabled"; |
| 383 | }; |
| 384 | |
| 385 | hnat: hnat@15000000 { |
| 386 | compatible = "mediatek,mtk-hnat_v4"; |
| 387 | reg = <0 0x15100000 0 0x80000>; |
| 388 | resets = <ðsys 0>; |
| 389 | reset-names = "mtketh"; |
| 390 | status = "disabled"; |
| 391 | }; |
| 392 | |
| 393 | sgmiisys0: syscon@10060000 { |
developer | 2df324b | 2021-06-24 10:21:45 +0800 | [diff] [blame^] | 394 | compatible = "mediatek,mt7986-sgmiisys", |
| 395 | "mediatek,mt7986-sgmiisys_0", |
| 396 | "syscon"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 397 | reg = <0 0x10060000 0 0x1000>; |
| 398 | #clock-cells = <1>; |
| 399 | }; |
| 400 | |
| 401 | sgmiisys1: syscon@10070000 { |
developer | 2df324b | 2021-06-24 10:21:45 +0800 | [diff] [blame^] | 402 | compatible = "mediatek,mt7986-sgmiisys", |
| 403 | "mediatek,mt7986-sgmiisys_1", |
| 404 | "syscon"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 405 | reg = <0 0x10070000 0 0x1000>; |
| 406 | #clock-cells = <1>; |
| 407 | }; |
| 408 | |
| 409 | snand: snfi@11005000 { |
| 410 | compatible = "mediatek,mt7986-snand"; |
| 411 | reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>; |
| 412 | reg-names = "nfi", "ecc"; |
| 413 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
developer | 2df324b | 2021-06-24 10:21:45 +0800 | [diff] [blame^] | 414 | clocks = <&topckgen CK_TOP_SPINFI_SEL>, |
| 415 | <&infracfg_ao CK_INFRA_SPINFI1_CK>, |
| 416 | <&topckgen CK_TOP_NFI1X_SEL>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 417 | clock-names = "nfi_clk", "pad_clk", "ecc_clk"; |
developer | 2df324b | 2021-06-24 10:21:45 +0800 | [diff] [blame^] | 418 | assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>, |
| 419 | <&topckgen CK_TOP_NFI1X_SEL>; |
| 420 | assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M_D2>, |
| 421 | <&topckgen CK_TOP_CB_CKSQ_40M>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 422 | #address-cells = <1>; |
| 423 | #size-cells = <0>; |
| 424 | status = "disabled"; |
| 425 | }; |
| 426 | |
| 427 | wbsys: wbsys@18000000 { |
| 428 | compatible = "mediatek,wbsys"; |
| 429 | reg = <0 0x18000000 0 0x1000000>; |
| 430 | interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, |
| 431 | <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, |
| 432 | <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, |
| 433 | <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; |
| 434 | chip_id = <0x7986>; |
| 435 | }; |
| 436 | |
| 437 | wed_pcie: wed_pcie@10003000 { |
| 438 | compatible = "mediatek,wed_pcie"; |
| 439 | reg = <0 0x10003000 0 0x10>; |
| 440 | }; |
| 441 | |
| 442 | spi0: spi@1100a000 { |
| 443 | compatible = "mediatek,ipm-spi"; |
| 444 | reg = <0 0x1100a000 0 0x100>; |
| 445 | interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
developer | 2df324b | 2021-06-24 10:21:45 +0800 | [diff] [blame^] | 446 | clocks = <&topckgen CK_TOP_CB_M_D2>, |
| 447 | <&infracfg_ao CK_INFRA_SPI0_CK>, |
| 448 | <&topckgen CK_TOP_SPI_SEL>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 449 | clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| 450 | status = "disabled"; |
| 451 | }; |
| 452 | |
| 453 | spi1: spi@1100b000 { |
| 454 | compatible = "mediatek,ipm-spi"; |
| 455 | reg = <0 0x1100b000 0 0x100>; |
| 456 | interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
developer | 2df324b | 2021-06-24 10:21:45 +0800 | [diff] [blame^] | 457 | clocks = <&topckgen CK_TOP_CB_M_D2>, |
| 458 | <&infracfg_ao CK_INFRA_SPI1_CK>, |
| 459 | <&topckgen CK_TOP_SPIM_MST_SEL>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 460 | clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| 461 | status = "disabled"; |
| 462 | }; |
| 463 | |
developer | ee2df73 | 2021-05-21 15:19:42 +0800 | [diff] [blame] | 464 | auxadc: adc@1100d000 { |
| 465 | compatible = "mediatek,mt7986-auxadc", |
| 466 | "mediatek,mt7622-auxadc"; |
| 467 | reg = <0 0x1100d000 0 0x1000>; |
developer | 2df324b | 2021-06-24 10:21:45 +0800 | [diff] [blame^] | 468 | clocks = <&infracfg_ao CK_INFRA_ADC_26M_CK>; |
developer | ee2df73 | 2021-05-21 15:19:42 +0800 | [diff] [blame] | 469 | clock-names = "main"; |
| 470 | #io-channel-cells = <1>; |
developer | 2df324b | 2021-06-24 10:21:45 +0800 | [diff] [blame^] | 471 | status = "disabled"; |
developer | ee2df73 | 2021-05-21 15:19:42 +0800 | [diff] [blame] | 472 | }; |
| 473 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 474 | consys: consys@10000000 { |
| 475 | compatible = "mediatek,mt7986-consys"; |
| 476 | reg = <0 0x10000000 0 0x8600000>; |
| 477 | memory-region = <&wmcpu_emi>; |
| 478 | }; |
| 479 | |
| 480 | xhci: xhci@11200000 { |
| 481 | compatible = "mediatek,mt7986-xhci", |
| 482 | "mediatek,mtk-xhci"; |
| 483 | reg = <0 0x11200000 0 0x2e00>, |
| 484 | <0 0x11203e00 0 0x0100>; |
| 485 | reg-names = "mac", "ippc"; |
| 486 | interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; |
| 487 | phys = <&u2port0 PHY_TYPE_USB2>, |
| 488 | <&u3port0 PHY_TYPE_USB3>, |
| 489 | <&u2port1 PHY_TYPE_USB2>; |
| 490 | clocks = <&system_clk>, |
| 491 | <&system_clk>, |
| 492 | <&system_clk>, |
| 493 | <&system_clk>, |
| 494 | <&system_clk>; |
| 495 | clock-names = "sys_ck", |
| 496 | "xhci_ck", |
| 497 | "ref_ck", |
| 498 | "mcu_ck", |
| 499 | "dma_ck"; |
| 500 | #address-cells = <2>; |
| 501 | #size-cells = <2>; |
| 502 | status = "okay"; |
| 503 | }; |
| 504 | |
| 505 | usbtphy: usb-phy@11e10000 { |
| 506 | compatible = "mediatek,mt7986", |
| 507 | "mediatek,generic-tphy-v2"; |
| 508 | #address-cells = <2>; |
| 509 | #size-cells = <2>; |
| 510 | ranges; |
| 511 | status = "okay"; |
| 512 | |
| 513 | u2port0: usb-phy@11e10000 { |
| 514 | reg = <0 0x11e10000 0 0x700>; |
| 515 | clocks = <&system_clk>; |
| 516 | clock-names = "ref"; |
| 517 | #phy-cells = <1>; |
| 518 | status = "okay"; |
| 519 | }; |
| 520 | |
| 521 | u3port0: usb-phy@11e10700 { |
| 522 | reg = <0 0x11e10700 0 0x900>; |
| 523 | clocks = <&system_clk>; |
| 524 | clock-names = "ref"; |
| 525 | #phy-cells = <1>; |
| 526 | status = "okay"; |
| 527 | }; |
| 528 | |
| 529 | u2port1: usb-phy@11e11000 { |
| 530 | reg = <0 0x11e11000 0 0x700>; |
| 531 | clocks = <&system_clk>; |
| 532 | clock-names = "ref"; |
| 533 | #phy-cells = <1>; |
developer | 2df324b | 2021-06-24 10:21:45 +0800 | [diff] [blame^] | 534 | status = "disabled"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 535 | }; |
| 536 | }; |
developer | 2df324b | 2021-06-24 10:21:45 +0800 | [diff] [blame^] | 537 | |
| 538 | clkitg: clkitg { |
| 539 | compatible = "simple-bus"; |
| 540 | }; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 541 | }; |
developer | 2df324b | 2021-06-24 10:21:45 +0800 | [diff] [blame^] | 542 | |
| 543 | #include "mt7986-clkitg.dtsi" |