developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (c) 2018 MediaTek Inc. |
| 4 | * Author: Zhanguo Ju <zhanguo.ju@mediatek.com> |
| 5 | */ |
| 6 | |
| 7 | #include <linux/kernel.h> |
| 8 | #include <linux/delay.h> |
| 9 | #include <linux/hrtimer.h> |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 10 | #include <linux/of_platform.h> |
| 11 | #include <linux/mfd/syscon.h> |
| 12 | #include <linux/regmap.h> |
| 13 | #include <linux/of_address.h> |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 14 | |
| 15 | #include "mt753x.h" |
| 16 | #include "mt753x_regs.h" |
| 17 | |
| 18 | /* MT7531 registers */ |
| 19 | #define SGMII_REG_BASE 0x5000 |
| 20 | #define SGMII_REG_PORT_BASE 0x1000 |
| 21 | #define SGMII_REG(p, r) (SGMII_REG_BASE + \ |
| 22 | (p) * SGMII_REG_PORT_BASE + (r)) |
| 23 | #define PCS_CONTROL_1(p) SGMII_REG(p, 0x00) |
| 24 | #define SGMII_MODE(p) SGMII_REG(p, 0x20) |
| 25 | #define QPHY_PWR_STATE_CTRL(p) SGMII_REG(p, 0xe8) |
| 26 | #define ANA_CKBG(p) SGMII_REG(p, 0x100) |
| 27 | #define ANA_DA_FORCE_MODE1(p) SGMII_REG(p, 0x110) |
| 28 | #define PHYA_CTRL_SIGNAL3(p) SGMII_REG(p, 0x128) |
| 29 | #define PHYA_ANA_SYSPLL(p) SGMII_REG(p, 0x158) |
| 30 | |
| 31 | /* Fields of PCS_CONTROL_1 */ |
| 32 | #define SGMII_LINK_STATUS BIT(18) |
| 33 | #define SGMII_AN_ENABLE BIT(12) |
| 34 | #define SGMII_AN_RESTART BIT(9) |
| 35 | |
| 36 | /* Fields of SGMII_MODE */ |
| 37 | #define SGMII_REMOTE_FAULT_DIS BIT(8) |
| 38 | #define SGMII_IF_MODE_FORCE_DUPLEX BIT(4) |
| 39 | #define SGMII_IF_MODE_FORCE_SPEED_S 0x2 |
| 40 | #define SGMII_IF_MODE_FORCE_SPEED_M 0x0c |
| 41 | #define SGMII_IF_MODE_ADVERT_AN BIT(1) |
| 42 | |
| 43 | /* Values of SGMII_IF_MODE_FORCE_SPEED */ |
| 44 | #define SGMII_IF_MODE_FORCE_SPEED_10 0 |
| 45 | #define SGMII_IF_MODE_FORCE_SPEED_100 1 |
| 46 | #define SGMII_IF_MODE_FORCE_SPEED_1000 2 |
| 47 | |
| 48 | /* Fields of QPHY_PWR_STATE_CTRL */ |
| 49 | #define PHYA_PWD BIT(4) |
| 50 | |
| 51 | /* Fields of ANA_CKBG */ |
| 52 | #define SSUSB_PLL_SSC_EN BIT(21) |
| 53 | |
| 54 | /* Fields of ANA_DA_FORCE_MODE1 */ |
| 55 | #define FORCE_PLL_SSC_EN BIT(30) |
| 56 | |
| 57 | /* Fields of PHYA_CTRL_SIGNAL3 */ |
| 58 | #define RG_TPHY_SPEED_S 2 |
| 59 | #define RG_TPHY_SPEED_M 0x0c |
| 60 | |
| 61 | /* Values of RG_TPHY_SPEED */ |
| 62 | #define RG_TPHY_SPEED_1000 0 |
| 63 | #define RG_TPHY_SPEED_2500 1 |
| 64 | |
| 65 | /* Fields of PHYA_ANA_SYSPLL */ |
| 66 | #define RG_VUSB10_ON BIT(29) |
| 67 | |
| 68 | /* Unique fields of (M)HWSTRAP for MT7531 */ |
| 69 | #define XTAL_FSEL_S 7 |
| 70 | #define XTAL_FSEL_M BIT(7) |
| 71 | #define PHY_EN BIT(6) |
| 72 | #define CHG_STRAP BIT(8) |
| 73 | |
| 74 | /* Efuse Register Define */ |
| 75 | #define GBE_EFUSE 0x7bc8 |
| 76 | #define GBE_SEL_EFUSE_EN BIT(0) |
| 77 | |
| 78 | /* PHY ENABLE Register bitmap define */ |
| 79 | #define PHY_DEV1F 0x1f |
| 80 | #define PHY_DEV1F_REG_44 0x44 |
| 81 | #define PHY_DEV1F_REG_104 0x104 |
| 82 | #define PHY_DEV1F_REG_10A 0x10a |
| 83 | #define PHY_DEV1F_REG_10B 0x10b |
| 84 | #define PHY_DEV1F_REG_10C 0x10c |
| 85 | #define PHY_DEV1F_REG_10D 0x10d |
| 86 | #define PHY_DEV1F_REG_268 0x268 |
| 87 | #define PHY_DEV1F_REG_269 0x269 |
| 88 | #define PHY_DEV1F_REG_26A 0x26A |
| 89 | #define PHY_DEV1F_REG_403 0x403 |
| 90 | |
| 91 | /* Fields of PHY_DEV1F_REG_403 */ |
| 92 | #define GBE_EFUSE_SETTING BIT(3) |
| 93 | #define PHY_EN_BYPASS_MODE BIT(4) |
| 94 | #define POWER_ON_OFF BIT(5) |
| 95 | #define PHY_PLL_M GENMASK(9, 8) |
| 96 | #define PHY_PLL_SEL(x) (((x) << 8) & GENMASK(9, 8)) |
| 97 | |
| 98 | /* PHY EEE Register bitmap of define */ |
| 99 | #define PHY_DEV07 0x07 |
| 100 | #define PHY_DEV07_REG_03C 0x3c |
| 101 | |
| 102 | /* PHY Extend Register 0x14 bitmap of define */ |
| 103 | #define PHY_EXT_REG_14 0x14 |
| 104 | |
| 105 | /* Fields of PHY_EXT_REG_14 */ |
| 106 | #define PHY_EN_DOWN_SHFIT BIT(4) |
| 107 | |
| 108 | /* PHY Extend Register 0x17 bitmap of define */ |
| 109 | #define PHY_EXT_REG_17 0x17 |
| 110 | |
| 111 | /* Fields of PHY_EXT_REG_17 */ |
| 112 | #define PHY_LINKDOWN_POWER_SAVING_EN BIT(4) |
| 113 | |
| 114 | /* PHY PMA Register 0x17 bitmap of define */ |
| 115 | #define SLV_DSP_READY_TIME_S 15 |
| 116 | #define SLV_DSP_READY_TIME_M (0xff << SLV_DSP_READY_TIME_S) |
| 117 | |
| 118 | /* PHY PMA Register 0x18 bitmap of define */ |
| 119 | #define ENABLE_RANDOM_UPDATE_TRIGGER BIT(8) |
| 120 | |
| 121 | /* PHY DEV 0x1e Register bitmap of define */ |
| 122 | #define PHY_DEV1E 0x1e |
| 123 | #define PHY_TX_MLT3_BASE 0x0 |
| 124 | #define PHY_DEV1E_REG_13 0x13 |
| 125 | #define PHY_DEV1E_REG_14 0x14 |
| 126 | #define PHY_DEV1E_REG_41 0x41 |
| 127 | #define PHY_DEV1E_REG_A6 0xa6 |
| 128 | #define PHY_DEV1E_REG_0C6 0x0c6 |
| 129 | #define PHY_DEV1E_REG_0FE 0x0fe |
| 130 | #define PHY_DEV1E_REG_123 0x123 |
| 131 | #define PHY_DEV1E_REG_141 0x141 |
| 132 | #define PHY_DEV1E_REG_189 0x189 |
| 133 | #define PHY_DEV1E_REG_234 0x234 |
| 134 | |
| 135 | /* Fields of PHY_DEV1E_REG_0C6 */ |
| 136 | #define PHY_POWER_SAVING_S 8 |
| 137 | #define PHY_POWER_SAVING_M 0x300 |
| 138 | #define PHY_POWER_SAVING_TX 0x0 |
| 139 | |
| 140 | /* Fields of PHY_DEV1E_REG_189 */ |
| 141 | #define DESCRAMBLER_CLEAR_EN 0x1 |
| 142 | |
| 143 | /* Fields of PHY_DEV1E_REG_234 */ |
| 144 | #define TR_OPEN_LOOP_EN BIT(0) |
| 145 | |
| 146 | /* Port debug count register */ |
| 147 | #define DBG_CNT_BASE 0x3018 |
| 148 | #define DBG_CNT_PORT_BASE 0x100 |
| 149 | #define DBG_CNT(p) (DBG_CNT_BASE + \ |
| 150 | (p) * DBG_CNT_PORT_BASE) |
| 151 | #define DIS_CLR BIT(31) |
| 152 | |
| 153 | /* Values of XTAL_FSEL_S */ |
| 154 | #define XTAL_40MHZ 0 |
| 155 | #define XTAL_25MHZ 1 |
| 156 | |
| 157 | #define PLLGP_EN 0x7820 |
| 158 | #define EN_COREPLL BIT(2) |
| 159 | #define SW_CLKSW BIT(1) |
| 160 | #define SW_PLLGP BIT(0) |
| 161 | |
| 162 | #define PLLGP_CR0 0x78a8 |
| 163 | #define RG_COREPLL_EN BIT(22) |
| 164 | #define RG_COREPLL_POSDIV_S 23 |
| 165 | #define RG_COREPLL_POSDIV_M 0x3800000 |
| 166 | #define RG_COREPLL_SDM_PCW_S 1 |
| 167 | #define RG_COREPLL_SDM_PCW_M 0x3ffffe |
| 168 | #define RG_COREPLL_SDM_PCW_CHG BIT(0) |
| 169 | |
| 170 | /* TOP Signals Status Register */ |
| 171 | #define TOP_SIG_SR 0x780c |
| 172 | #define PAD_MCM_SMI_EN BIT(0) |
| 173 | #define PAD_DUAL_SGMII_EN BIT(1) |
| 174 | |
| 175 | /* RGMII and SGMII PLL clock */ |
| 176 | #define ANA_PLLGP_CR2 0x78b0 |
| 177 | #define ANA_PLLGP_CR5 0x78bc |
| 178 | |
| 179 | /* GPIO mode define */ |
| 180 | #define GPIO_MODE_REGS(x) (0x7c0c + (((x) / 8) * 4)) |
| 181 | #define GPIO_MODE_S 4 |
| 182 | |
| 183 | /* GPIO GROUP IOLB SMT0 Control */ |
| 184 | #define SMT0_IOLB 0x7f04 |
| 185 | #define SMT_IOLB_5_SMI_MDC_EN BIT(5) |
| 186 | |
| 187 | /* Unique fields of PMCR for MT7531 */ |
| 188 | #define FORCE_MODE_EEE1G BIT(25) |
| 189 | #define FORCE_MODE_EEE100 BIT(26) |
| 190 | #define FORCE_MODE_TX_FC BIT(27) |
| 191 | #define FORCE_MODE_RX_FC BIT(28) |
| 192 | #define FORCE_MODE_DPX BIT(29) |
| 193 | #define FORCE_MODE_SPD BIT(30) |
| 194 | #define FORCE_MODE_LNK BIT(31) |
| 195 | #define FORCE_MODE BIT(15) |
| 196 | |
| 197 | #define CHIP_REV 0x781C |
| 198 | #define CHIP_NAME_S 16 |
| 199 | #define CHIP_NAME_M 0xffff0000 |
| 200 | #define CHIP_REV_S 0 |
| 201 | #define CHIP_REV_M 0x0f |
| 202 | #define CHIP_REV_E1 0x0 |
| 203 | |
| 204 | #define CLKGEN_CTRL 0x7500 |
| 205 | #define CLK_SKEW_OUT_S 8 |
| 206 | #define CLK_SKEW_OUT_M 0x300 |
| 207 | #define CLK_SKEW_IN_S 6 |
| 208 | #define CLK_SKEW_IN_M 0xc0 |
| 209 | #define RXCLK_NO_DELAY BIT(5) |
| 210 | #define TXCLK_NO_REVERSE BIT(4) |
| 211 | #define GP_MODE_S 1 |
| 212 | #define GP_MODE_M 0x06 |
| 213 | #define GP_CLK_EN BIT(0) |
| 214 | |
| 215 | #define CPGC_CTRL 0xB0 |
| 216 | #define COL_EN BIT(0) |
| 217 | #define COL_CLK_EN BIT(1) |
| 218 | #define COL_RST_N BIT(2) |
| 219 | #define COL_BUSY BIT(3) |
| 220 | |
| 221 | /* Values of GP_MODE */ |
| 222 | #define GP_MODE_RGMII 0 |
| 223 | #define GP_MODE_MII 1 |
| 224 | #define GP_MODE_REV_MII 2 |
| 225 | |
| 226 | /* Values of CLK_SKEW_IN */ |
| 227 | #define CLK_SKEW_IN_NO_CHANGE 0 |
| 228 | #define CLK_SKEW_IN_DELAY_100PPS 1 |
| 229 | #define CLK_SKEW_IN_DELAY_200PPS 2 |
| 230 | #define CLK_SKEW_IN_REVERSE 3 |
| 231 | |
| 232 | /* Values of CLK_SKEW_OUT */ |
| 233 | #define CLK_SKEW_OUT_NO_CHANGE 0 |
| 234 | #define CLK_SKEW_OUT_DELAY_100PPS 1 |
| 235 | #define CLK_SKEW_OUT_DELAY_200PPS 2 |
| 236 | #define CLK_SKEW_OUT_REVERSE 3 |
| 237 | |
| 238 | /* Proprietory Control Register of Internal Phy device 0x1e */ |
| 239 | #define RXADC_CONTROL_3 0xc2 |
| 240 | #define RXADC_LDO_CONTROL_2 0xd3 |
| 241 | |
| 242 | /* Proprietory Control Register of Internal Phy device 0x1f */ |
| 243 | #define TXVLD_DA_271 0x271 |
| 244 | #define TXVLD_DA_272 0x272 |
| 245 | #define TXVLD_DA_273 0x273 |
| 246 | |
| 247 | /* gpio pinmux pins and functions define */ |
| 248 | static int gpio_int_pins[] = {0}; |
| 249 | static int gpio_int_funcs[] = {1}; |
| 250 | static int gpio_mdc_pins[] = {11, 20}; |
| 251 | static int gpio_mdc_funcs[] = {2, 2}; |
| 252 | static int gpio_mdio_pins[] = {12, 21}; |
| 253 | static int gpio_mdio_funcs[] = {2, 2}; |
| 254 | |
| 255 | static int mt7531_set_port_sgmii_force_mode(struct gsw_mt753x *gsw, u32 port, |
| 256 | struct mt753x_port_cfg *port_cfg) |
| 257 | { |
| 258 | u32 speed, port_base, val; |
| 259 | ktime_t timeout; |
| 260 | u32 timeout_us; |
| 261 | |
| 262 | if (port < 5 || port >= MT753X_NUM_PORTS) { |
| 263 | dev_info(gsw->dev, "port %d is not a SGMII port\n", port); |
| 264 | return -EINVAL; |
| 265 | } |
| 266 | |
| 267 | port_base = port - 5; |
| 268 | |
| 269 | switch (port_cfg->speed) { |
| 270 | case MAC_SPD_1000: |
| 271 | speed = RG_TPHY_SPEED_1000; |
| 272 | break; |
| 273 | case MAC_SPD_2500: |
| 274 | speed = RG_TPHY_SPEED_2500; |
| 275 | break; |
| 276 | default: |
| 277 | dev_info(gsw->dev, "invalid SGMII speed idx %d for port %d\n", |
| 278 | port_cfg->speed, port); |
| 279 | |
| 280 | speed = RG_TPHY_SPEED_1000; |
| 281 | } |
| 282 | |
| 283 | /* Step 1: Speed select register setting */ |
| 284 | val = mt753x_reg_read(gsw, PHYA_CTRL_SIGNAL3(port_base)); |
| 285 | val &= ~RG_TPHY_SPEED_M; |
| 286 | val |= speed << RG_TPHY_SPEED_S; |
| 287 | mt753x_reg_write(gsw, PHYA_CTRL_SIGNAL3(port_base), val); |
| 288 | |
| 289 | /* Step 2 : Disable AN */ |
| 290 | val = mt753x_reg_read(gsw, PCS_CONTROL_1(port_base)); |
| 291 | val &= ~SGMII_AN_ENABLE; |
| 292 | mt753x_reg_write(gsw, PCS_CONTROL_1(port_base), val); |
| 293 | |
| 294 | /* Step 3: SGMII force mode setting */ |
| 295 | val = mt753x_reg_read(gsw, SGMII_MODE(port_base)); |
| 296 | val &= ~SGMII_IF_MODE_ADVERT_AN; |
| 297 | val &= ~SGMII_IF_MODE_FORCE_SPEED_M; |
| 298 | val |= SGMII_IF_MODE_FORCE_SPEED_1000 << SGMII_IF_MODE_FORCE_SPEED_S; |
| 299 | val |= SGMII_IF_MODE_FORCE_DUPLEX; |
| 300 | /* For sgmii force mode, 0 is full duplex and 1 is half duplex */ |
| 301 | if (port_cfg->duplex) |
| 302 | val &= ~SGMII_IF_MODE_FORCE_DUPLEX; |
| 303 | |
| 304 | mt753x_reg_write(gsw, SGMII_MODE(port_base), val); |
| 305 | |
| 306 | /* Step 4: XXX: Disable Link partner's AN and set force mode */ |
| 307 | |
| 308 | /* Step 5: XXX: Special setting for PHYA ==> reserved for flexible */ |
| 309 | |
| 310 | /* Step 6 : Release PHYA power down state */ |
| 311 | val = mt753x_reg_read(gsw, QPHY_PWR_STATE_CTRL(port_base)); |
| 312 | val &= ~PHYA_PWD; |
| 313 | mt753x_reg_write(gsw, QPHY_PWR_STATE_CTRL(port_base), val); |
| 314 | |
| 315 | /* Step 7 : Polling SGMII_LINK_STATUS */ |
| 316 | timeout_us = 2000000; |
| 317 | timeout = ktime_add_us(ktime_get(), timeout_us); |
| 318 | while (1) { |
| 319 | val = mt753x_reg_read(gsw, PCS_CONTROL_1(port_base)); |
| 320 | val &= SGMII_LINK_STATUS; |
| 321 | |
| 322 | if (val) |
| 323 | break; |
| 324 | |
| 325 | if (ktime_compare(ktime_get(), timeout) > 0) |
| 326 | return -ETIMEDOUT; |
| 327 | } |
| 328 | |
| 329 | return 0; |
| 330 | } |
| 331 | |
| 332 | static int mt7531_set_port_sgmii_an_mode(struct gsw_mt753x *gsw, u32 port, |
| 333 | struct mt753x_port_cfg *port_cfg) |
| 334 | { |
| 335 | u32 speed, port_base, val; |
| 336 | ktime_t timeout; |
| 337 | u32 timeout_us; |
| 338 | |
| 339 | if (port < 5 || port >= MT753X_NUM_PORTS) { |
| 340 | dev_info(gsw->dev, "port %d is not a SGMII port\n", port); |
| 341 | return -EINVAL; |
| 342 | } |
| 343 | |
| 344 | port_base = port - 5; |
| 345 | |
| 346 | switch (port_cfg->speed) { |
| 347 | case MAC_SPD_1000: |
| 348 | speed = RG_TPHY_SPEED_1000; |
| 349 | break; |
| 350 | case MAC_SPD_2500: |
| 351 | speed = RG_TPHY_SPEED_2500; |
| 352 | break; |
| 353 | default: |
| 354 | dev_info(gsw->dev, "invalid SGMII speed idx %d for port %d\n", |
| 355 | port_cfg->speed, port); |
| 356 | |
| 357 | speed = RG_TPHY_SPEED_1000; |
| 358 | } |
| 359 | |
| 360 | /* Step 1: Speed select register setting */ |
| 361 | val = mt753x_reg_read(gsw, PHYA_CTRL_SIGNAL3(port_base)); |
| 362 | val &= ~RG_TPHY_SPEED_M; |
| 363 | val |= speed << RG_TPHY_SPEED_S; |
| 364 | mt753x_reg_write(gsw, PHYA_CTRL_SIGNAL3(port_base), val); |
| 365 | |
| 366 | /* Step 2: Remote fault disable */ |
| 367 | val = mt753x_reg_read(gsw, SGMII_MODE(port)); |
| 368 | val |= SGMII_REMOTE_FAULT_DIS; |
| 369 | mt753x_reg_write(gsw, SGMII_MODE(port), val); |
| 370 | |
| 371 | /* Step 3: Setting Link partner's AN enable = 1 */ |
| 372 | |
| 373 | /* Step 4: Setting Link partner's device ability for speed/duplex */ |
| 374 | |
| 375 | /* Step 5: AN re-start */ |
| 376 | val = mt753x_reg_read(gsw, PCS_CONTROL_1(port)); |
| 377 | val |= SGMII_AN_RESTART; |
| 378 | mt753x_reg_write(gsw, PCS_CONTROL_1(port), val); |
| 379 | |
| 380 | /* Step 6: Special setting for PHYA ==> reserved for flexible */ |
| 381 | |
| 382 | /* Step 7 : Polling SGMII_LINK_STATUS */ |
| 383 | timeout_us = 2000000; |
| 384 | timeout = ktime_add_us(ktime_get(), timeout_us); |
| 385 | while (1) { |
| 386 | val = mt753x_reg_read(gsw, PCS_CONTROL_1(port_base)); |
| 387 | val &= SGMII_LINK_STATUS; |
| 388 | |
| 389 | if (val) |
| 390 | break; |
| 391 | |
| 392 | if (ktime_compare(ktime_get(), timeout) > 0) |
| 393 | return -ETIMEDOUT; |
| 394 | } |
| 395 | |
| 396 | return 0; |
| 397 | } |
| 398 | |
| 399 | static void mt7531_sgmii_ssc(struct gsw_mt753x *gsw, u32 port, int enable) |
| 400 | { |
| 401 | u32 val; |
| 402 | u32 port_base = port - 5; |
| 403 | |
| 404 | if (enable) { |
| 405 | val = mt753x_reg_read(gsw, ANA_CKBG(port_base)); |
| 406 | val |= SSUSB_PLL_SSC_EN; |
| 407 | mt753x_reg_write(gsw, ANA_CKBG(port_base), val); |
| 408 | |
| 409 | val = mt753x_reg_read(gsw, ANA_DA_FORCE_MODE1(port_base)); |
| 410 | val |= FORCE_PLL_SSC_EN; |
| 411 | mt753x_reg_write(gsw, ANA_DA_FORCE_MODE1(port_base), val); |
| 412 | } else { |
| 413 | val = mt753x_reg_read(gsw, ANA_CKBG(port_base)); |
| 414 | val &= ~SSUSB_PLL_SSC_EN; |
| 415 | mt753x_reg_write(gsw, ANA_CKBG(port_base), val); |
| 416 | |
| 417 | val = mt753x_reg_read(gsw, ANA_DA_FORCE_MODE1(port_base)); |
| 418 | val &= ~FORCE_PLL_SSC_EN; |
| 419 | mt753x_reg_write(gsw, ANA_DA_FORCE_MODE1(port_base), val); |
| 420 | } |
| 421 | } |
| 422 | |
| 423 | static int mt7531_set_port_rgmii(struct gsw_mt753x *gsw, u32 port) |
| 424 | { |
| 425 | u32 val; |
| 426 | |
| 427 | if (port != 5) { |
| 428 | dev_info(gsw->dev, "RGMII mode is not available for port %d\n", |
| 429 | port); |
| 430 | return -EINVAL; |
| 431 | } |
| 432 | |
| 433 | val = mt753x_reg_read(gsw, CLKGEN_CTRL); |
| 434 | val |= GP_CLK_EN; |
| 435 | val &= ~GP_MODE_M; |
| 436 | val |= GP_MODE_RGMII << GP_MODE_S; |
| 437 | val |= TXCLK_NO_REVERSE; |
| 438 | val |= RXCLK_NO_DELAY; |
| 439 | val &= ~CLK_SKEW_IN_M; |
| 440 | val |= CLK_SKEW_IN_NO_CHANGE << CLK_SKEW_IN_S; |
| 441 | val &= ~CLK_SKEW_OUT_M; |
| 442 | val |= CLK_SKEW_OUT_NO_CHANGE << CLK_SKEW_OUT_S; |
| 443 | mt753x_reg_write(gsw, CLKGEN_CTRL, val); |
| 444 | |
| 445 | return 0; |
| 446 | } |
| 447 | |
| 448 | static int mt7531_mac_port_setup(struct gsw_mt753x *gsw, u32 port, |
| 449 | struct mt753x_port_cfg *port_cfg) |
| 450 | { |
| 451 | u32 pmcr; |
| 452 | u32 speed; |
| 453 | |
| 454 | if (port < 5 || port >= MT753X_NUM_PORTS) { |
| 455 | dev_info(gsw->dev, "port %d is not a MAC port\n", port); |
| 456 | return -EINVAL; |
| 457 | } |
| 458 | |
| 459 | if (port_cfg->enabled) { |
| 460 | pmcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | |
| 461 | MAC_MODE | MAC_TX_EN | MAC_RX_EN | |
| 462 | BKOFF_EN | BACKPR_EN; |
| 463 | |
| 464 | if (port_cfg->force_link) { |
| 465 | /* PMCR's speed field 0x11 is reserved, |
| 466 | * sw should set 0x10 |
| 467 | */ |
| 468 | speed = port_cfg->speed; |
| 469 | if (port_cfg->speed == MAC_SPD_2500) |
| 470 | speed = MAC_SPD_1000; |
| 471 | |
| 472 | pmcr |= FORCE_MODE_LNK | FORCE_LINK | |
| 473 | FORCE_MODE_SPD | FORCE_MODE_DPX | |
| 474 | FORCE_MODE_RX_FC | FORCE_MODE_TX_FC | |
| 475 | FORCE_RX_FC | FORCE_TX_FC | |
| 476 | (speed << FORCE_SPD_S); |
| 477 | |
| 478 | if (port_cfg->duplex) |
| 479 | pmcr |= FORCE_DPX; |
| 480 | } |
| 481 | } else { |
| 482 | pmcr = FORCE_MODE_LNK; |
| 483 | } |
| 484 | |
| 485 | switch (port_cfg->phy_mode) { |
| 486 | case PHY_INTERFACE_MODE_RGMII: |
| 487 | mt7531_set_port_rgmii(gsw, port); |
| 488 | break; |
| 489 | case PHY_INTERFACE_MODE_SGMII: |
| 490 | if (port_cfg->force_link) |
| 491 | mt7531_set_port_sgmii_force_mode(gsw, port, port_cfg); |
| 492 | else |
| 493 | mt7531_set_port_sgmii_an_mode(gsw, port, port_cfg); |
| 494 | |
| 495 | mt7531_sgmii_ssc(gsw, port, port_cfg->ssc_on); |
| 496 | break; |
| 497 | default: |
| 498 | if (port_cfg->enabled) |
| 499 | dev_info(gsw->dev, "%s is not supported by port %d\n", |
| 500 | phy_modes(port_cfg->phy_mode), port); |
| 501 | |
| 502 | pmcr = FORCE_MODE_LNK; |
| 503 | } |
| 504 | |
| 505 | mt753x_reg_write(gsw, PMCR(port), pmcr); |
| 506 | |
| 507 | return 0; |
| 508 | } |
| 509 | |
| 510 | static void mt7531_core_pll_setup(struct gsw_mt753x *gsw) |
| 511 | { |
| 512 | u32 val; |
| 513 | u32 top_sig; |
| 514 | u32 hwstrap; |
| 515 | u32 xtal; |
| 516 | |
| 517 | val = mt753x_reg_read(gsw, CHIP_REV); |
| 518 | top_sig = mt753x_reg_read(gsw, TOP_SIG_SR); |
| 519 | hwstrap = mt753x_reg_read(gsw, HWSTRAP); |
| 520 | if ((val & CHIP_REV_M) > 0) |
| 521 | xtal = (top_sig & PAD_MCM_SMI_EN) ? XTAL_40MHZ : XTAL_25MHZ; |
| 522 | else |
| 523 | xtal = (hwstrap & XTAL_FSEL_M) >> XTAL_FSEL_S; |
| 524 | |
| 525 | /* dump HW strap and XTAL */ |
| 526 | dev_info(gsw->dev, "HWSTRAP=0x%x XTAL=%dMHz\n", hwstrap, |
| 527 | (xtal == XTAL_25MHZ) ? 25 : 40); |
| 528 | |
| 529 | /* Only BE needs additional setting */ |
| 530 | if (top_sig & PAD_DUAL_SGMII_EN) |
| 531 | return; |
| 532 | |
| 533 | /* Disable Port5 SGMII clearly */ |
| 534 | val = mt753x_reg_read(gsw, PHYA_ANA_SYSPLL(0)); |
| 535 | val &= ~RG_VUSB10_ON; |
| 536 | mt753x_reg_write(gsw, PHYA_ANA_SYSPLL(0), val); |
| 537 | |
| 538 | switch (xtal) { |
| 539 | case XTAL_25MHZ: |
| 540 | /* Step 1 : Disable MT7531 COREPLL */ |
| 541 | val = mt753x_reg_read(gsw, PLLGP_EN); |
| 542 | val &= ~EN_COREPLL; |
| 543 | mt753x_reg_write(gsw, PLLGP_EN, val); |
| 544 | |
| 545 | /* Step 2: switch to XTAL output */ |
| 546 | val = mt753x_reg_read(gsw, PLLGP_EN); |
| 547 | val |= SW_CLKSW; |
| 548 | mt753x_reg_write(gsw, PLLGP_EN, val); |
| 549 | |
| 550 | val = mt753x_reg_read(gsw, PLLGP_CR0); |
| 551 | val &= ~RG_COREPLL_EN; |
| 552 | mt753x_reg_write(gsw, PLLGP_CR0, val); |
| 553 | |
| 554 | /* Step 3: disable PLLGP and enable program PLLGP */ |
| 555 | val = mt753x_reg_read(gsw, PLLGP_EN); |
| 556 | val |= SW_PLLGP; |
| 557 | mt753x_reg_write(gsw, PLLGP_EN, val); |
| 558 | |
| 559 | /* Step 4: program COREPLL output frequency to 500MHz */ |
| 560 | val = mt753x_reg_read(gsw, PLLGP_CR0); |
| 561 | val &= ~RG_COREPLL_POSDIV_M; |
| 562 | val |= 2 << RG_COREPLL_POSDIV_S; |
| 563 | mt753x_reg_write(gsw, PLLGP_CR0, val); |
| 564 | usleep_range(25, 35); |
| 565 | |
| 566 | val = mt753x_reg_read(gsw, PLLGP_CR0); |
| 567 | val &= ~RG_COREPLL_SDM_PCW_M; |
| 568 | val |= 0x140000 << RG_COREPLL_SDM_PCW_S; |
| 569 | mt753x_reg_write(gsw, PLLGP_CR0, val); |
| 570 | |
| 571 | /* Set feedback divide ratio update signal to high */ |
| 572 | val = mt753x_reg_read(gsw, PLLGP_CR0); |
| 573 | val |= RG_COREPLL_SDM_PCW_CHG; |
| 574 | mt753x_reg_write(gsw, PLLGP_CR0, val); |
| 575 | /* Wait for at least 16 XTAL clocks */ |
| 576 | usleep_range(10, 20); |
| 577 | |
| 578 | /* Step 5: set feedback divide ratio update signal to low */ |
| 579 | val = mt753x_reg_read(gsw, PLLGP_CR0); |
| 580 | val &= ~RG_COREPLL_SDM_PCW_CHG; |
| 581 | mt753x_reg_write(gsw, PLLGP_CR0, val); |
| 582 | |
| 583 | /* Enable 325M clock for SGMII */ |
| 584 | mt753x_reg_write(gsw, ANA_PLLGP_CR5, 0xad0000); |
| 585 | |
| 586 | /* Enable 250SSC clock for RGMII */ |
| 587 | mt753x_reg_write(gsw, ANA_PLLGP_CR2, 0x4f40000); |
| 588 | |
| 589 | /* Step 6: Enable MT7531 PLL */ |
| 590 | val = mt753x_reg_read(gsw, PLLGP_CR0); |
| 591 | val |= RG_COREPLL_EN; |
| 592 | mt753x_reg_write(gsw, PLLGP_CR0, val); |
| 593 | |
| 594 | val = mt753x_reg_read(gsw, PLLGP_EN); |
| 595 | val |= EN_COREPLL; |
| 596 | mt753x_reg_write(gsw, PLLGP_EN, val); |
| 597 | usleep_range(25, 35); |
| 598 | |
| 599 | break; |
| 600 | case XTAL_40MHZ: |
| 601 | /* Step 1 : Disable MT7531 COREPLL */ |
| 602 | val = mt753x_reg_read(gsw, PLLGP_EN); |
| 603 | val &= ~EN_COREPLL; |
| 604 | mt753x_reg_write(gsw, PLLGP_EN, val); |
| 605 | |
| 606 | /* Step 2: switch to XTAL output */ |
| 607 | val = mt753x_reg_read(gsw, PLLGP_EN); |
| 608 | val |= SW_CLKSW; |
| 609 | mt753x_reg_write(gsw, PLLGP_EN, val); |
| 610 | |
| 611 | val = mt753x_reg_read(gsw, PLLGP_CR0); |
| 612 | val &= ~RG_COREPLL_EN; |
| 613 | mt753x_reg_write(gsw, PLLGP_CR0, val); |
| 614 | |
| 615 | /* Step 3: disable PLLGP and enable program PLLGP */ |
| 616 | val = mt753x_reg_read(gsw, PLLGP_EN); |
| 617 | val |= SW_PLLGP; |
| 618 | mt753x_reg_write(gsw, PLLGP_EN, val); |
| 619 | |
| 620 | /* Step 4: program COREPLL output frequency to 500MHz */ |
| 621 | val = mt753x_reg_read(gsw, PLLGP_CR0); |
| 622 | val &= ~RG_COREPLL_POSDIV_M; |
| 623 | val |= 2 << RG_COREPLL_POSDIV_S; |
| 624 | mt753x_reg_write(gsw, PLLGP_CR0, val); |
| 625 | usleep_range(25, 35); |
| 626 | |
| 627 | val = mt753x_reg_read(gsw, PLLGP_CR0); |
| 628 | val &= ~RG_COREPLL_SDM_PCW_M; |
| 629 | val |= 0x190000 << RG_COREPLL_SDM_PCW_S; |
| 630 | mt753x_reg_write(gsw, PLLGP_CR0, val); |
| 631 | |
| 632 | /* Set feedback divide ratio update signal to high */ |
| 633 | val = mt753x_reg_read(gsw, PLLGP_CR0); |
| 634 | val |= RG_COREPLL_SDM_PCW_CHG; |
| 635 | mt753x_reg_write(gsw, PLLGP_CR0, val); |
| 636 | /* Wait for at least 16 XTAL clocks */ |
| 637 | usleep_range(10, 20); |
| 638 | |
| 639 | /* Step 5: set feedback divide ratio update signal to low */ |
| 640 | val = mt753x_reg_read(gsw, PLLGP_CR0); |
| 641 | val &= ~RG_COREPLL_SDM_PCW_CHG; |
| 642 | mt753x_reg_write(gsw, PLLGP_CR0, val); |
| 643 | |
| 644 | /* Enable 325M clock for SGMII */ |
| 645 | mt753x_reg_write(gsw, ANA_PLLGP_CR5, 0xad0000); |
| 646 | |
| 647 | /* Enable 250SSC clock for RGMII */ |
| 648 | mt753x_reg_write(gsw, ANA_PLLGP_CR2, 0x4f40000); |
| 649 | |
| 650 | /* Step 6: Enable MT7531 PLL */ |
| 651 | val = mt753x_reg_read(gsw, PLLGP_CR0); |
| 652 | val |= RG_COREPLL_EN; |
| 653 | mt753x_reg_write(gsw, PLLGP_CR0, val); |
| 654 | |
| 655 | val = mt753x_reg_read(gsw, PLLGP_EN); |
| 656 | val |= EN_COREPLL; |
| 657 | mt753x_reg_write(gsw, PLLGP_EN, val); |
| 658 | usleep_range(25, 35); |
| 659 | break; |
| 660 | } |
| 661 | } |
| 662 | |
| 663 | static int mt7531_internal_phy_calibration(struct gsw_mt753x *gsw) |
| 664 | { |
| 665 | return 0; |
| 666 | } |
| 667 | |
| 668 | static int mt7531_sw_detect(struct gsw_mt753x *gsw, struct chip_rev *crev) |
| 669 | { |
| 670 | u32 rev, topsig; |
| 671 | |
| 672 | rev = mt753x_reg_read(gsw, CHIP_REV); |
| 673 | |
| 674 | if (((rev & CHIP_NAME_M) >> CHIP_NAME_S) == MT7531) { |
| 675 | if (crev) { |
| 676 | topsig = mt753x_reg_read(gsw, TOP_SIG_SR); |
| 677 | |
| 678 | crev->rev = rev & CHIP_REV_M; |
| 679 | crev->name = topsig & PAD_DUAL_SGMII_EN ? |
| 680 | "MT7531AE" : "MT7531BE"; |
| 681 | } |
| 682 | |
| 683 | return 0; |
| 684 | } |
| 685 | |
| 686 | return -ENODEV; |
| 687 | } |
| 688 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 689 | static int mt7988_sw_detect(struct gsw_mt753x *gsw, struct chip_rev *crev) |
| 690 | { |
| 691 | const char *model; |
| 692 | struct device_node *np; |
| 693 | |
| 694 | np = of_find_compatible_node(NULL, NULL, "mediatek,mt7988-switch"); |
| 695 | if (!np) |
| 696 | return -ENODEV; |
| 697 | |
| 698 | of_node_put(np); |
| 699 | |
| 700 | crev->rev = 0; |
| 701 | crev->name = "MT7988"; |
| 702 | gsw->direct_access = true; |
| 703 | |
| 704 | return 0; |
| 705 | } |
| 706 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 707 | static void pinmux_set_mux_7531(struct gsw_mt753x *gsw, u32 pin, u32 mode) |
| 708 | { |
| 709 | u32 val; |
| 710 | |
| 711 | val = mt753x_reg_read(gsw, GPIO_MODE_REGS(pin)); |
| 712 | val &= ~(0xf << (pin & 7) * GPIO_MODE_S); |
| 713 | val |= mode << (pin & 7) * GPIO_MODE_S; |
| 714 | mt753x_reg_write(gsw, GPIO_MODE_REGS(pin), val); |
| 715 | } |
| 716 | |
| 717 | static int mt7531_set_gpio_pinmux(struct gsw_mt753x *gsw) |
| 718 | { |
| 719 | u32 group = 0; |
| 720 | struct device_node *np = gsw->dev->of_node; |
| 721 | |
| 722 | /* Set GPIO 0 interrupt mode */ |
| 723 | pinmux_set_mux_7531(gsw, gpio_int_pins[0], gpio_int_funcs[0]); |
| 724 | |
| 725 | of_property_read_u32(np, "mediatek,mdio_master_pinmux", &group); |
| 726 | |
| 727 | /* group = 0: do nothing, 1: 1st group (AE), 2: 2nd group (BE) */ |
| 728 | if (group > 0 && group <= 2) { |
| 729 | group--; |
| 730 | pinmux_set_mux_7531(gsw, gpio_mdc_pins[group], |
| 731 | gpio_mdc_funcs[group]); |
| 732 | pinmux_set_mux_7531(gsw, gpio_mdio_pins[group], |
| 733 | gpio_mdio_funcs[group]); |
| 734 | } |
| 735 | |
| 736 | return 0; |
| 737 | } |
| 738 | |
| 739 | static void mt7531_phy_pll_setup(struct gsw_mt753x *gsw) |
| 740 | { |
| 741 | u32 hwstrap; |
| 742 | u32 val; |
| 743 | |
| 744 | val = mt753x_reg_read(gsw, CHIP_REV); |
| 745 | if ((val & CHIP_REV_M) > 0) |
| 746 | return; |
| 747 | |
| 748 | hwstrap = mt753x_reg_read(gsw, HWSTRAP); |
| 749 | |
| 750 | switch ((hwstrap & XTAL_FSEL_M) >> XTAL_FSEL_S) { |
| 751 | case XTAL_25MHZ: |
| 752 | /* disable pll auto calibration */ |
| 753 | gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_104, 0x608); |
| 754 | |
| 755 | /* change pll sel */ |
| 756 | val = gsw->mmd_read(gsw, 0, PHY_DEV1F, |
| 757 | PHY_DEV1F_REG_403); |
| 758 | val &= ~(PHY_PLL_M); |
| 759 | val |= PHY_PLL_SEL(3); |
| 760 | gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403, val); |
| 761 | |
| 762 | /* set divider ratio */ |
| 763 | gsw->mmd_write(gsw, 0, PHY_DEV1F, |
| 764 | PHY_DEV1F_REG_10A, 0x1009); |
| 765 | |
| 766 | /* set divider ratio */ |
| 767 | gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_10B, 0x7c6); |
| 768 | |
| 769 | /* capacitance and resistance adjustment */ |
| 770 | gsw->mmd_write(gsw, 0, PHY_DEV1F, |
| 771 | PHY_DEV1F_REG_10C, 0xa8be); |
| 772 | |
| 773 | break; |
| 774 | case XTAL_40MHZ: |
| 775 | /* disable pll auto calibration */ |
| 776 | gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_104, 0x608); |
| 777 | |
| 778 | /* change pll sel */ |
| 779 | val = gsw->mmd_read(gsw, 0, PHY_DEV1F, |
| 780 | PHY_DEV1F_REG_403); |
| 781 | val &= ~(PHY_PLL_M); |
| 782 | val |= PHY_PLL_SEL(3); |
| 783 | gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403, val); |
| 784 | |
| 785 | /* set divider ratio */ |
| 786 | gsw->mmd_write(gsw, 0, PHY_DEV1F, |
| 787 | PHY_DEV1F_REG_10A, 0x1018); |
| 788 | |
| 789 | /* set divider ratio */ |
| 790 | gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_10B, 0xc676); |
| 791 | |
| 792 | /* capacitance and resistance adjustment */ |
| 793 | gsw->mmd_write(gsw, 0, PHY_DEV1F, |
| 794 | PHY_DEV1F_REG_10C, 0xd8be); |
| 795 | break; |
| 796 | } |
| 797 | |
| 798 | /* power down pll. additional delay is not required via mdio access */ |
| 799 | gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_10D, 0x10); |
| 800 | |
| 801 | /* power up pll */ |
| 802 | gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_10D, 0x14); |
| 803 | } |
| 804 | |
| 805 | /* 12 registers for TX_MLT3 waveform tuning. |
| 806 | * 012 345 678 9ab |
| 807 | * 1 __ |
| 808 | * _/ \_ |
| 809 | * 0_/ \ |
| 810 | * \_ _/ |
| 811 | * -1 \__/ |
| 812 | */ |
| 813 | static void mt7531_phy_100m_eye_diag_setting(struct gsw_mt753x *gsw, u32 port) |
| 814 | { |
| 815 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_TX_MLT3_BASE + 0x0, 0x187); |
| 816 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_TX_MLT3_BASE + 0x1, 0x1c9); |
| 817 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_TX_MLT3_BASE + 0x2, 0x1c6); |
| 818 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_TX_MLT3_BASE + 0x3, 0x182); |
| 819 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_TX_MLT3_BASE + 0x4, 0x208); |
| 820 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_TX_MLT3_BASE + 0x5, 0x205); |
| 821 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_TX_MLT3_BASE + 0x6, 0x384); |
| 822 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_TX_MLT3_BASE + 0x7, 0x3cb); |
| 823 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_TX_MLT3_BASE + 0x8, 0x3c4); |
| 824 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_TX_MLT3_BASE + 0x9, 0x30a); |
| 825 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_TX_MLT3_BASE + 0xa, 0x00b); |
| 826 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_TX_MLT3_BASE + 0xb, 0x002); |
| 827 | } |
| 828 | |
| 829 | static void mt7531_phy_setting(struct gsw_mt753x *gsw) |
| 830 | { |
| 831 | int i; |
| 832 | u32 val; |
| 833 | |
| 834 | for (i = 0; i < MT753X_NUM_PHYS; i++) { |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 835 | if (!gsw->direct_access) |
| 836 | mt7531_phy_100m_eye_diag_setting(gsw, i); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 837 | |
| 838 | /* Enable HW auto downshift */ |
| 839 | gsw->mii_write(gsw, i, 0x1f, 0x1); |
| 840 | val = gsw->mii_read(gsw, i, PHY_EXT_REG_14); |
| 841 | val |= PHY_EN_DOWN_SHFIT; |
| 842 | gsw->mii_write(gsw, i, PHY_EXT_REG_14, val); |
| 843 | |
| 844 | /* Decrease SlvDPSready time */ |
| 845 | val = mt753x_tr_read(gsw, i, PMA_CH, PMA_NOD, PMA_17); |
| 846 | val &= ~SLV_DSP_READY_TIME_M; |
| 847 | val |= 0xc << SLV_DSP_READY_TIME_S; |
| 848 | mt753x_tr_write(gsw, i, PMA_CH, PMA_NOD, PMA_17, val); |
| 849 | |
| 850 | /* Enable Random Update Mechanism */ |
| 851 | val = mt753x_tr_read(gsw, i, PMA_CH, PMA_NOD, PMA_18); |
| 852 | val |= ENABLE_RANDOM_UPDATE_TRIGGER; |
| 853 | mt753x_tr_write(gsw, i, PMA_CH, PMA_NOD, PMA_18, val); |
| 854 | |
| 855 | /* PHY link down power saving enable */ |
| 856 | val = gsw->mii_read(gsw, i, PHY_EXT_REG_17); |
| 857 | val |= PHY_LINKDOWN_POWER_SAVING_EN; |
| 858 | gsw->mii_write(gsw, i, PHY_EXT_REG_17, val); |
| 859 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 860 | if (!gsw->direct_access) { |
| 861 | val = gsw->mmd_read(gsw, i, PHY_DEV1E, |
| 862 | PHY_DEV1E_REG_0C6); |
| 863 | val &= ~PHY_POWER_SAVING_M; |
| 864 | val |= PHY_POWER_SAVING_TX << PHY_POWER_SAVING_S; |
| 865 | gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_0C6, |
| 866 | val); |
| 867 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 868 | |
| 869 | /* Timing Recovery for GbE slave mode */ |
| 870 | mt753x_tr_write(gsw, i, PMA_CH, PMA_NOD, PMA_01, 0x6fb90a); |
| 871 | mt753x_tr_write(gsw, i, DSP_CH, DSP_NOD, DSP_06, 0x2ebaef); |
| 872 | val = gsw->mmd_read(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_234); |
| 873 | val |= TR_OPEN_LOOP_EN; |
| 874 | gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_234, val); |
| 875 | |
| 876 | /* Enable Asymmetric Pause Capability */ |
| 877 | val = gsw->mii_read(gsw, i, MII_ADVERTISE); |
| 878 | val |= ADVERTISE_PAUSE_ASYM; |
| 879 | gsw->mii_write(gsw, i, MII_ADVERTISE, val); |
| 880 | } |
| 881 | } |
| 882 | |
| 883 | static void mt7531_adjust_line_driving(struct gsw_mt753x *gsw, u32 port) |
| 884 | { |
| 885 | /* For ADC timing margin window for LDO calibration */ |
| 886 | gsw->mmd_write(gsw, port, PHY_DEV1E, RXADC_LDO_CONTROL_2, 0x2222); |
| 887 | |
| 888 | /* Adjust AD sample timing */ |
| 889 | gsw->mmd_write(gsw, port, PHY_DEV1E, RXADC_CONTROL_3, 0x4444); |
| 890 | |
| 891 | /* Adjust Line driver current for different mode */ |
| 892 | gsw->mmd_write(gsw, port, PHY_DEV1F, TXVLD_DA_271, 0x2ca5); |
| 893 | |
| 894 | /* Adjust Line driver current for different mode */ |
| 895 | gsw->mmd_write(gsw, port, PHY_DEV1F, TXVLD_DA_272, 0xc6b); |
| 896 | |
| 897 | /* Adjust Line driver gain for 10BT from 1000BT calibration result */ |
| 898 | gsw->mmd_write(gsw, port, PHY_DEV1F, TXVLD_DA_273, 0x3000); |
| 899 | |
| 900 | /* Adjust RX Echo path filter */ |
developer | d1ea115 | 2022-10-13 18:24:48 +0800 | [diff] [blame] | 901 | if (!gsw->direct_access) |
| 902 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_0FE, 0x2); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 903 | |
| 904 | /* Adjust RX HVGA bias current */ |
| 905 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_41, 0x3333); |
| 906 | |
| 907 | /* Adjust TX class AB driver 1 */ |
| 908 | gsw->mmd_write(gsw, port, PHY_DEV1F, PHY_DEV1F_REG_268, 0x384); |
| 909 | |
| 910 | /* Adjust TX class AB driver 2 */ |
| 911 | gsw->mmd_write(gsw, port, PHY_DEV1F, PHY_DEV1F_REG_269, 0x1114); |
| 912 | |
| 913 | /* Adjust DAC delay for TX Pairs */ |
| 914 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_13, 0x404); |
| 915 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_14, 0x404); |
| 916 | |
| 917 | /* Adjust DAC digital delay for TX Delay */ |
| 918 | gsw->mmd_write(gsw, port, PHY_DEV1F, PHY_DEV1F_REG_44, 0xc0); |
| 919 | |
| 920 | /* Adjust Line driver compensation cap for stability concern due to |
| 921 | * increase current. |
| 922 | */ |
| 923 | gsw->mmd_write(gsw, port, PHY_DEV1F, PHY_DEV1F_REG_26A, 0x3333); |
| 924 | } |
| 925 | |
| 926 | static void mt7531_eee_setting(struct gsw_mt753x *gsw, u32 port) |
| 927 | { |
| 928 | u32 val; |
| 929 | |
| 930 | /* Disable EEE */ |
| 931 | gsw->mmd_write(gsw, port, PHY_DEV07, PHY_DEV07_REG_03C, 0); |
| 932 | |
| 933 | /* Disable generate signal to clear the scramble_lock when lpi mode */ |
| 934 | val = gsw->mmd_read(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_189); |
| 935 | val &= ~DESCRAMBLER_CLEAR_EN; |
| 936 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_189, val); |
| 937 | |
| 938 | /* Roll back EEE Slave Mode */ |
| 939 | gsw->mmd_write(gsw, port, 0x1e, 0x2d1, 0); |
| 940 | mt753x_tr_write(gsw, port, DSP_CH, DSP_NOD, DSP_08, 0x1b); |
| 941 | mt753x_tr_write(gsw, port, DSP_CH, DSP_NOD, DSP_0f, 0); |
| 942 | mt753x_tr_write(gsw, port, DSP_CH, DSP_NOD, DSP_10, 0x5000); |
| 943 | |
| 944 | /* Adjust 100_mse_threshold */ |
| 945 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_123, 0xffff); |
| 946 | |
| 947 | /* Disable mcc */ |
| 948 | gsw->mmd_write(gsw, port, PHY_DEV1E, PHY_DEV1E_REG_A6, 0x300); |
| 949 | } |
| 950 | |
| 951 | static void mt7531_afifo_reset(struct gsw_mt753x *gsw, int enable) |
| 952 | { |
| 953 | int p; |
| 954 | u32 val; |
| 955 | |
| 956 | if (enable) { |
| 957 | for (p = 0; p < MT753X_NUM_PORTS; p++) { |
| 958 | val = mt753x_reg_read(gsw, DBG_CNT(p)); |
| 959 | val &= ~DIS_CLR; |
| 960 | mt753x_reg_write(gsw, DBG_CNT(p), val); |
| 961 | } |
| 962 | } else { |
| 963 | for (p = 0; p < MT753X_NUM_PORTS; p++) { |
| 964 | val = mt753x_reg_read(gsw, DBG_CNT(p)); |
| 965 | val |= DIS_CLR; |
| 966 | mt753x_reg_write(gsw, DBG_CNT(p), val); |
| 967 | } |
| 968 | } |
| 969 | } |
| 970 | |
| 971 | static int mt7531_sw_init(struct gsw_mt753x *gsw) |
| 972 | { |
| 973 | int i; |
| 974 | u32 val; |
| 975 | |
| 976 | gsw->phy_base = (gsw->smi_addr + 1) & MT753X_SMI_ADDR_MASK; |
| 977 | |
| 978 | gsw->mii_read = mt753x_mii_read; |
| 979 | gsw->mii_write = mt753x_mii_write; |
| 980 | gsw->mmd_read = mt753x_mmd_read; |
| 981 | gsw->mmd_write = mt753x_mmd_write; |
| 982 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 983 | gsw->hw_phy_cal = of_property_read_bool(gsw->dev->of_node, |
| 984 | "mediatek,hw_phy_cal"); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 985 | |
| 986 | for (i = 0; i < MT753X_NUM_PHYS; i++) { |
| 987 | val = gsw->mii_read(gsw, i, MII_BMCR); |
| 988 | val |= BMCR_ISOLATE; |
| 989 | gsw->mii_write(gsw, i, MII_BMCR, val); |
| 990 | } |
| 991 | |
| 992 | /* Force MAC link down before reset */ |
| 993 | mt753x_reg_write(gsw, PMCR(5), FORCE_MODE_LNK); |
| 994 | mt753x_reg_write(gsw, PMCR(6), FORCE_MODE_LNK); |
| 995 | |
| 996 | /* Switch soft reset */ |
| 997 | mt753x_reg_write(gsw, SYS_CTRL, SW_SYS_RST | SW_REG_RST); |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 998 | udelay(20); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 999 | |
| 1000 | /* Enable MDC input Schmitt Trigger */ |
| 1001 | val = mt753x_reg_read(gsw, SMT0_IOLB); |
| 1002 | mt753x_reg_write(gsw, SMT0_IOLB, val | SMT_IOLB_5_SMI_MDC_EN); |
| 1003 | |
| 1004 | /* Set 7531 gpio pinmux */ |
| 1005 | mt7531_set_gpio_pinmux(gsw); |
| 1006 | |
| 1007 | mt7531_core_pll_setup(gsw); |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 1008 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1009 | mt7531_mac_port_setup(gsw, 5, &gsw->port5_cfg); |
| 1010 | mt7531_mac_port_setup(gsw, 6, &gsw->port6_cfg); |
| 1011 | |
| 1012 | /* Global mac control settings */ |
| 1013 | mt753x_reg_write(gsw, GMACCR, |
| 1014 | (15 << MTCC_LMT_S) | (15 << MAX_RX_JUMBO_S) | |
| 1015 | RX_PKT_LEN_MAX_JUMBO); |
| 1016 | |
| 1017 | /* Enable Collision Poll */ |
| 1018 | val = mt753x_reg_read(gsw, CPGC_CTRL); |
| 1019 | val |= COL_CLK_EN; |
| 1020 | mt753x_reg_write(gsw, CPGC_CTRL, val); |
| 1021 | val |= COL_RST_N; |
| 1022 | mt753x_reg_write(gsw, CPGC_CTRL, val); |
| 1023 | val |= COL_EN; |
| 1024 | mt753x_reg_write(gsw, CPGC_CTRL, val); |
| 1025 | |
| 1026 | /* Disable AFIFO reset for extra short IPG */ |
| 1027 | mt7531_afifo_reset(gsw, 0); |
| 1028 | |
| 1029 | return 0; |
| 1030 | } |
| 1031 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 1032 | static int mt7988_sw_init(struct gsw_mt753x *gsw) |
| 1033 | { |
| 1034 | struct device_node *switch_node = NULL; |
| 1035 | struct platform_device *pdev; |
| 1036 | int i; |
| 1037 | u32 val; |
| 1038 | u32 pmcr; |
| 1039 | u32 speed; |
| 1040 | |
| 1041 | switch_node = of_find_node_by_name(NULL, "switch0"); |
| 1042 | if (switch_node == NULL) { |
| 1043 | dev_err(&pdev->dev, "switch node invaild\n"); |
| 1044 | return -ENOENT; |
| 1045 | } |
| 1046 | |
| 1047 | gsw->base = of_iomap(switch_node, 0); |
| 1048 | if (IS_ERR(gsw->base)) { |
| 1049 | dev_err(&pdev->dev, "switch ioremap failed\n"); |
| 1050 | return -EIO; |
| 1051 | } |
| 1052 | |
| 1053 | pdev = container_of(gsw->dev, struct platform_device, dev); |
| 1054 | gsw->sysctrl_base = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, |
| 1055 | "mediatek,sysctrl"); |
| 1056 | if (IS_ERR(gsw->sysctrl_base)) { |
| 1057 | dev_err(&pdev->dev, "no sysctl regmap found\n"); |
| 1058 | return -ENODEV; |
| 1059 | } |
| 1060 | |
| 1061 | /* reset control */ |
| 1062 | regmap_write(gsw->sysctrl_base, ETH_RESET, 0x200); |
| 1063 | udelay(20); |
| 1064 | regmap_write(gsw->sysctrl_base, ETH_RESET, 0); |
| 1065 | udelay(20); |
| 1066 | |
| 1067 | gsw->phy_base = (gsw->smi_addr + 1) & MT753X_SMI_ADDR_MASK; |
| 1068 | |
| 1069 | gsw->mii_read = mt753x_mii_read; |
| 1070 | gsw->mii_write = mt753x_mii_write; |
| 1071 | gsw->mmd_read = mt753x_mmd_read; |
| 1072 | gsw->mmd_write = mt753x_mmd_write; |
| 1073 | |
| 1074 | for (i = 0; i < MT753X_NUM_PHYS; i++) { |
| 1075 | val = gsw->mii_read(gsw, i, MII_BMCR); |
| 1076 | val |= BMCR_ISOLATE; |
| 1077 | gsw->mii_write(gsw, i, MII_BMCR, val); |
| 1078 | } |
| 1079 | |
| 1080 | speed = MAC_SPD_1000; |
| 1081 | pmcr = (IPG_96BIT_WITH_SHORT_IPG << IPG_CFG_S) | |
| 1082 | MAC_MODE | MAC_TX_EN | MAC_RX_EN | BKOFF_EN | |
| 1083 | BACKPR_EN | FORCE_MODE_LNK | FORCE_LINK | FORCE_MODE_SPD | |
| 1084 | FORCE_MODE_DPX | FORCE_MODE_RX_FC | FORCE_MODE_TX_FC | |
| 1085 | FORCE_RX_FC | FORCE_TX_FC | (speed << FORCE_SPD_S) | FORCE_DPX; |
| 1086 | |
| 1087 | mt753x_reg_write(gsw, PMCR(6), pmcr); |
| 1088 | |
| 1089 | /* Global mac control settings */ |
| 1090 | mt753x_reg_write(gsw, GMACCR, |
| 1091 | (15 << MTCC_LMT_S) | (15 << MAX_RX_JUMBO_S) | |
| 1092 | RX_PKT_LEN_MAX_JUMBO); |
| 1093 | |
| 1094 | /* Enable Collision Poll */ |
| 1095 | val = mt753x_reg_read(gsw, CPGC_CTRL); |
| 1096 | val |= COL_CLK_EN; |
| 1097 | mt753x_reg_write(gsw, CPGC_CTRL, val); |
| 1098 | val |= COL_RST_N; |
| 1099 | mt753x_reg_write(gsw, CPGC_CTRL, val); |
| 1100 | val |= COL_EN; |
| 1101 | mt753x_reg_write(gsw, CPGC_CTRL, val); |
| 1102 | |
| 1103 | /* Disable AFIFO reset for extra short IPG */ |
| 1104 | mt7531_afifo_reset(gsw, 0); |
| 1105 | |
| 1106 | /* PHY force slave 1G*/ |
| 1107 | for (i = 0; i < MT753X_NUM_PHYS; i++) { |
| 1108 | gsw->mii_write(gsw, i, MII_CTRL1000, 0x1200); |
| 1109 | gsw->mii_write(gsw, i, MII_BMCR, 0x140); |
| 1110 | } |
| 1111 | |
| 1112 | return 0; |
| 1113 | } |
| 1114 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1115 | static int mt7531_sw_post_init(struct gsw_mt753x *gsw) |
| 1116 | { |
| 1117 | int i; |
| 1118 | u32 val; |
| 1119 | |
| 1120 | /* Let internal PHYs only Tx constant data in configure stage. */ |
| 1121 | for (i = 0; i < MT753X_NUM_PHYS; i++) |
| 1122 | gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_141, 0x200); |
| 1123 | |
| 1124 | /* Internal PHYs might be enabled by HW Bootstrapping, or bootloader. |
| 1125 | * Turn off PHYs before setup PHY PLL. |
| 1126 | */ |
| 1127 | val = gsw->mmd_read(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403); |
| 1128 | val |= PHY_EN_BYPASS_MODE; |
| 1129 | val |= POWER_ON_OFF; |
| 1130 | gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403, val); |
| 1131 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 1132 | if (!gsw->direct_access) |
| 1133 | mt7531_phy_pll_setup(gsw); |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1134 | |
| 1135 | /* Enable Internal PHYs before phy setting */ |
| 1136 | val = gsw->mmd_read(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403); |
| 1137 | val |= PHY_EN_BYPASS_MODE; |
| 1138 | val &= ~POWER_ON_OFF; |
| 1139 | gsw->mmd_write(gsw, 0, PHY_DEV1F, PHY_DEV1F_REG_403, val); |
| 1140 | |
| 1141 | mt7531_phy_setting(gsw); |
| 1142 | |
| 1143 | for (i = 0; i < MT753X_NUM_PHYS; i++) { |
| 1144 | val = gsw->mii_read(gsw, i, MII_BMCR); |
| 1145 | val &= ~BMCR_ISOLATE; |
| 1146 | gsw->mii_write(gsw, i, MII_BMCR, val); |
| 1147 | } |
| 1148 | |
| 1149 | for (i = 0; i < MT753X_NUM_PHYS; i++) { |
| 1150 | mt7531_adjust_line_driving(gsw, i); |
| 1151 | mt7531_eee_setting(gsw, i); |
| 1152 | } |
| 1153 | |
| 1154 | /* Restore internal PHYs normal Tx function after configure stage. */ |
| 1155 | for (i = 0; i < MT753X_NUM_PHYS; i++) |
| 1156 | gsw->mmd_write(gsw, i, PHY_DEV1E, PHY_DEV1E_REG_141, 0x0); |
| 1157 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 1158 | if (!gsw->direct_access) |
| 1159 | mt7531_internal_phy_calibration(gsw); |
| 1160 | |
| 1161 | /* PHY force slave disable, restart AN*/ |
| 1162 | for (i = 0; i < MT753X_NUM_PHYS; i++) { |
| 1163 | gsw->mii_write(gsw, i, MII_CTRL1000, 0x200); |
| 1164 | gsw->mii_write(gsw, i, MII_BMCR, 0x1240); |
| 1165 | } |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1166 | |
| 1167 | return 0; |
| 1168 | } |
| 1169 | |
| 1170 | struct mt753x_sw_id mt7531_id = { |
| 1171 | .model = MT7531, |
| 1172 | .detect = mt7531_sw_detect, |
| 1173 | .init = mt7531_sw_init, |
| 1174 | .post_init = mt7531_sw_post_init |
| 1175 | }; |
| 1176 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 1177 | struct mt753x_sw_id mt7988_id = { |
| 1178 | .model = MT7988, |
| 1179 | .detect = mt7988_sw_detect, |
| 1180 | .init = mt7988_sw_init, |
| 1181 | .post_init = mt7531_sw_post_init |
| 1182 | }; |
| 1183 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1184 | MODULE_LICENSE("GPL"); |
| 1185 | MODULE_AUTHOR("Zhanguo Ju <zhanguo.ju@mediatek.com>"); |
| 1186 | MODULE_DESCRIPTION("Driver for MediaTek MT753x Gigabit Switch"); |