target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986b-2500wan-sd-rfb.dts

/dts-v1/;
#include "mt7986b.dtsi"
#include "mt7986b-pinctrl.dtsi"
/ {
	model = "MediaTek MT7986b RFB";
	compatible = "mediatek,mt7986b-2500wan-sd-rfb";
	chosen {
		bootargs = "console=ttyS0,115200n1 loglevel=8  \
			earlycon=uart8250,mmio32,0x11002000 \
			root=PARTLABEL=rootfs rootwait rootfstype=squashfs,f2fs";
	};

	memory {
		reg = <0 0x40000000 0 0x10000000>;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "fixed-3.3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};
};

&uart0 {
	status = "okay";
};

/* Warning: pins shared with &snand */
&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart1_pins>;
	status = "disabled";
};

/* Warning: pins shared with &spi1 */
&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&uart2_pins>;
	status = "disabled";
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c_pins>;
	status = "okay";
};

&watchdog {
	status = "okay";
};

&eth {
	status = "okay";

	gmac0: mac@0 {
		compatible = "mediatek,eth-mac";
		reg = <0>;
		phy-mode = "2500base-x";

		fixed-link {
			speed = <2500>;
			full-duplex;
			pause;
			link-gpio = <&pio 47 0>;
			phy-handle = <&phy5>;
			label = "lan5";
		};
	};

	gmac1: mac@1 {
		compatible = "mediatek,eth-mac";
		reg = <1>;
		phy-mode = "2500base-x";
		phy-handle = <&phy6>;
	};

	mdio: mdio-bus {
		#address-cells = <1>;
		#size-cells = <0>;

		reset-gpios = <&pio 6 1>;
		reset-delay-us = <600>;

		phy5: phy@5 {
			compatible = "ethernet-phy-id67c9.de0a";
			reg = <5>;
		};

		phy6: phy@6 {
			compatible = "ethernet-phy-ieee802.3-c45";
			reg = <6>;
		};

		switch@0 {
			compatible = "mediatek,mt7531";
			reg = <31>;
			reset-gpios = <&pio 5 0>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				port@0 {
					reg = <0>;
					label = "lan0";
				};

				port@1 {
					reg = <1>;
					label = "lan1";
				};

				port@2 {
					reg = <2>;
					label = "lan2";
				};

				port@3 {
					reg = <3>;
					label = "lan3";
				};

				port@4 {
					reg = <4>;
					label = "lan4";
				};

				port@5 {
					reg = <5>;
					label = "lan5";
					phy-mode = "2500base-x";

					fixed-link {
						speed = <2500>;
						full-duplex;
						pause;
					};
				};

				port@6 {
					reg = <6>;
					label = "cpu";
					ethernet = <&gmac0>;
					phy-mode = "2500base-x";

					fixed-link {
						speed = <2500>;
						full-duplex;
						pause;
					};
				};
			};
		};
	};
};

&hnat {
	mtketh-wan = "eth1";
	mtketh-lan = "lan";
	mtketh-max-gmac = <2>;
	status = "okay";
};

&mmc0 {
	pinctrl-names = "default", "state_uhs";
	pinctrl-0 = <&mmc0_pins_default>;
	pinctrl-1 = <&mmc0_pins_uhs>;
	bus-width = <4>;
	max-frequency = <52000000>;
	cap-sd-highspeed;
	vmmc-supply = <&reg_3p3v>;
	vqmmc-supply = <&reg_3p3v>;
	status = "okay";
};

&pio {
	mmc0_pins_default: mmc0-pins-22-to-32-default {
		mux {
			function = "flash";
			groups = "emmc_45";
		};

		conf-cmd-dat {
			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
			       "SPI0_CS", "SPI0_HOLD", "SPI0_WP",
			       "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
			input-enable;
			drive-strength = <MTK_DRIVE_4mA>;
			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
		};

		conf-clk {
			pins = "SPI1_CS";
			drive-strength = <MTK_DRIVE_6mA>;
			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
		};

		conf-rst {
			pins = "PWM1";
			drive-strength = <MTK_DRIVE_4mA>;
			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
		};
	};

	mmc0_pins_uhs: mmc0-pins-22-to-32-uhs {
		mux {
			function = "flash";
			groups = "emmc_45";
		};

		conf-cmd-dat {
			pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
			       "SPI0_CS", "SPI0_HOLD", "SPI0_WP",
			       "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
			input-enable;
			drive-strength = <MTK_DRIVE_4mA>;
			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
		};

		conf-clk {
			pins = "SPI1_CS";
			drive-strength = <MTK_DRIVE_6mA>;
			mediatek,pull-down-adv = <2>;	/* pull-down 50K */
		};

		conf-rst {
			pins = "PWM1";
			drive-strength = <MTK_DRIVE_4mA>;
			mediatek,pull-up-adv = <1>;	/* pull-up 10K */
		};
	};

	wf_2g_5g_pins: wf_2g_5g-pins {
		mux {
			function = "wifi";
			groups = "wf_2g", "wf_5g";
		};
		conf {
			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
			       "WF1_TOP_CLK", "WF1_TOP_DATA";
			drive-strength = <MTK_DRIVE_4mA>;
		};
	};

	wf_dbdc_pins: wf_dbdc-pins {
		mux {
			function = "wifi";
			groups = "wf_dbdc";
		};
		conf {
			pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
			       "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
			       "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
			       "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
			       "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
			       "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
			       "WF1_TOP_CLK", "WF1_TOP_DATA";
			drive-strength = <MTK_DRIVE_4mA>;
		};
	};
};