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developercd6a1382022-01-11 15:45:19 +08001/dts-v1/;
2#include "mt7986b.dtsi"
3#include "mt7986b-pinctrl.dtsi"
4/ {
5 model = "MediaTek MT7986b RFB";
6 compatible = "mediatek,mt7986b-2500wan-sd-rfb";
7 chosen {
8 bootargs = "console=ttyS0,115200n1 loglevel=8 \
9 earlycon=uart8250,mmio32,0x11002000 \
10 root=PARTLABEL=rootfs rootwait rootfstype=squashfs,f2fs";
11 };
12
13 memory {
14 reg = <0 0x40000000 0 0x10000000>;
15 };
16
17 reg_3p3v: regulator-3p3v {
18 compatible = "regulator-fixed";
19 regulator-name = "fixed-3.3V";
20 regulator-min-microvolt = <3300000>;
21 regulator-max-microvolt = <3300000>;
22 regulator-boot-on;
23 regulator-always-on;
24 };
25};
26
27&uart0 {
28 status = "okay";
29};
30
31/* Warning: pins shared with &snand */
32&uart1 {
33 pinctrl-names = "default";
34 pinctrl-0 = <&uart1_pins>;
35 status = "disabled";
36};
37
38/* Warning: pins shared with &spi1 */
39&uart2 {
40 pinctrl-names = "default";
41 pinctrl-0 = <&uart2_pins>;
42 status = "disabled";
43};
44
45&i2c0 {
46 pinctrl-names = "default";
47 pinctrl-0 = <&i2c_pins>;
48 status = "okay";
49};
50
51&watchdog {
52 status = "okay";
53};
54
55&eth {
56 status = "okay";
57
58 gmac0: mac@0 {
59 compatible = "mediatek,eth-mac";
60 reg = <0>;
61 phy-mode = "2500base-x";
developerf0a1e452022-08-15 12:06:11 +080062 phy-handle = <&phy5>;
developercd6a1382022-01-11 15:45:19 +080063 };
64
65 gmac1: mac@1 {
66 compatible = "mediatek,eth-mac";
67 reg = <1>;
68 phy-mode = "2500base-x";
developerf0a1e452022-08-15 12:06:11 +080069 phy-handle = <&phy6>;
developercd6a1382022-01-11 15:45:19 +080070 };
71
72 mdio: mdio-bus {
73 #address-cells = <1>;
74 #size-cells = <0>;
75
developerf0a1e452022-08-15 12:06:11 +080076 reset-gpios = <&pio 6 1>;
77 reset-delay-us = <600>;
78
developercd6a1382022-01-11 15:45:19 +080079 phy5: phy@5 {
developerf0a1e452022-08-15 12:06:11 +080080 compatible = "ethernet-phy-ieee802.3-c45";
developercd6a1382022-01-11 15:45:19 +080081 reg = <5>;
developercd6a1382022-01-11 15:45:19 +080082 };
83
84 phy6: phy@6 {
developerf0a1e452022-08-15 12:06:11 +080085 compatible = "ethernet-phy-ieee802.3-c45";
developercd6a1382022-01-11 15:45:19 +080086 reg = <6>;
developercd6a1382022-01-11 15:45:19 +080087 };
88
89 switch@0 {
90 compatible = "mediatek,mt7531";
91 reg = <31>;
92 reset-gpios = <&pio 5 0>;
93
94 ports {
95 #address-cells = <1>;
96 #size-cells = <0>;
97
98 port@0 {
99 reg = <0>;
100 label = "lan0";
101 };
102
103 port@1 {
104 reg = <1>;
105 label = "lan1";
106 };
107
108 port@2 {
109 reg = <2>;
110 label = "lan2";
111 };
112
113 port@3 {
114 reg = <3>;
115 label = "lan3";
116 };
117
118 port@4 {
119 reg = <4>;
120 label = "lan4";
121 };
122
123 port@5 {
124 reg = <5>;
125 label = "lan5";
126 phy-mode = "2500base-x";
127
128 fixed-link {
129 speed = <2500>;
130 full-duplex;
131 pause;
132 };
133 };
134
135 port@6 {
136 reg = <6>;
137 label = "cpu";
138 ethernet = <&gmac0>;
139 phy-mode = "2500base-x";
140
141 fixed-link {
142 speed = <2500>;
143 full-duplex;
144 pause;
145 };
146 };
147 };
148 };
149 };
150};
151
152&hnat {
153 mtketh-wan = "eth1";
154 mtketh-lan = "lan";
155 mtketh-max-gmac = <2>;
156 status = "okay";
157};
158
159&mmc0 {
160 pinctrl-names = "default", "state_uhs";
161 pinctrl-0 = <&mmc0_pins_default>;
162 pinctrl-1 = <&mmc0_pins_uhs>;
163 bus-width = <4>;
164 max-frequency = <52000000>;
165 cap-sd-highspeed;
166 vmmc-supply = <&reg_3p3v>;
167 vqmmc-supply = <&reg_3p3v>;
168 status = "okay";
169};
170
171&pio {
172 mmc0_pins_default: mmc0-pins-22-to-32-default {
173 mux {
174 function = "flash";
175 groups = "emmc_45";
176 };
177
178 conf-cmd-dat {
179 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
180 "SPI0_CS", "SPI0_HOLD", "SPI0_WP",
181 "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
182 input-enable;
183 drive-strength = <MTK_DRIVE_4mA>;
184 mediatek,pull-up-adv = <1>; /* pull-up 10K */
185 };
186
187 conf-clk {
188 pins = "SPI1_CS";
189 drive-strength = <MTK_DRIVE_6mA>;
190 mediatek,pull-down-adv = <2>; /* pull-down 50K */
191 };
192
193 conf-rst {
194 pins = "PWM1";
195 drive-strength = <MTK_DRIVE_4mA>;
196 mediatek,pull-up-adv = <1>; /* pull-up 10K */
197 };
198 };
199
200 mmc0_pins_uhs: mmc0-pins-22-to-32-uhs {
201 mux {
202 function = "flash";
203 groups = "emmc_45";
204 };
205
206 conf-cmd-dat {
207 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
208 "SPI0_CS", "SPI0_HOLD", "SPI0_WP",
209 "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
210 input-enable;
211 drive-strength = <MTK_DRIVE_4mA>;
212 mediatek,pull-up-adv = <1>; /* pull-up 10K */
213 };
214
215 conf-clk {
216 pins = "SPI1_CS";
217 drive-strength = <MTK_DRIVE_6mA>;
218 mediatek,pull-down-adv = <2>; /* pull-down 50K */
219 };
220
221 conf-rst {
222 pins = "PWM1";
223 drive-strength = <MTK_DRIVE_4mA>;
224 mediatek,pull-up-adv = <1>; /* pull-up 10K */
225 };
226 };
227
228 wf_2g_5g_pins: wf_2g_5g-pins {
229 mux {
230 function = "wifi";
231 groups = "wf_2g", "wf_5g";
232 };
233 conf {
234 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
235 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
236 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
237 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
238 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
239 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
240 "WF1_TOP_CLK", "WF1_TOP_DATA";
241 drive-strength = <MTK_DRIVE_4mA>;
242 };
243 };
244
245 wf_dbdc_pins: wf_dbdc-pins {
246 mux {
247 function = "wifi";
248 groups = "wf_dbdc";
249 };
250 conf {
251 pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
252 "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
253 "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
254 "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
255 "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
256 "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
257 "WF1_TOP_CLK", "WF1_TOP_DATA";
258 drive-strength = <MTK_DRIVE_4mA>;
259 };
260 };
261};