developer | 9516570 | 2023-12-14 10:47:09 +0800 | [diff] [blame] | 1 | From d76914437a405265b298b7b01235a7304634c567 Mon Sep 17 00:00:00 2001 |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 2 | From: Bo Jiao <Bo.Jiao@mediatek.com> |
developer | 58aa068 | 2023-09-18 14:02:26 +0800 | [diff] [blame] | 3 | Date: Mon, 18 Sep 2023 11:01:55 +0800 |
developer | 9516570 | 2023-12-14 10:47:09 +0800 | [diff] [blame] | 4 | Subject: [PATCH] add-wed-tx-support-for-mt7986 |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 5 | |
| 6 | --- |
developer | 9516570 | 2023-12-14 10:47:09 +0800 | [diff] [blame] | 7 | arch/arm64/boot/dts/mediatek/mt7981.dtsi | 1 + |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 8 | arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 2 + |
| 9 | arch/arm64/boot/dts/mediatek/mt7986b.dtsi | 2 + |
developer | 0158738 | 2023-08-24 14:46:09 +0800 | [diff] [blame] | 10 | drivers/net/ethernet/mediatek/mtk_eth_soc.c | 17 +- |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 11 | drivers/net/ethernet/mediatek/mtk_eth_soc.h | 5 + |
developer | 9516570 | 2023-12-14 10:47:09 +0800 | [diff] [blame] | 12 | drivers/net/ethernet/mediatek/mtk_wed.c | 498 +++++++++++++----- |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 13 | drivers/net/ethernet/mediatek/mtk_wed.h | 18 +- |
| 14 | .../net/ethernet/mediatek/mtk_wed_debugfs.c | 3 + |
developer | 0158738 | 2023-08-24 14:46:09 +0800 | [diff] [blame] | 15 | drivers/net/ethernet/mediatek/mtk_wed_regs.h | 130 ++++- |
developer | 58aa068 | 2023-09-18 14:02:26 +0800 | [diff] [blame] | 16 | include/linux/soc/mediatek/mtk_wed.h | 23 + |
developer | 9516570 | 2023-12-14 10:47:09 +0800 | [diff] [blame] | 17 | 10 files changed, 549 insertions(+), 150 deletions(-) |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 18 | |
developer | 9516570 | 2023-12-14 10:47:09 +0800 | [diff] [blame] | 19 | diff --git a/arch/arm64/boot/dts/mediatek/mt7981.dtsi b/arch/arm64/boot/dts/mediatek/mt7981.dtsi |
| 20 | index e1b9b2c..3e0d2c0 100644 |
| 21 | --- a/arch/arm64/boot/dts/mediatek/mt7981.dtsi |
| 22 | +++ b/arch/arm64/boot/dts/mediatek/mt7981.dtsi |
| 23 | @@ -96,6 +96,7 @@ |
| 24 | reg = <0 0x15010000 0 0x1000>; |
| 25 | interrupt-parent = <&gic>; |
| 26 | interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; |
| 27 | + mediatek,wed_pcie = <&wed_pcie>; |
| 28 | }; |
| 29 | |
| 30 | ap2woccif: ap2woccif@151A5000 { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 31 | diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi |
developer | 9516570 | 2023-12-14 10:47:09 +0800 | [diff] [blame] | 32 | index 7e3101c..e9756bd 100644 |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 33 | --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi |
| 34 | +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi |
| 35 | @@ -64,6 +64,7 @@ |
| 36 | reg = <0 0x15010000 0 0x1000>; |
| 37 | interrupt-parent = <&gic>; |
| 38 | interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; |
| 39 | + mediatek,wed_pcie = <&wed_pcie>; |
| 40 | }; |
| 41 | |
| 42 | wed1: wed@15011000 { |
| 43 | @@ -72,6 +73,7 @@ |
| 44 | reg = <0 0x15011000 0 0x1000>; |
| 45 | interrupt-parent = <&gic>; |
| 46 | interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| 47 | + mediatek,wed_pcie = <&wed_pcie>; |
| 48 | }; |
| 49 | |
| 50 | ap2woccif: ap2woccif@151A5000 { |
| 51 | diff --git a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi |
developer | 9516570 | 2023-12-14 10:47:09 +0800 | [diff] [blame] | 52 | index a780cfb..eafe314 100644 |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 53 | --- a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi |
| 54 | +++ b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi |
| 55 | @@ -64,6 +64,7 @@ |
| 56 | reg = <0 0x15010000 0 0x1000>; |
| 57 | interrupt-parent = <&gic>; |
| 58 | interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; |
| 59 | + mediatek,wed_pcie = <&wed_pcie>; |
| 60 | }; |
| 61 | |
| 62 | wed1: wed@15011000 { |
| 63 | @@ -72,6 +73,7 @@ |
| 64 | reg = <0 0x15011000 0 0x1000>; |
| 65 | interrupt-parent = <&gic>; |
| 66 | interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| 67 | + mediatek,wed_pcie = <&wed_pcie>; |
| 68 | }; |
| 69 | |
| 70 | ap2woccif: ap2woccif@151A5000 { |
| 71 | diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c |
developer | 9516570 | 2023-12-14 10:47:09 +0800 | [diff] [blame] | 72 | index 3685926..51fe4b3 100644 |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 73 | --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c |
| 74 | +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c |
developer | 9516570 | 2023-12-14 10:47:09 +0800 | [diff] [blame] | 75 | @@ -5091,6 +5091,7 @@ static int mtk_probe(struct platform_device *pdev) |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 76 | { |
developer | 58aa068 | 2023-09-18 14:02:26 +0800 | [diff] [blame] | 77 | struct device_node *mac_np, *mux_np; |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 78 | struct mtk_eth *eth; |
developer | f50c180 | 2022-07-05 20:35:53 +0800 | [diff] [blame] | 79 | + struct resource *res = NULL; |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 80 | int err, i; |
| 81 | |
| 82 | eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); |
developer | 9516570 | 2023-12-14 10:47:09 +0800 | [diff] [blame] | 83 | @@ -5111,13 +5112,12 @@ static int mtk_probe(struct platform_device *pdev) |
developer | 0158738 | 2023-08-24 14:46:09 +0800 | [diff] [blame] | 84 | return PTR_ERR(eth->sram_base); |
| 85 | } |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 86 | |
developer | 0158738 | 2023-08-24 14:46:09 +0800 | [diff] [blame] | 87 | - if(eth->soc->has_sram) { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 88 | - struct resource *res; |
developer | 0158738 | 2023-08-24 14:46:09 +0800 | [diff] [blame] | 89 | - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 90 | - if (unlikely(!res)) |
| 91 | - return -EINVAL; |
| 92 | + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 93 | + if (unlikely(!res)) |
| 94 | + return -EINVAL; |
| 95 | + |
| 96 | + if(eth->soc->has_sram) |
| 97 | eth->phy_scratch_ring = res->start + MTK_ETH_SRAM_OFFSET; |
| 98 | - } |
| 99 | |
| 100 | mtk_get_hwver(eth); |
| 101 | |
developer | 9516570 | 2023-12-14 10:47:09 +0800 | [diff] [blame] | 102 | @@ -5213,12 +5213,15 @@ static int mtk_probe(struct platform_device *pdev) |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 103 | MTK_WDMA1_BASE |
| 104 | }; |
| 105 | void __iomem *wdma; |
| 106 | + u32 wdma_phy; |
| 107 | |
| 108 | if (!np || i >= ARRAY_SIZE(wdma_regs)) |
| 109 | break; |
| 110 | |
| 111 | wdma = eth->base + wdma_regs[i]; |
| 112 | - mtk_wed_add_hw(np, eth, wdma, i); |
developer | 0158738 | 2023-08-24 14:46:09 +0800 | [diff] [blame] | 113 | + wdma_phy = res->start + wdma_regs[i]; |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 114 | + |
| 115 | + mtk_wed_add_hw(np, eth, wdma, wdma_phy, i); |
| 116 | } |
| 117 | |
developer | 9516570 | 2023-12-14 10:47:09 +0800 | [diff] [blame] | 118 | if (MTK_HAS_CAPS(eth->soc->caps, MTK_PDMA_INT)) { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 119 | diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h |
developer | 9516570 | 2023-12-14 10:47:09 +0800 | [diff] [blame] | 120 | index b714c27..e9d88f1 100644 |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 121 | --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h |
| 122 | +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h |
developer | 9516570 | 2023-12-14 10:47:09 +0800 | [diff] [blame] | 123 | @@ -593,8 +593,13 @@ |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 124 | #define RX_DMA_SPORT_MASK 0x7 |
developer | 58aa068 | 2023-09-18 14:02:26 +0800 | [diff] [blame] | 125 | #define RX_DMA_SPORT_MASK_V2 0xf |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 126 | |
| 127 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 128 | +#define MTK_WDMA0_BASE 0x4800 |
| 129 | +#define MTK_WDMA1_BASE 0x4c00 |
| 130 | +#else |
| 131 | #define MTK_WDMA0_BASE 0x2800 |
| 132 | #define MTK_WDMA1_BASE 0x2c00 |
| 133 | +#endif |
| 134 | |
| 135 | /* QDMA descriptor txd4 */ |
| 136 | #define TX_DMA_CHKSUM (0x7 << 29) |
| 137 | diff --git a/drivers/net/ethernet/mediatek/mtk_wed.c b/drivers/net/ethernet/mediatek/mtk_wed.c |
developer | 9516570 | 2023-12-14 10:47:09 +0800 | [diff] [blame] | 138 | index ea1cbdf..948f013 100644 |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 139 | --- a/drivers/net/ethernet/mediatek/mtk_wed.c |
| 140 | +++ b/drivers/net/ethernet/mediatek/mtk_wed.c |
| 141 | @@ -18,15 +18,6 @@ |
| 142 | #include "mtk_wed.h" |
| 143 | #include "mtk_ppe.h" |
| 144 | |
| 145 | -#define MTK_PCIE_BASE(n) (0x1a143000 + (n) * 0x2000) |
| 146 | - |
| 147 | -#define MTK_WED_PKT_SIZE 1900 |
| 148 | -#define MTK_WED_BUF_SIZE 2048 |
| 149 | -#define MTK_WED_BUF_PER_PAGE (PAGE_SIZE / 2048) |
| 150 | - |
| 151 | -#define MTK_WED_TX_RING_SIZE 2048 |
| 152 | -#define MTK_WED_WDMA_RING_SIZE 1024 |
| 153 | - |
| 154 | static struct mtk_wed_hw *hw_list[2]; |
| 155 | static DEFINE_MUTEX(hw_lock); |
| 156 | |
| 157 | @@ -80,14 +71,19 @@ mtk_wed_reset(struct mtk_wed_device *dev, u32 mask) |
| 158 | static struct mtk_wed_hw * |
| 159 | mtk_wed_assign(struct mtk_wed_device *dev) |
| 160 | { |
| 161 | - struct mtk_wed_hw *hw; |
| 162 | + int i; |
| 163 | + |
| 164 | + for (i = 0; i < ARRAY_SIZE(hw_list); i++) { |
| 165 | + struct mtk_wed_hw *hw = hw_list[i]; |
| 166 | + |
| 167 | + if (!hw || hw->wed_dev) |
| 168 | + continue; |
| 169 | |
| 170 | - hw = hw_list[pci_domain_nr(dev->wlan.pci_dev->bus)]; |
| 171 | - if (!hw || hw->wed_dev) |
| 172 | - return NULL; |
| 173 | + hw->wed_dev = dev; |
| 174 | + return hw; |
| 175 | + } |
| 176 | |
| 177 | - hw->wed_dev = dev; |
| 178 | - return hw; |
| 179 | + return NULL; |
| 180 | } |
| 181 | |
| 182 | static int |
| 183 | @@ -96,19 +92,27 @@ mtk_wed_buffer_alloc(struct mtk_wed_device *dev) |
| 184 | struct mtk_wdma_desc *desc; |
| 185 | dma_addr_t desc_phys; |
| 186 | void **page_list; |
| 187 | + u32 last_seg = MTK_WDMA_DESC_CTRL_LAST_SEG1; |
| 188 | int token = dev->wlan.token_start; |
| 189 | - int ring_size; |
| 190 | - int n_pages; |
| 191 | - int i, page_idx; |
| 192 | + int ring_size, n_pages, page_idx; |
| 193 | + int i; |
| 194 | + |
| 195 | + |
| 196 | + if (dev->ver == MTK_WED_V1) { |
| 197 | + ring_size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1); |
| 198 | + } else { |
| 199 | + ring_size = MTK_WED_VLD_GROUP_SIZE * MTK_WED_PER_GROUP_PKT + |
| 200 | + MTK_WED_WDMA_RING_SIZE * 2; |
| 201 | + last_seg = MTK_WDMA_DESC_CTRL_LAST_SEG0; |
| 202 | + } |
| 203 | |
| 204 | - ring_size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1); |
| 205 | n_pages = ring_size / MTK_WED_BUF_PER_PAGE; |
| 206 | |
| 207 | page_list = kcalloc(n_pages, sizeof(*page_list), GFP_KERNEL); |
| 208 | if (!page_list) |
| 209 | return -ENOMEM; |
| 210 | |
| 211 | - dev->buf_ring.size = ring_size; |
| 212 | + dev->buf_ring.size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1); |
| 213 | dev->buf_ring.pages = page_list; |
| 214 | |
| 215 | desc = dma_alloc_coherent(dev->hw->dev, ring_size * sizeof(*desc), |
| 216 | @@ -154,7 +158,7 @@ mtk_wed_buffer_alloc(struct mtk_wed_device *dev) |
| 217 | txd_size) | |
| 218 | FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1, |
| 219 | MTK_WED_BUF_SIZE - txd_size) | |
| 220 | - MTK_WDMA_DESC_CTRL_LAST_SEG1; |
| 221 | + last_seg; |
| 222 | desc->info = 0; |
| 223 | desc++; |
| 224 | |
developer | 58aa068 | 2023-09-18 14:02:26 +0800 | [diff] [blame] | 225 | @@ -202,12 +206,12 @@ mtk_wed_free_buffer(struct mtk_wed_device *dev) |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 226 | } |
| 227 | |
| 228 | static void |
| 229 | -mtk_wed_free_ring(struct mtk_wed_device *dev, struct mtk_wed_ring *ring) |
| 230 | +mtk_wed_free_ring(struct mtk_wed_device *dev, struct mtk_wed_ring *ring, int scale) |
| 231 | { |
| 232 | if (!ring->desc) |
| 233 | return; |
| 234 | |
| 235 | - dma_free_coherent(dev->hw->dev, ring->size * sizeof(*ring->desc), |
| 236 | + dma_free_coherent(dev->hw->dev, ring->size * sizeof(*ring->desc) * scale, |
| 237 | ring->desc, ring->desc_phys); |
| 238 | } |
| 239 | |
| 240 | @@ -217,9 +221,69 @@ mtk_wed_free_tx_rings(struct mtk_wed_device *dev) |
| 241 | int i; |
| 242 | |
| 243 | for (i = 0; i < ARRAY_SIZE(dev->tx_ring); i++) |
| 244 | - mtk_wed_free_ring(dev, &dev->tx_ring[i]); |
| 245 | + mtk_wed_free_ring(dev, &dev->tx_ring[i], 1); |
| 246 | for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++) |
| 247 | - mtk_wed_free_ring(dev, &dev->tx_wdma[i]); |
| 248 | + mtk_wed_free_ring(dev, &dev->tx_wdma[i], dev->ver); |
| 249 | +} |
| 250 | + |
| 251 | +static void |
| 252 | +mtk_wed_set_int(struct mtk_wed_device *dev, u32 irq_mask) |
| 253 | +{ |
| 254 | + u32 wdma_mask; |
| 255 | + |
| 256 | + wdma_mask = FIELD_PREP(MTK_WDMA_INT_MASK_RX_DONE, GENMASK(1, 0)); |
| 257 | + |
| 258 | + /* wed control cr set */ |
| 259 | + wed_set(dev, MTK_WED_CTRL, |
| 260 | + MTK_WED_CTRL_WDMA_INT_AGENT_EN | |
| 261 | + MTK_WED_CTRL_WPDMA_INT_AGENT_EN | |
| 262 | + MTK_WED_CTRL_WED_TX_BM_EN | |
| 263 | + MTK_WED_CTRL_WED_TX_FREE_AGENT_EN); |
| 264 | + |
| 265 | + if (dev->ver == MTK_WED_V1) { |
| 266 | + wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, |
| 267 | + MTK_WED_PCIE_INT_TRIGGER_STATUS); |
| 268 | + |
| 269 | + wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, |
| 270 | + MTK_WED_WPDMA_INT_TRIGGER_RX_DONE | |
| 271 | + MTK_WED_WPDMA_INT_TRIGGER_TX_DONE); |
| 272 | + |
| 273 | + wed_set(dev, MTK_WED_WPDMA_INT_CTRL, |
| 274 | + MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV); |
| 275 | + } else { |
| 276 | + /* initail tx interrupt trigger */ |
| 277 | + wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX, |
| 278 | + MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN | |
| 279 | + MTK_WED_WPDMA_INT_CTRL_TX0_DONE_CLR | |
| 280 | + MTK_WED_WPDMA_INT_CTRL_TX1_DONE_EN | |
| 281 | + MTK_WED_WPDMA_INT_CTRL_TX1_DONE_CLR | |
| 282 | + FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX0_DONE_TRIG, |
| 283 | + dev->wlan.tx_tbit[0]) | |
| 284 | + FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX1_DONE_TRIG, |
| 285 | + dev->wlan.tx_tbit[1])); |
| 286 | + |
| 287 | + /* initail txfree interrupt trigger */ |
| 288 | + wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX_FREE, |
| 289 | + MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_EN | |
| 290 | + MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_CLR | |
| 291 | + FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG, |
| 292 | + dev->wlan.txfree_tbit)); |
| 293 | + } |
| 294 | + /* initail wdma interrupt agent */ |
| 295 | + wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, wdma_mask); |
| 296 | + if (dev->ver == MTK_WED_V1) { |
| 297 | + wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask); |
| 298 | + } else { |
| 299 | + wed_w32(dev, MTK_WED_WDMA_INT_CLR, wdma_mask); |
| 300 | + wed_set(dev, MTK_WED_WDMA_INT_CTRL, |
| 301 | + FIELD_PREP(MTK_WED_WDMA_INT_POLL_SRC_SEL,dev->wdma_idx)); |
| 302 | + |
| 303 | + } |
| 304 | + |
| 305 | + wdma_w32(dev, MTK_WDMA_INT_MASK, wdma_mask); |
| 306 | + wdma_w32(dev, MTK_WDMA_INT_GRP2, wdma_mask); |
| 307 | + wed_w32(dev, MTK_WED_WPDMA_INT_MASK, irq_mask); |
| 308 | + wed_w32(dev, MTK_WED_INT_MASK, irq_mask); |
| 309 | } |
| 310 | |
| 311 | static void |
| 312 | @@ -234,10 +298,95 @@ mtk_wed_set_ext_int(struct mtk_wed_device *dev, bool en) |
| 313 | wed_r32(dev, MTK_WED_EXT_INT_MASK); |
| 314 | } |
| 315 | |
| 316 | +static void |
| 317 | +mtk_wed_set_512_support(struct mtk_wed_device *dev, bool en) |
| 318 | +{ |
| 319 | + if (en) { |
| 320 | + wed_w32(dev, MTK_WED_TXDP_CTRL, MTK_WED_TXDP_DW9_OVERWR); |
| 321 | + wed_w32(dev, MTK_WED_TXP_DW1, |
| 322 | + FIELD_PREP(MTK_WED_WPDMA_WRITE_TXP, 0x0103)); |
| 323 | + } else { |
| 324 | + wed_w32(dev, MTK_WED_TXP_DW1, |
| 325 | + FIELD_PREP(MTK_WED_WPDMA_WRITE_TXP, 0x0100)); |
| 326 | + wed_clr(dev, MTK_WED_TXDP_CTRL, MTK_WED_TXDP_DW9_OVERWR); |
| 327 | + } |
| 328 | +} |
| 329 | + |
| 330 | +static void |
| 331 | +mtk_wed_dma_enable(struct mtk_wed_device *dev) |
| 332 | +{ |
| 333 | + wed_set(dev, MTK_WED_WPDMA_INT_CTRL, |
| 334 | + MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV); |
| 335 | + |
| 336 | + wed_set(dev, MTK_WED_GLO_CFG, |
| 337 | + MTK_WED_GLO_CFG_TX_DMA_EN | |
| 338 | + MTK_WED_GLO_CFG_RX_DMA_EN); |
| 339 | + wed_set(dev, MTK_WED_WPDMA_GLO_CFG, |
| 340 | + MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN | |
| 341 | + MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN); |
| 342 | + wed_set(dev, MTK_WED_WDMA_GLO_CFG, |
| 343 | + MTK_WED_WDMA_GLO_CFG_RX_DRV_EN); |
| 344 | + |
| 345 | + wdma_set(dev, MTK_WDMA_GLO_CFG, |
| 346 | + MTK_WDMA_GLO_CFG_TX_DMA_EN | |
| 347 | + MTK_WDMA_GLO_CFG_RX_INFO1_PRERES | |
| 348 | + MTK_WDMA_GLO_CFG_RX_INFO2_PRERES); |
| 349 | + |
| 350 | + if (dev->ver == MTK_WED_V1) { |
| 351 | + wdma_set(dev, MTK_WDMA_GLO_CFG, |
| 352 | + MTK_WDMA_GLO_CFG_RX_INFO3_PRERES); |
| 353 | + } else { |
| 354 | + wed_set(dev, MTK_WED_WPDMA_CTRL, |
| 355 | + MTK_WED_WPDMA_CTRL_SDL1_FIXED); |
| 356 | + |
| 357 | + wed_set(dev, MTK_WED_WPDMA_GLO_CFG, |
| 358 | + MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC | |
| 359 | + MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC); |
| 360 | + |
| 361 | + wed_clr(dev, MTK_WED_WPDMA_GLO_CFG, |
| 362 | + MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP | |
| 363 | + MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV); |
| 364 | + } |
| 365 | +} |
| 366 | + |
| 367 | +static void |
| 368 | +mtk_wed_dma_disable(struct mtk_wed_device *dev) |
| 369 | +{ |
| 370 | + wed_clr(dev, MTK_WED_WPDMA_GLO_CFG, |
| 371 | + MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN | |
| 372 | + MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN); |
| 373 | + |
| 374 | + wed_clr(dev, MTK_WED_WDMA_GLO_CFG, |
| 375 | + MTK_WED_WDMA_GLO_CFG_RX_DRV_EN); |
| 376 | + |
| 377 | + wed_clr(dev, MTK_WED_GLO_CFG, |
| 378 | + MTK_WED_GLO_CFG_TX_DMA_EN | |
| 379 | + MTK_WED_GLO_CFG_RX_DMA_EN); |
| 380 | + |
| 381 | + wdma_m32(dev, MTK_WDMA_GLO_CFG, |
| 382 | + MTK_WDMA_GLO_CFG_TX_DMA_EN | |
| 383 | + MTK_WDMA_GLO_CFG_RX_INFO1_PRERES | |
| 384 | + MTK_WDMA_GLO_CFG_RX_INFO2_PRERES, 0); |
| 385 | + |
| 386 | + if (dev->ver == MTK_WED_V1) { |
| 387 | + regmap_write(dev->hw->mirror, dev->hw->index * 4, 0); |
| 388 | + wdma_m32(dev, MTK_WDMA_GLO_CFG, |
| 389 | + MTK_WDMA_GLO_CFG_RX_INFO3_PRERES, 0); |
| 390 | + } else { |
| 391 | + wed_clr(dev, MTK_WED_WPDMA_GLO_CFG, |
| 392 | + MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC | |
| 393 | + MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC); |
| 394 | + } |
| 395 | +} |
| 396 | + |
| 397 | static void |
| 398 | mtk_wed_stop(struct mtk_wed_device *dev) |
| 399 | { |
| 400 | - regmap_write(dev->hw->mirror, dev->hw->index * 4, 0); |
| 401 | + mtk_wed_dma_disable(dev); |
| 402 | + |
| 403 | + if (dev->ver > MTK_WED_V1) |
| 404 | + mtk_wed_set_512_support(dev, false); |
| 405 | + |
| 406 | mtk_wed_set_ext_int(dev, false); |
| 407 | |
| 408 | wed_clr(dev, MTK_WED_CTRL, |
| 409 | @@ -245,26 +394,18 @@ mtk_wed_stop(struct mtk_wed_device *dev) |
| 410 | MTK_WED_CTRL_WPDMA_INT_AGENT_EN | |
| 411 | MTK_WED_CTRL_WED_TX_BM_EN | |
| 412 | MTK_WED_CTRL_WED_TX_FREE_AGENT_EN); |
| 413 | + |
| 414 | wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0); |
| 415 | wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0); |
| 416 | wdma_w32(dev, MTK_WDMA_INT_MASK, 0); |
| 417 | wdma_w32(dev, MTK_WDMA_INT_GRP2, 0); |
| 418 | wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0); |
| 419 | - |
| 420 | - wed_clr(dev, MTK_WED_GLO_CFG, |
| 421 | - MTK_WED_GLO_CFG_TX_DMA_EN | |
| 422 | - MTK_WED_GLO_CFG_RX_DMA_EN); |
| 423 | - wed_clr(dev, MTK_WED_WPDMA_GLO_CFG, |
| 424 | - MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN | |
| 425 | - MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN); |
| 426 | - wed_clr(dev, MTK_WED_WDMA_GLO_CFG, |
| 427 | - MTK_WED_WDMA_GLO_CFG_RX_DRV_EN); |
| 428 | } |
| 429 | |
| 430 | static void |
| 431 | mtk_wed_detach(struct mtk_wed_device *dev) |
| 432 | { |
| 433 | - struct device_node *wlan_node = dev->wlan.pci_dev->dev.of_node; |
| 434 | + struct device_node *wlan_node; |
| 435 | struct mtk_wed_hw *hw = dev->hw; |
| 436 | |
| 437 | mutex_lock(&hw_lock); |
developer | 9516570 | 2023-12-14 10:47:09 +0800 | [diff] [blame] | 438 | @@ -279,11 +420,14 @@ mtk_wed_detach(struct mtk_wed_device *dev) |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 439 | mtk_wed_free_buffer(dev); |
| 440 | mtk_wed_free_tx_rings(dev); |
| 441 | |
| 442 | - if (of_dma_is_coherent(wlan_node)) |
| 443 | - regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP, |
| 444 | - BIT(hw->index), BIT(hw->index)); |
| 445 | + if (dev->wlan.bus_type == MTK_BUS_TYPE_PCIE) { |
| 446 | + wlan_node = dev->wlan.pci_dev->dev.of_node; |
| 447 | + if (of_dma_is_coherent(wlan_node)) |
| 448 | + regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP, |
| 449 | + BIT(hw->index), BIT(hw->index)); |
| 450 | + } |
| 451 | |
developer | 9516570 | 2023-12-14 10:47:09 +0800 | [diff] [blame] | 452 | - if (!hw_list[!hw->index]->wed_dev && |
| 453 | + if ((!hw_list[!hw->index] || !hw_list[!hw->index]->wed_dev) && |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 454 | hw->eth->dma_dev != hw->eth->dev) |
developer | 9516570 | 2023-12-14 10:47:09 +0800 | [diff] [blame] | 455 | mtk_eth_set_dma_device(hw->eth, hw->eth->dev); |
| 456 | |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 457 | @@ -294,15 +438,87 @@ mtk_wed_detach(struct mtk_wed_device *dev) |
| 458 | mutex_unlock(&hw_lock); |
| 459 | } |
| 460 | |
| 461 | +static void |
| 462 | +mtk_wed_bus_init(struct mtk_wed_device *dev) |
| 463 | +{ |
| 464 | +#define PCIE_BASE_ADDR0 0x11280000 |
| 465 | + |
| 466 | + if (dev->wlan.bus_type == MTK_BUS_TYPE_PCIE) { |
| 467 | + struct device_node *node; |
| 468 | + void __iomem * base_addr; |
| 469 | + u32 value = 0; |
| 470 | + |
| 471 | + node = of_parse_phandle(dev->hw->node, "mediatek,wed_pcie", 0); |
| 472 | + if (!node) { |
| 473 | + pr_err("%s: no wed_pcie node\n", __func__); |
| 474 | + return; |
| 475 | + } |
| 476 | + |
| 477 | + base_addr = of_iomap(node, 0); |
| 478 | + |
| 479 | + value = readl(base_addr); |
| 480 | + value |= BIT(0); |
| 481 | + writel(value, base_addr); |
| 482 | + |
| 483 | + wed_w32(dev, MTK_WED_PCIE_INT_CTRL, |
| 484 | + FIELD_PREP(MTK_WED_PCIE_INT_CTRL_POLL_EN, 2)); |
| 485 | + |
| 486 | + /* pcie interrupt control: pola/source selection */ |
| 487 | + wed_set(dev, MTK_WED_PCIE_INT_CTRL, |
| 488 | + MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA | |
| 489 | + FIELD_PREP(MTK_WED_PCIE_INT_CTRL_SRC_SEL, 1)); |
| 490 | + wed_r32(dev, MTK_WED_PCIE_INT_CTRL); |
| 491 | + |
| 492 | + value = wed_r32(dev, MTK_WED_PCIE_CFG_INTM); |
| 493 | + value = wed_r32(dev, MTK_WED_PCIE_CFG_BASE); |
| 494 | + wed_w32(dev, MTK_WED_PCIE_CFG_INTM, PCIE_BASE_ADDR0 | 0x180); |
| 495 | + wed_w32(dev, MTK_WED_PCIE_CFG_BASE, PCIE_BASE_ADDR0 | 0x184); |
| 496 | + |
| 497 | + value = wed_r32(dev, MTK_WED_PCIE_CFG_INTM); |
| 498 | + value = wed_r32(dev, MTK_WED_PCIE_CFG_BASE); |
| 499 | + |
| 500 | + /* pcie interrupt status trigger register */ |
| 501 | + wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(24)); |
| 502 | + wed_r32(dev, MTK_WED_PCIE_INT_TRIGGER); |
| 503 | + |
| 504 | + /* pola setting */ |
| 505 | + value = wed_r32(dev, MTK_WED_PCIE_INT_CTRL); |
| 506 | + wed_set(dev, MTK_WED_PCIE_INT_CTRL, |
| 507 | + MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA); |
| 508 | + } else if (dev->wlan.bus_type == MTK_BUS_TYPE_AXI) { |
| 509 | + wed_set(dev, MTK_WED_WPDMA_INT_CTRL, |
| 510 | + MTK_WED_WPDMA_INT_CTRL_SIG_SRC | |
| 511 | + FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_SRC_SEL, 0)); |
| 512 | + } |
| 513 | + return; |
| 514 | +} |
| 515 | + |
| 516 | +static void |
| 517 | +mtk_wed_set_wpdma(struct mtk_wed_device *dev) |
| 518 | +{ |
| 519 | + if (dev->ver > MTK_WED_V1) { |
| 520 | + wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_int); |
| 521 | + wed_w32(dev, MTK_WED_WPDMA_CFG_INT_MASK, dev->wlan.wpdma_mask); |
| 522 | + wed_w32(dev, MTK_WED_WPDMA_CFG_TX, dev->wlan.wpdma_tx); |
| 523 | + wed_w32(dev, MTK_WED_WPDMA_CFG_TX_FREE, dev->wlan.wpdma_txfree); |
| 524 | + } else { |
| 525 | + wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys); |
| 526 | + } |
| 527 | +} |
| 528 | + |
| 529 | static void |
| 530 | mtk_wed_hw_init_early(struct mtk_wed_device *dev) |
| 531 | { |
| 532 | u32 mask, set; |
| 533 | - u32 offset; |
| 534 | |
| 535 | mtk_wed_stop(dev); |
| 536 | mtk_wed_reset(dev, MTK_WED_RESET_WED); |
| 537 | |
| 538 | + if (dev->ver > MTK_WED_V1) |
| 539 | + mtk_wed_bus_init(dev); |
| 540 | + |
| 541 | + mtk_wed_set_wpdma(dev); |
| 542 | + |
| 543 | mask = MTK_WED_WDMA_GLO_CFG_BT_SIZE | |
| 544 | MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE | |
| 545 | MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE; |
| 546 | @@ -311,30 +527,54 @@ mtk_wed_hw_init_early(struct mtk_wed_device *dev) |
| 547 | MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY; |
| 548 | wed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set); |
| 549 | |
| 550 | - wdma_set(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_RX_INFO_PRERES); |
| 551 | + if (dev->ver == MTK_WED_V1) { |
| 552 | + u32 offset; |
| 553 | + offset = dev->hw->index ? 0x04000400 : 0; |
| 554 | + wed_w32(dev, MTK_WED_WDMA_OFFSET0, 0x2a042a20 + offset); |
| 555 | + wed_w32(dev, MTK_WED_WDMA_OFFSET1, 0x29002800 + offset); |
| 556 | |
| 557 | - offset = dev->hw->index ? 0x04000400 : 0; |
| 558 | - wed_w32(dev, MTK_WED_WDMA_OFFSET0, 0x2a042a20 + offset); |
| 559 | - wed_w32(dev, MTK_WED_WDMA_OFFSET1, 0x29002800 + offset); |
| 560 | + wed_w32(dev, MTK_WED_PCIE_CFG_BASE, MTK_PCIE_BASE(dev->hw->index)); |
| 561 | + } else { |
| 562 | + wed_w32(dev, MTK_WED_WDMA_CFG_BASE, dev->hw->wdma_phy); |
| 563 | + wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_ETH_DMAD_FMT); |
| 564 | + wed_w32(dev, MTK_WED_WDMA_OFFSET0, |
| 565 | + FIELD_PREP(MTK_WED_WDMA_OFST0_GLO_INTS, |
| 566 | + MTK_WDMA_INT_STATUS) | |
| 567 | + FIELD_PREP(MTK_WED_WDMA_OFST0_GLO_CFG, |
| 568 | + MTK_WDMA_GLO_CFG)); |
| 569 | + |
| 570 | + wed_w32(dev, MTK_WED_WDMA_OFFSET1, |
| 571 | + FIELD_PREP(MTK_WED_WDMA_OFST1_TX_CTRL, |
| 572 | + MTK_WDMA_RING_TX(0)) | |
| 573 | + FIELD_PREP(MTK_WED_WDMA_OFST1_RX_CTRL, |
| 574 | + MTK_WDMA_RING_RX(0))); |
| 575 | + } |
| 576 | |
| 577 | - wed_w32(dev, MTK_WED_PCIE_CFG_BASE, MTK_PCIE_BASE(dev->hw->index)); |
| 578 | - wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys); |
| 579 | } |
| 580 | |
| 581 | static void |
| 582 | mtk_wed_hw_init(struct mtk_wed_device *dev) |
| 583 | { |
| 584 | + int size = dev->buf_ring.size; |
| 585 | + int rev_size = MTK_WED_TX_RING_SIZE / 2; |
| 586 | + int thr = 1; |
| 587 | + |
| 588 | if (dev->init_done) |
| 589 | return; |
| 590 | |
| 591 | dev->init_done = true; |
| 592 | mtk_wed_set_ext_int(dev, false); |
| 593 | + |
| 594 | + if (dev->ver > MTK_WED_V1) { |
| 595 | + size = MTK_WED_WDMA_RING_SIZE * 2 + dev->buf_ring.size; |
| 596 | + rev_size = size; |
| 597 | + thr = 0; |
| 598 | + } |
| 599 | + |
| 600 | wed_w32(dev, MTK_WED_TX_BM_CTRL, |
| 601 | MTK_WED_TX_BM_CTRL_PAUSE | |
| 602 | - FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM, |
| 603 | - dev->buf_ring.size / 128) | |
| 604 | - FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM, |
| 605 | - MTK_WED_TX_RING_SIZE / 256)); |
| 606 | + FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM, size / 128) | |
| 607 | + FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM, rev_size / 128)); |
| 608 | |
| 609 | wed_w32(dev, MTK_WED_TX_BM_BASE, dev->buf_ring.desc_phys); |
| 610 | |
| 611 | @@ -347,28 +587,38 @@ mtk_wed_hw_init(struct mtk_wed_device *dev) |
| 612 | wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE); |
| 613 | |
| 614 | wed_w32(dev, MTK_WED_TX_BM_DYN_THR, |
| 615 | - FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO, 1) | |
| 616 | + FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO, thr) | |
| 617 | MTK_WED_TX_BM_DYN_THR_HI); |
| 618 | |
| 619 | + if (dev->ver > MTK_WED_V1) { |
| 620 | + wed_w32(dev, MTK_WED_TX_TKID_CTRL, |
| 621 | + MTK_WED_TX_TKID_CTRL_PAUSE | |
| 622 | + FIELD_PREP(MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM, |
| 623 | + dev->buf_ring.size / 128) | |
| 624 | + FIELD_PREP(MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM, |
| 625 | + dev->buf_ring.size / 128)); |
| 626 | + wed_w32(dev, MTK_WED_TX_TKID_DYN_THR, |
| 627 | + FIELD_PREP(MTK_WED_TX_TKID_DYN_THR_LO, 0) | |
| 628 | + MTK_WED_TX_TKID_DYN_THR_HI); |
| 629 | + } |
| 630 | mtk_wed_reset(dev, MTK_WED_RESET_TX_BM); |
| 631 | |
| 632 | - wed_set(dev, MTK_WED_CTRL, |
| 633 | - MTK_WED_CTRL_WED_TX_BM_EN | |
| 634 | - MTK_WED_CTRL_WED_TX_FREE_AGENT_EN); |
| 635 | - |
| 636 | wed_clr(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_PAUSE); |
| 637 | + if (dev->ver > MTK_WED_V1) |
| 638 | + wed_clr(dev, MTK_WED_TX_TKID_CTRL, MTK_WED_TX_TKID_CTRL_PAUSE); |
| 639 | } |
| 640 | |
| 641 | static void |
| 642 | -mtk_wed_ring_reset(struct mtk_wdma_desc *desc, int size) |
| 643 | +mtk_wed_ring_reset(struct mtk_wdma_desc *desc, int size, int scale) |
| 644 | { |
| 645 | int i; |
| 646 | |
| 647 | for (i = 0; i < size; i++) { |
| 648 | - desc[i].buf0 = 0; |
| 649 | - desc[i].ctrl = cpu_to_le32(MTK_WDMA_DESC_CTRL_DMA_DONE); |
| 650 | - desc[i].buf1 = 0; |
| 651 | - desc[i].info = 0; |
| 652 | + desc->buf0 = 0; |
| 653 | + desc->ctrl = cpu_to_le32(MTK_WDMA_DESC_CTRL_DMA_DONE); |
| 654 | + desc->buf1 = 0; |
| 655 | + desc->info = 0; |
| 656 | + desc += scale; |
| 657 | } |
| 658 | } |
| 659 | |
| 660 | @@ -424,7 +674,7 @@ mtk_wed_reset_dma(struct mtk_wed_device *dev) |
| 661 | if (!desc) |
| 662 | continue; |
| 663 | |
| 664 | - mtk_wed_ring_reset(desc, MTK_WED_TX_RING_SIZE); |
| 665 | + mtk_wed_ring_reset(desc, MTK_WED_TX_RING_SIZE, dev->ver); |
| 666 | } |
| 667 | |
| 668 | if (mtk_wed_poll_busy(dev)) |
| 669 | @@ -481,16 +731,16 @@ mtk_wed_reset_dma(struct mtk_wed_device *dev) |
| 670 | |
| 671 | static int |
| 672 | mtk_wed_ring_alloc(struct mtk_wed_device *dev, struct mtk_wed_ring *ring, |
| 673 | - int size) |
| 674 | + int size, int scale) |
| 675 | { |
| 676 | ring->desc = dma_alloc_coherent(dev->hw->dev, |
| 677 | - size * sizeof(*ring->desc), |
| 678 | + size * sizeof(*ring->desc) * scale, |
| 679 | &ring->desc_phys, GFP_KERNEL); |
| 680 | if (!ring->desc) |
| 681 | return -ENOMEM; |
| 682 | |
| 683 | ring->size = size; |
| 684 | - mtk_wed_ring_reset(ring->desc, size); |
| 685 | + mtk_wed_ring_reset(ring->desc, size, scale); |
| 686 | |
| 687 | return 0; |
| 688 | } |
| 689 | @@ -500,7 +750,7 @@ mtk_wed_wdma_ring_setup(struct mtk_wed_device *dev, int idx, int size) |
| 690 | { |
| 691 | struct mtk_wed_ring *wdma = &dev->tx_wdma[idx]; |
| 692 | |
| 693 | - if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE)) |
| 694 | + if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE, dev->ver)) |
| 695 | return -ENOMEM; |
| 696 | |
| 697 | wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE, |
| 698 | @@ -521,60 +771,36 @@ static void |
| 699 | mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask) |
| 700 | { |
| 701 | u32 wdma_mask; |
| 702 | - u32 val; |
| 703 | int i; |
| 704 | |
| 705 | for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++) |
| 706 | if (!dev->tx_wdma[i].desc) |
| 707 | mtk_wed_wdma_ring_setup(dev, i, 16); |
| 708 | |
| 709 | - wdma_mask = FIELD_PREP(MTK_WDMA_INT_MASK_RX_DONE, GENMASK(1, 0)); |
| 710 | |
| 711 | mtk_wed_hw_init(dev); |
| 712 | |
| 713 | - wed_set(dev, MTK_WED_CTRL, |
| 714 | - MTK_WED_CTRL_WDMA_INT_AGENT_EN | |
| 715 | - MTK_WED_CTRL_WPDMA_INT_AGENT_EN | |
| 716 | - MTK_WED_CTRL_WED_TX_BM_EN | |
| 717 | - MTK_WED_CTRL_WED_TX_FREE_AGENT_EN); |
| 718 | - |
| 719 | - wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, MTK_WED_PCIE_INT_TRIGGER_STATUS); |
developer | 58aa068 | 2023-09-18 14:02:26 +0800 | [diff] [blame] | 720 | - |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 721 | - wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, |
| 722 | - MTK_WED_WPDMA_INT_TRIGGER_RX_DONE | |
| 723 | - MTK_WED_WPDMA_INT_TRIGGER_TX_DONE); |
developer | 58aa068 | 2023-09-18 14:02:26 +0800 | [diff] [blame] | 724 | + mtk_wed_set_int(dev, irq_mask); |
| 725 | |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 726 | - wed_set(dev, MTK_WED_WPDMA_INT_CTRL, |
| 727 | - MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV); |
| 728 | - |
| 729 | - wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, wdma_mask); |
| 730 | - wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask); |
| 731 | - |
| 732 | - wdma_w32(dev, MTK_WDMA_INT_MASK, wdma_mask); |
| 733 | - wdma_w32(dev, MTK_WDMA_INT_GRP2, wdma_mask); |
| 734 | |
| 735 | - wed_w32(dev, MTK_WED_WPDMA_INT_MASK, irq_mask); |
| 736 | - wed_w32(dev, MTK_WED_INT_MASK, irq_mask); |
| 737 | + mtk_wed_set_ext_int(dev, true); |
| 738 | |
| 739 | - wed_set(dev, MTK_WED_GLO_CFG, |
| 740 | - MTK_WED_GLO_CFG_TX_DMA_EN | |
| 741 | - MTK_WED_GLO_CFG_RX_DMA_EN); |
| 742 | - wed_set(dev, MTK_WED_WPDMA_GLO_CFG, |
| 743 | - MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN | |
| 744 | - MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN); |
| 745 | - wed_set(dev, MTK_WED_WDMA_GLO_CFG, |
| 746 | - MTK_WED_WDMA_GLO_CFG_RX_DRV_EN); |
| 747 | + if (dev->ver == MTK_WED_V1) { |
| 748 | + u32 val; |
| 749 | |
| 750 | - mtk_wed_set_ext_int(dev, true); |
| 751 | - val = dev->wlan.wpdma_phys | |
| 752 | - MTK_PCIE_MIRROR_MAP_EN | |
| 753 | - FIELD_PREP(MTK_PCIE_MIRROR_MAP_WED_ID, dev->hw->index); |
| 754 | + val = dev->wlan.wpdma_phys | |
| 755 | + MTK_PCIE_MIRROR_MAP_EN | |
| 756 | + FIELD_PREP(MTK_PCIE_MIRROR_MAP_WED_ID, dev->hw->index); |
| 757 | |
| 758 | - if (dev->hw->index) |
| 759 | - val |= BIT(1); |
| 760 | - val |= BIT(0); |
| 761 | - regmap_write(dev->hw->mirror, dev->hw->index * 4, val); |
| 762 | + if (dev->hw->index) |
| 763 | + val |= BIT(1); |
| 764 | + val |= BIT(0); |
| 765 | + regmap_write(dev->hw->mirror, dev->hw->index * 4, val); |
| 766 | + } else { |
| 767 | + mtk_wed_set_512_support(dev, true); |
| 768 | + } |
| 769 | |
| 770 | + mtk_wed_dma_enable(dev); |
| 771 | dev->running = true; |
| 772 | } |
| 773 | |
| 774 | @@ -588,15 +814,11 @@ mtk_wed_attach(struct mtk_wed_device *dev) |
| 775 | RCU_LOCKDEP_WARN(!rcu_read_lock_held(), |
| 776 | "mtk_wed_attach without holding the RCU read lock"); |
| 777 | |
| 778 | - if (pci_domain_nr(dev->wlan.pci_dev->bus) > 1 || |
| 779 | - !try_module_get(THIS_MODULE)) |
| 780 | - ret = -ENODEV; |
| 781 | + if (!try_module_get(THIS_MODULE)) |
| 782 | + return -ENODEV; |
| 783 | |
| 784 | rcu_read_unlock(); |
| 785 | |
| 786 | - if (ret) |
| 787 | - return ret; |
| 788 | - |
| 789 | mutex_lock(&hw_lock); |
| 790 | |
| 791 | hw = mtk_wed_assign(dev); |
| 792 | @@ -606,8 +828,6 @@ mtk_wed_attach(struct mtk_wed_device *dev) |
| 793 | goto out; |
| 794 | } |
| 795 | |
| 796 | - dev_info(&dev->wlan.pci_dev->dev, "attaching wed device %d\n", hw->index); |
| 797 | - |
| 798 | dev->hw = hw; |
| 799 | dev->dev = hw->dev; |
| 800 | dev->irq = hw->irq; |
| 801 | @@ -617,6 +837,9 @@ mtk_wed_attach(struct mtk_wed_device *dev) |
| 802 | of_dma_is_coherent(hw->eth->dev->of_node)) |
| 803 | mtk_eth_set_dma_device(hw->eth, hw->dev); |
| 804 | |
| 805 | + dev->ver = FIELD_GET(MTK_WED_REV_ID_MAJOR, |
| 806 | + wed_r32(dev, MTK_WED_REV_ID)); |
| 807 | + |
| 808 | ret = mtk_wed_buffer_alloc(dev); |
| 809 | if (ret) { |
| 810 | mtk_wed_detach(dev); |
| 811 | @@ -624,7 +847,10 @@ mtk_wed_attach(struct mtk_wed_device *dev) |
| 812 | } |
| 813 | |
| 814 | mtk_wed_hw_init_early(dev); |
| 815 | - regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP, BIT(hw->index), 0); |
| 816 | + |
| 817 | + if (dev->ver == MTK_WED_V1) |
| 818 | + regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP, |
| 819 | + BIT(hw->index), 0); |
| 820 | |
| 821 | out: |
| 822 | mutex_unlock(&hw_lock); |
| 823 | @@ -651,7 +877,7 @@ mtk_wed_tx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs) |
| 824 | |
| 825 | BUG_ON(idx > ARRAY_SIZE(dev->tx_ring)); |
| 826 | |
| 827 | - if (mtk_wed_ring_alloc(dev, ring, MTK_WED_TX_RING_SIZE)) |
| 828 | + if (mtk_wed_ring_alloc(dev, ring, MTK_WED_TX_RING_SIZE, 1)) |
| 829 | return -ENOMEM; |
| 830 | |
| 831 | if (mtk_wed_wdma_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE)) |
| 832 | @@ -678,21 +904,24 @@ static int |
| 833 | mtk_wed_txfree_ring_setup(struct mtk_wed_device *dev, void __iomem *regs) |
| 834 | { |
| 835 | struct mtk_wed_ring *ring = &dev->txfree_ring; |
| 836 | - int i; |
| 837 | + int i, idx = 1; |
| 838 | + |
| 839 | + if(dev->ver > MTK_WED_V1) |
| 840 | + idx = 0; |
| 841 | |
| 842 | /* |
| 843 | * For txfree event handling, the same DMA ring is shared between WED |
| 844 | * and WLAN. The WLAN driver accesses the ring index registers through |
| 845 | * WED |
| 846 | */ |
| 847 | - ring->reg_base = MTK_WED_RING_RX(1); |
| 848 | + ring->reg_base = MTK_WED_RING_RX(idx); |
| 849 | ring->wpdma = regs; |
| 850 | |
| 851 | for (i = 0; i < 12; i += 4) { |
| 852 | u32 val = readl(regs + i); |
| 853 | |
| 854 | - wed_w32(dev, MTK_WED_RING_RX(1) + i, val); |
| 855 | - wed_w32(dev, MTK_WED_WPDMA_RING_RX(1) + i, val); |
| 856 | + wed_w32(dev, MTK_WED_RING_RX(idx) + i, val); |
| 857 | + wed_w32(dev, MTK_WED_WPDMA_RING_RX(idx) + i, val); |
| 858 | } |
| 859 | |
| 860 | return 0; |
developer | 58aa068 | 2023-09-18 14:02:26 +0800 | [diff] [blame] | 861 | @@ -780,7 +1009,8 @@ void mtk_wed_flow_remove(int index) |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 862 | } |
| 863 | |
| 864 | void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth, |
| 865 | - void __iomem *wdma, int index) |
| 866 | + void __iomem *wdma, u32 wdma_phy, int index) |
| 867 | + |
| 868 | { |
| 869 | static const struct mtk_wed_ops wed_ops = { |
| 870 | .attach = mtk_wed_attach, |
developer | 8a2ded5 | 2023-08-21 17:40:56 +0800 | [diff] [blame] | 871 | @@ -830,21 +1060,27 @@ void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth, |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 872 | hw->eth = eth; |
| 873 | hw->dev = &pdev->dev; |
| 874 | hw->wdma = wdma; |
| 875 | + hw->wdma_phy = wdma_phy; |
| 876 | hw->index = index; |
| 877 | hw->irq = irq; |
| 878 | - hw->mirror = syscon_regmap_lookup_by_phandle(eth_np, |
| 879 | - "mediatek,pcie-mirror"); |
| 880 | - hw->hifsys = syscon_regmap_lookup_by_phandle(eth_np, |
| 881 | - "mediatek,hifsys"); |
| 882 | - if (IS_ERR(hw->mirror) || IS_ERR(hw->hifsys)) { |
| 883 | - kfree(hw); |
| 884 | - goto unlock; |
| 885 | - } |
| 886 | |
| 887 | - if (!index) { |
| 888 | - regmap_write(hw->mirror, 0, 0); |
| 889 | - regmap_write(hw->mirror, 4, 0); |
| 890 | + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { |
| 891 | + hw->mirror = syscon_regmap_lookup_by_phandle(eth_np, |
| 892 | + "mediatek,pcie-mirror"); |
| 893 | + hw->hifsys = syscon_regmap_lookup_by_phandle(eth_np, |
| 894 | + "mediatek,hifsys"); |
| 895 | + |
| 896 | + if (IS_ERR(hw->mirror) || IS_ERR(hw->hifsys)) { |
| 897 | + kfree(hw); |
| 898 | + goto unlock; |
| 899 | + } |
| 900 | + |
| 901 | + if (!index) { |
| 902 | + regmap_write(hw->mirror, 0, 0); |
| 903 | + regmap_write(hw->mirror, 4, 0); |
| 904 | + } |
| 905 | } |
| 906 | + |
| 907 | mtk_wed_hw_add_debugfs(hw); |
| 908 | |
| 909 | hw_list[index] = hw; |
| 910 | diff --git a/drivers/net/ethernet/mediatek/mtk_wed.h b/drivers/net/ethernet/mediatek/mtk_wed.h |
developer | 58aa068 | 2023-09-18 14:02:26 +0800 | [diff] [blame] | 911 | index 981ec61..9b17b74 100644 |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 912 | --- a/drivers/net/ethernet/mediatek/mtk_wed.h |
| 913 | +++ b/drivers/net/ethernet/mediatek/mtk_wed.h |
| 914 | @@ -8,6 +8,19 @@ |
| 915 | #include <linux/debugfs.h> |
| 916 | #include <linux/regmap.h> |
| 917 | #include <linux/netdevice.h> |
| 918 | +#define MTK_PCIE_BASE(n) (0x1a143000 + (n) * 0x2000) |
| 919 | + |
| 920 | +#define MTK_WED_PKT_SIZE 1900 |
| 921 | +#define MTK_WED_BUF_SIZE 2048 |
| 922 | +#define MTK_WED_BUF_PER_PAGE (PAGE_SIZE / 2048) |
| 923 | + |
| 924 | +#define MTK_WED_TX_RING_SIZE 2048 |
| 925 | +#define MTK_WED_WDMA_RING_SIZE 512 |
| 926 | +#define MTK_WED_MAX_GROUP_SIZE 0x100 |
| 927 | +#define MTK_WED_VLD_GROUP_SIZE 0x40 |
| 928 | +#define MTK_WED_PER_GROUP_PKT 128 |
| 929 | + |
| 930 | +#define MTK_WED_FBUF_SIZE 128 |
| 931 | |
| 932 | struct mtk_eth; |
| 933 | |
| 934 | @@ -23,6 +36,7 @@ struct mtk_wed_hw { |
| 935 | struct mtk_wed_device *wed_dev; |
| 936 | u32 debugfs_reg; |
| 937 | u32 num_flows; |
| 938 | + u32 wdma_phy; |
| 939 | char dirname[5]; |
| 940 | int irq; |
| 941 | int index; |
| 942 | @@ -101,14 +115,14 @@ wpdma_txfree_w32(struct mtk_wed_device *dev, u32 reg, u32 val) |
| 943 | } |
| 944 | |
| 945 | void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth, |
| 946 | - void __iomem *wdma, int index); |
| 947 | + void __iomem *wdma, u32 wdma_phy, int index); |
| 948 | void mtk_wed_exit(void); |
| 949 | int mtk_wed_flow_add(int index); |
| 950 | void mtk_wed_flow_remove(int index); |
| 951 | #else |
| 952 | static inline void |
| 953 | mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth, |
| 954 | - void __iomem *wdma, int index) |
| 955 | + void __iomem *wdma, u32 wdma_phy, int index) |
| 956 | { |
| 957 | } |
| 958 | static inline void |
| 959 | diff --git a/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c |
developer | 58aa068 | 2023-09-18 14:02:26 +0800 | [diff] [blame] | 960 | index a81d3fd..f420f18 100644 |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 961 | --- a/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c |
| 962 | +++ b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c |
| 963 | @@ -116,6 +116,9 @@ wed_txinfo_show(struct seq_file *s, void *data) |
| 964 | DUMP_WDMA(WDMA_GLO_CFG), |
| 965 | DUMP_WDMA_RING(WDMA_RING_RX(0)), |
| 966 | DUMP_WDMA_RING(WDMA_RING_RX(1)), |
| 967 | + |
| 968 | + DUMP_STR("TX FREE"), |
| 969 | + DUMP_WED(WED_RX_MIB(0)), |
| 970 | }; |
| 971 | struct mtk_wed_hw *hw = s->private; |
| 972 | struct mtk_wed_device *dev = hw->wed_dev; |
| 973 | diff --git a/drivers/net/ethernet/mediatek/mtk_wed_regs.h b/drivers/net/ethernet/mediatek/mtk_wed_regs.h |
developer | 58aa068 | 2023-09-18 14:02:26 +0800 | [diff] [blame] | 974 | index 0a0465e..a9b9e2a 100644 |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 975 | --- a/drivers/net/ethernet/mediatek/mtk_wed_regs.h |
| 976 | +++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h |
| 977 | @@ -4,9 +4,15 @@ |
| 978 | #ifndef __MTK_WED_REGS_H |
| 979 | #define __MTK_WED_REGS_H |
| 980 | |
| 981 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 982 | +#define MTK_WDMA_DESC_CTRL_LEN1 GENMASK(13, 0) |
| 983 | +#define MTK_WDMA_DESC_CTRL_LAST_SEG1 BIT(14) |
| 984 | +#define MTK_WDMA_DESC_CTRL_BURST BIT(15) |
| 985 | +#else |
| 986 | #define MTK_WDMA_DESC_CTRL_LEN1 GENMASK(14, 0) |
| 987 | #define MTK_WDMA_DESC_CTRL_LAST_SEG1 BIT(15) |
| 988 | #define MTK_WDMA_DESC_CTRL_BURST BIT(16) |
| 989 | +#endif |
| 990 | #define MTK_WDMA_DESC_CTRL_LEN0 GENMASK(29, 16) |
| 991 | #define MTK_WDMA_DESC_CTRL_LAST_SEG0 BIT(30) |
| 992 | #define MTK_WDMA_DESC_CTRL_DMA_DONE BIT(31) |
developer | f50c180 | 2022-07-05 20:35:53 +0800 | [diff] [blame] | 993 | @@ -18,6 +24,14 @@ struct mtk_wdma_desc { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 994 | __le32 info; |
| 995 | } __packed __aligned(4); |
| 996 | |
developer | f50c180 | 2022-07-05 20:35:53 +0800 | [diff] [blame] | 997 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 998 | +#define MTK_WED_REV_ID 0x004 |
| 999 | +#define MTK_WED_REV_ID_MAJOR GENMASK(31, 28) |
developer | f50c180 | 2022-07-05 20:35:53 +0800 | [diff] [blame] | 1000 | +#else |
| 1001 | +#define MTK_WED_REV_ID 0x000 |
| 1002 | +#define MTK_WED_REV_ID_MAJOR GENMASK(7, 0) |
| 1003 | +#endif |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1004 | + |
| 1005 | #define MTK_WED_RESET 0x008 |
| 1006 | #define MTK_WED_RESET_TX_BM BIT(0) |
| 1007 | #define MTK_WED_RESET_TX_FREE_AGENT BIT(4) |
developer | 8a2ded5 | 2023-08-21 17:40:56 +0800 | [diff] [blame] | 1008 | @@ -41,6 +55,7 @@ struct mtk_wdma_desc { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1009 | #define MTK_WED_CTRL_RESERVE_EN BIT(12) |
| 1010 | #define MTK_WED_CTRL_RESERVE_BUSY BIT(13) |
| 1011 | #define MTK_WED_CTRL_FINAL_DIDX_READ BIT(24) |
| 1012 | +#define MTK_WED_CTRL_ETH_DMAD_FMT BIT(25) |
| 1013 | #define MTK_WED_CTRL_MIB_READ_CLEAR BIT(28) |
| 1014 | |
| 1015 | #define MTK_WED_EXT_INT_STATUS 0x020 |
developer | 8a2ded5 | 2023-08-21 17:40:56 +0800 | [diff] [blame] | 1016 | @@ -49,6 +64,10 @@ struct mtk_wdma_desc { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1017 | #define MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID BIT(4) |
| 1018 | #define MTK_WED_EXT_INT_STATUS_TX_FBUF_LO_TH BIT(8) |
| 1019 | #define MTK_WED_EXT_INT_STATUS_TX_FBUF_HI_TH BIT(9) |
| 1020 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 1021 | +#define MTK_WED_EXT_INT_STATUS_TX_TKID_LO_TH BIT(10) |
| 1022 | +#define MTK_WED_EXT_INT_STATUS_TX_TKID_HI_TH BIT(11) |
| 1023 | +#endif |
| 1024 | #define MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH BIT(12) |
| 1025 | #define MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH BIT(13) |
| 1026 | #define MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR BIT(16) |
developer | 8a2ded5 | 2023-08-21 17:40:56 +0800 | [diff] [blame] | 1027 | @@ -57,16 +76,23 @@ struct mtk_wdma_desc { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1028 | #define MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN BIT(19) |
| 1029 | #define MTK_WED_EXT_INT_STATUS_RX_DRV_BM_DMAD_COHERENT BIT(20) |
| 1030 | #define MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR BIT(21) |
| 1031 | -#define MTK_WED_EXT_INT_STATUS_TX_DRV_W_RESP_ERR BIT(22) |
| 1032 | +#define MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR BIT(22) |
| 1033 | +#define MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR BIT(23) |
| 1034 | #define MTK_WED_EXT_INT_STATUS_RX_DRV_DMA_RECYCLE BIT(24) |
| 1035 | +#define MTK_WED_EXT_INT_STATUS_RX_DRV_GET_BM_DMAD_SKIP BIT(25) |
| 1036 | +#define MTK_WED_EXT_INT_STATUS_WPDMA_RX_D_DRV_ERR BIT(26) |
| 1037 | +#define MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY BIT(27) |
| 1038 | + |
| 1039 | #define MTK_WED_EXT_INT_STATUS_ERROR_MASK (MTK_WED_EXT_INT_STATUS_TF_LEN_ERR | \ |
| 1040 | MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD | \ |
| 1041 | MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID | \ |
| 1042 | + MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH | \ |
| 1043 | + MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH | \ |
| 1044 | MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR | \ |
| 1045 | MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR | \ |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1046 | MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN | \ |
| 1047 | - MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR | \ |
| 1048 | - MTK_WED_EXT_INT_STATUS_TX_DRV_W_RESP_ERR) |
| 1049 | + MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR | \ |
| 1050 | + MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR) |
| 1051 | |
| 1052 | #define MTK_WED_EXT_INT_MASK 0x028 |
| 1053 | |
developer | 8a2ded5 | 2023-08-21 17:40:56 +0800 | [diff] [blame] | 1054 | @@ -80,10 +106,6 @@ struct mtk_wdma_desc { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1055 | |
| 1056 | #define MTK_WED_TX_BM_BASE 0x084 |
| 1057 | |
| 1058 | -#define MTK_WED_TX_BM_TKID 0x088 |
| 1059 | -#define MTK_WED_TX_BM_TKID_START GENMASK(15, 0) |
| 1060 | -#define MTK_WED_TX_BM_TKID_END GENMASK(31, 16) |
| 1061 | - |
| 1062 | #define MTK_WED_TX_BM_BUF_LEN 0x08c |
| 1063 | |
| 1064 | #define MTK_WED_TX_BM_INTF 0x09c |
developer | 8a2ded5 | 2023-08-21 17:40:56 +0800 | [diff] [blame] | 1065 | @@ -93,9 +115,38 @@ struct mtk_wdma_desc { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1066 | #define MTK_WED_TX_BM_INTF_TKID_READ BIT(29) |
| 1067 | |
| 1068 | #define MTK_WED_TX_BM_DYN_THR 0x0a0 |
| 1069 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 1070 | +#define MTK_WED_TX_BM_DYN_THR_LO GENMASK(8, 0) |
| 1071 | +#define MTK_WED_TX_BM_DYN_THR_HI GENMASK(24, 16) |
| 1072 | + |
| 1073 | +#define MTK_WED_TX_BM_TKID 0x0c8 |
| 1074 | +#define MTK_WED_TX_BM_TKID_START GENMASK(15, 0) |
| 1075 | +#define MTK_WED_TX_BM_TKID_END GENMASK(31, 16) |
| 1076 | +#else |
| 1077 | #define MTK_WED_TX_BM_DYN_THR_LO GENMASK(6, 0) |
| 1078 | #define MTK_WED_TX_BM_DYN_THR_HI GENMASK(22, 16) |
| 1079 | |
| 1080 | +#define MTK_WED_TX_BM_TKID 0x088 |
| 1081 | +#define MTK_WED_TX_BM_TKID_START GENMASK(15, 0) |
| 1082 | +#define MTK_WED_TX_BM_TKID_END GENMASK(31, 16) |
| 1083 | +#endif |
| 1084 | + |
| 1085 | +#define MTK_WED_TX_TKID_CTRL 0x0c0 |
| 1086 | +#define MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM GENMASK(6, 0) |
| 1087 | +#define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM GENMASK(22, 16) |
| 1088 | +#define MTK_WED_TX_TKID_CTRL_PAUSE BIT(28) |
| 1089 | + |
| 1090 | +#define MTK_WED_TX_TKID_DYN_THR 0x0e0 |
| 1091 | +#define MTK_WED_TX_TKID_DYN_THR_LO GENMASK(6, 0) |
| 1092 | +#define MTK_WED_TX_TKID_DYN_THR_HI GENMASK(22, 16) |
| 1093 | + |
| 1094 | +#define MTK_WED_TXP_DW0 0x120 |
| 1095 | +#define MTK_WED_TXP_DW1 0x124 |
| 1096 | +#define MTK_WED_WPDMA_WRITE_TXP GENMASK(31, 16) |
| 1097 | +#define MTK_WED_TXDP_CTRL 0x130 |
| 1098 | +#define MTK_WED_TXDP_DW9_OVERWR BIT(9) |
| 1099 | +#define MTK_WED_RX_BM_TKID_MIB 0x1cc |
| 1100 | + |
| 1101 | #define MTK_WED_INT_STATUS 0x200 |
| 1102 | #define MTK_WED_INT_MASK 0x204 |
| 1103 | |
developer | 8a2ded5 | 2023-08-21 17:40:56 +0800 | [diff] [blame] | 1104 | @@ -125,6 +176,7 @@ struct mtk_wdma_desc { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1105 | #define MTK_WED_RESET_IDX_RX GENMASK(17, 16) |
| 1106 | |
| 1107 | #define MTK_WED_TX_MIB(_n) (0x2a0 + (_n) * 4) |
| 1108 | +#define MTK_WED_RX_MIB(_n) (0x2e0 + (_n) * 4) |
| 1109 | |
| 1110 | #define MTK_WED_RING_TX(_n) (0x300 + (_n) * 0x10) |
| 1111 | |
developer | 8a2ded5 | 2023-08-21 17:40:56 +0800 | [diff] [blame] | 1112 | @@ -139,6 +191,19 @@ struct mtk_wdma_desc { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1113 | #define MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY BIT(1) |
| 1114 | #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN BIT(2) |
| 1115 | #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_BUSY BIT(3) |
| 1116 | +/* CONFIG_MEDIATEK_NETSYS_V2 */ |
| 1117 | +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC BIT(4) |
| 1118 | +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_PKT_PROC BIT(5) |
| 1119 | +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC BIT(6) |
| 1120 | +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_CRX_SYNC BIT(7) |
| 1121 | +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_VER GENMASK(18, 16) |
| 1122 | +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNSUPPORT_FMT BIT(19) |
| 1123 | +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UEVENT_PKT_FMT_CHK BIT(20) |
| 1124 | +#define MTK_WED_WPDMA_GLO_CFG_RX_DDONE2_WR BIT(21) |
| 1125 | +#define MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP BIT(24) |
| 1126 | +#define MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV BIT(28) |
| 1127 | + |
| 1128 | +/* CONFIG_MEDIATEK_NETSYS_V1 */ |
| 1129 | #define MTK_WED_WPDMA_GLO_CFG_RX_BT_SIZE GENMASK(5, 4) |
| 1130 | #define MTK_WED_WPDMA_GLO_CFG_TX_WB_DDONE BIT(6) |
| 1131 | #define MTK_WED_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7) |
developer | 8a2ded5 | 2023-08-21 17:40:56 +0800 | [diff] [blame] | 1132 | @@ -152,24 +217,54 @@ struct mtk_wdma_desc { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1133 | #define MTK_WED_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY BIT(26) |
| 1134 | #define MTK_WED_WPDMA_GLO_CFG_OMIT_RX_INFO BIT(27) |
| 1135 | #define MTK_WED_WPDMA_GLO_CFG_OMIT_TX_INFO BIT(28) |
| 1136 | + |
| 1137 | #define MTK_WED_WPDMA_GLO_CFG_BYTE_SWAP BIT(29) |
| 1138 | +#define MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK BIT(30) |
| 1139 | #define MTK_WED_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31) |
| 1140 | |
| 1141 | #define MTK_WED_WPDMA_RESET_IDX 0x50c |
| 1142 | #define MTK_WED_WPDMA_RESET_IDX_TX GENMASK(3, 0) |
| 1143 | #define MTK_WED_WPDMA_RESET_IDX_RX GENMASK(17, 16) |
| 1144 | |
| 1145 | +#define MTK_WED_WPDMA_CTRL 0x518 |
| 1146 | +#define MTK_WED_WPDMA_CTRL_SDL1_FIXED BIT(31) |
| 1147 | + |
| 1148 | #define MTK_WED_WPDMA_INT_CTRL 0x520 |
| 1149 | #define MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV BIT(21) |
| 1150 | +#define MTK_WED_WPDMA_INT_CTRL_SIG_SRC BIT(22) |
| 1151 | +#define MTK_WED_WPDMA_INT_CTRL_SRC_SEL GENMASK(17, 16) |
| 1152 | |
| 1153 | #define MTK_WED_WPDMA_INT_MASK 0x524 |
| 1154 | |
| 1155 | -#define MTK_WED_PCIE_CFG_BASE 0x560 |
| 1156 | +#define MTK_WED_WPDMA_INT_CTRL_TX 0x530 |
| 1157 | +#define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN BIT(0) |
| 1158 | +#define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_CLR BIT(1) |
| 1159 | +#define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_TRIG GENMASK(6, 2) |
| 1160 | +#define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_EN BIT(8) |
| 1161 | +#define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_CLR BIT(9) |
| 1162 | +#define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_TRIG GENMASK(14, 10) |
| 1163 | + |
| 1164 | +#define MTK_WED_WPDMA_INT_CTRL_RX 0x534 |
| 1165 | + |
| 1166 | +#define MTK_WED_WPDMA_INT_CTRL_TX_FREE 0x538 |
| 1167 | +#define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_EN BIT(0) |
| 1168 | +#define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_CLR BIT(1) |
| 1169 | +#define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG GENMASK(6, 2) |
| 1170 | |
| 1171 | +#define MTK_WED_PCIE_CFG_BASE 0x560 |
| 1172 | +#define MTK_WED_PCIE_CFG_INTM 0x564 |
| 1173 | +#define MTK_WED_PCIE_CFG_MSIS 0x568 |
| 1174 | #define MTK_WED_PCIE_INT_TRIGGER 0x570 |
| 1175 | #define MTK_WED_PCIE_INT_TRIGGER_STATUS BIT(16) |
| 1176 | |
| 1177 | +#define MTK_WED_PCIE_INT_CTRL 0x57c |
| 1178 | +#define MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA BIT(20) |
| 1179 | +#define MTK_WED_PCIE_INT_CTRL_SRC_SEL GENMASK(17, 16) |
| 1180 | +#define MTK_WED_PCIE_INT_CTRL_POLL_EN GENMASK(13, 12) |
| 1181 | #define MTK_WED_WPDMA_CFG_BASE 0x580 |
| 1182 | +#define MTK_WED_WPDMA_CFG_INT_MASK 0x584 |
| 1183 | +#define MTK_WED_WPDMA_CFG_TX 0x588 |
| 1184 | +#define MTK_WED_WPDMA_CFG_TX_FREE 0x58c |
| 1185 | |
| 1186 | #define MTK_WED_WPDMA_TX_MIB(_n) (0x5a0 + (_n) * 4) |
| 1187 | #define MTK_WED_WPDMA_TX_COHERENT_MIB(_n) (0x5d0 + (_n) * 4) |
developer | 8a2ded5 | 2023-08-21 17:40:56 +0800 | [diff] [blame] | 1188 | @@ -203,14 +298,22 @@ struct mtk_wdma_desc { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1189 | #define MTK_WED_WDMA_RESET_IDX_RX GENMASK(17, 16) |
| 1190 | #define MTK_WED_WDMA_RESET_IDX_DRV GENMASK(25, 24) |
| 1191 | |
| 1192 | +#define MTK_WED_WDMA_INT_CLR 0xa24 |
| 1193 | +#define MTK_WED_WDMA_INT_CLR_RX_DONE GENMASK(17, 16) |
| 1194 | + |
| 1195 | #define MTK_WED_WDMA_INT_TRIGGER 0xa28 |
| 1196 | #define MTK_WED_WDMA_INT_TRIGGER_RX_DONE GENMASK(17, 16) |
| 1197 | |
| 1198 | #define MTK_WED_WDMA_INT_CTRL 0xa2c |
| 1199 | -#define MTK_WED_WDMA_INT_CTRL_POLL_SRC_SEL GENMASK(17, 16) |
| 1200 | +#define MTK_WED_WDMA_INT_POLL_SRC_SEL GENMASK(17, 16) |
| 1201 | |
| 1202 | +#define MTK_WED_WDMA_CFG_BASE 0xaa0 |
| 1203 | #define MTK_WED_WDMA_OFFSET0 0xaa4 |
| 1204 | #define MTK_WED_WDMA_OFFSET1 0xaa8 |
| 1205 | +#define MTK_WED_WDMA_OFST0_GLO_INTS GENMASK(15, 0) |
| 1206 | +#define MTK_WED_WDMA_OFST0_GLO_CFG GENMASK(31, 16) |
| 1207 | +#define MTK_WED_WDMA_OFST1_TX_CTRL GENMASK(15, 0) |
| 1208 | +#define MTK_WED_WDMA_OFST1_RX_CTRL GENMASK(31, 16) |
| 1209 | |
| 1210 | #define MTK_WED_WDMA_RX_MIB(_n) (0xae0 + (_n) * 4) |
| 1211 | #define MTK_WED_WDMA_RX_RECYCLE_MIB(_n) (0xae8 + (_n) * 4) |
developer | 8a2ded5 | 2023-08-21 17:40:56 +0800 | [diff] [blame] | 1212 | @@ -221,14 +324,21 @@ struct mtk_wdma_desc { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1213 | #define MTK_WED_RING_OFS_CPU_IDX 0x08 |
| 1214 | #define MTK_WED_RING_OFS_DMA_IDX 0x0c |
| 1215 | |
| 1216 | +#define MTK_WDMA_RING_TX(_n) (0x000 + (_n) * 0x10) |
| 1217 | #define MTK_WDMA_RING_RX(_n) (0x100 + (_n) * 0x10) |
| 1218 | |
| 1219 | #define MTK_WDMA_GLO_CFG 0x204 |
| 1220 | -#define MTK_WDMA_GLO_CFG_RX_INFO_PRERES GENMASK(28, 26) |
| 1221 | +#define MTK_WDMA_GLO_CFG_TX_DMA_EN BIT(0) |
| 1222 | +#define MTK_WDMA_GLO_CFG_RX_DMA_EN BIT(2) |
| 1223 | +#define MTK_WDMA_GLO_CFG_RX_INFO3_PRERES BIT(26) |
| 1224 | +#define MTK_WDMA_GLO_CFG_RX_INFO2_PRERES BIT(27) |
| 1225 | +#define MTK_WDMA_GLO_CFG_RX_INFO1_PRERES BIT(28) |
| 1226 | + |
| 1227 | |
| 1228 | #define MTK_WDMA_RESET_IDX 0x208 |
| 1229 | #define MTK_WDMA_RESET_IDX_TX GENMASK(3, 0) |
| 1230 | #define MTK_WDMA_RESET_IDX_RX GENMASK(17, 16) |
| 1231 | +#define MTK_WDMA_INT_STATUS 0x220 |
| 1232 | |
| 1233 | #define MTK_WDMA_INT_MASK 0x228 |
| 1234 | #define MTK_WDMA_INT_MASK_TX_DONE GENMASK(3, 0) |
| 1235 | diff --git a/include/linux/soc/mediatek/mtk_wed.h b/include/linux/soc/mediatek/mtk_wed.h |
developer | 58aa068 | 2023-09-18 14:02:26 +0800 | [diff] [blame] | 1236 | index 7e00cca..ffd547a 100644 |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1237 | --- a/include/linux/soc/mediatek/mtk_wed.h |
| 1238 | +++ b/include/linux/soc/mediatek/mtk_wed.h |
| 1239 | @@ -8,6 +8,19 @@ |
| 1240 | |
| 1241 | #define MTK_WED_TX_QUEUES 2 |
| 1242 | |
| 1243 | +enum { |
| 1244 | + MTK_NO_WED, |
| 1245 | + MTK_WED_V1, |
| 1246 | + MTK_WED_V2, |
| 1247 | + MTK_WED_VMAX |
| 1248 | +}; |
| 1249 | + |
| 1250 | +enum { |
| 1251 | + MTK_BUS_TYPE_PCIE, |
| 1252 | + MTK_BUS_TYPE_AXI, |
| 1253 | + MTK_BUS_TYPE_MAX |
| 1254 | +}; |
| 1255 | + |
| 1256 | struct mtk_wed_hw; |
| 1257 | struct mtk_wdma_desc; |
| 1258 | |
| 1259 | @@ -28,6 +41,7 @@ struct mtk_wed_device { |
| 1260 | bool init_done, running; |
| 1261 | int wdma_idx; |
| 1262 | int irq; |
| 1263 | + u8 ver; |
| 1264 | |
| 1265 | struct mtk_wed_ring tx_ring[MTK_WED_TX_QUEUES]; |
| 1266 | struct mtk_wed_ring txfree_ring; |
developer | 2cd6d28 | 2022-07-07 18:17:32 +0800 | [diff] [blame] | 1267 | @@ -43,8 +57,17 @@ struct mtk_wed_device { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1268 | /* filled by driver: */ |
| 1269 | struct { |
| 1270 | struct pci_dev *pci_dev; |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1271 | + void __iomem *base; |
| 1272 | + u32 bus_type; |
developer | 2cd6d28 | 2022-07-07 18:17:32 +0800 | [diff] [blame] | 1273 | |
| 1274 | u32 wpdma_phys; |
| 1275 | + u32 wpdma_int; |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1276 | + u32 wpdma_mask; |
| 1277 | + u32 wpdma_tx; |
| 1278 | + u32 wpdma_txfree; |
| 1279 | + |
| 1280 | + u8 tx_tbit[MTK_WED_TX_QUEUES]; |
| 1281 | + u8 txfree_tbit; |
| 1282 | |
| 1283 | u16 token_start; |
| 1284 | unsigned int nbuf; |
| 1285 | -- |
| 1286 | 2.18.0 |
| 1287 | |