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git01.mediatek.com / openwrt / feeds / mtk-openwrt-feeds / 8cb3ac77bd09e8dcf731320fb5df08e2a7ec1ccd / . / autobuild_mac80211_release / target / linux / mediatek / patches-5.4 / 9996-add-wed-tx-support-for-mt7986.patch
blob: 8f3e2caf94a1f754ec0e4817e739ef3a74761262 [file] [log] [blame]
developer8cb3ac72022-07-04 10:55:14 +0800[diff] [blame^]1From c6b43d63c3d4229b5f15cb7391192494b07e0fa7 Mon Sep 17 00:00:00 2001
2From: Bo Jiao <Bo.Jiao@mediatek.com>
3Date: Mon, 27 Jun 2022 14:53:54 +0800
4Subject: [PATCH 7/8] 9996-add-wed-tx-support-for-mt7986
5
6---
7 arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 2 +
8 arch/arm64/boot/dts/mediatek/mt7986b.dtsi | 2 +
9 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 8 +-
10 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 5 +
11 drivers/net/ethernet/mediatek/mtk_wed.c | 502 +++++++++++++-----
12 drivers/net/ethernet/mediatek/mtk_wed.h | 18 +-
13 .../net/ethernet/mediatek/mtk_wed_debugfs.c | 3 +
14 drivers/net/ethernet/mediatek/mtk_wed_regs.h | 127 ++++-
15 include/linux/soc/mediatek/mtk_wed.h | 29 +-
16 9 files changed, 546 insertions(+), 150 deletions(-)
17
18diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
19index 381136c21..644255b35 100644
20--- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
21+++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
22@@ -64,6 +64,7 @@
23 reg = <0 0x15010000 0 0x1000>;
24 interrupt-parent = <&gic>;
25 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
26+ mediatek,wed_pcie = <&wed_pcie>;
27 };
28
29 wed1: wed@15011000 {
30@@ -72,6 +73,7 @@
31 reg = <0 0x15011000 0 0x1000>;
32 interrupt-parent = <&gic>;
33 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
34+ mediatek,wed_pcie = <&wed_pcie>;
35 };
36
37 ap2woccif: ap2woccif@151A5000 {
38diff --git a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
39index 0e5f116a2..67bf86f6a 100644
40--- a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
41+++ b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi
42@@ -64,6 +64,7 @@
43 reg = <0 0x15010000 0 0x1000>;
44 interrupt-parent = <&gic>;
45 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
46+ mediatek,wed_pcie = <&wed_pcie>;
47 };
48
49 wed1: wed@15011000 {
50@@ -72,6 +73,7 @@
51 reg = <0 0x15011000 0 0x1000>;
52 interrupt-parent = <&gic>;
53 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
54+ mediatek,wed_pcie = <&wed_pcie>;
55 };
56
57 ap2woccif: ap2woccif@151A5000 {
58diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
59index 3f67bebfe..ac021e2ed 100644
60--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
61+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
62@@ -3579,6 +3579,7 @@ static int mtk_probe(struct platform_device *pdev)
63 {
64 struct device_node *mac_np;
65 struct mtk_eth *eth;
66+ struct resource *res;
67 int err, i;
68
69 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
70@@ -3594,7 +3595,6 @@ static int mtk_probe(struct platform_device *pdev)
71 return PTR_ERR(eth->base);
72
73 if(eth->soc->has_sram) {
74- struct resource *res;
75 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
76 if (unlikely(!res))
77 return -EINVAL;
78@@ -3682,12 +3682,16 @@ static int mtk_probe(struct platform_device *pdev)
79 MTK_WDMA1_BASE
80 };
81 void __iomem *wdma;
82+ u32 wdma_phy;
83
84 if (!np || i >= ARRAY_SIZE(wdma_regs))
85 break;
86
87 wdma = eth->base + wdma_regs[i];
88- mtk_wed_add_hw(np, eth, wdma, i);
89+ if (res)
90+ wdma_phy = res->start + wdma_regs[i];
91+
92+ mtk_wed_add_hw(np, eth, wdma, wdma_phy, i);
93 }
94
95 for (i = 0; i < MTK_MAX_IRQ_NUM; i++) {
96diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
97index b4de7c0c6..4a69bd0cf 100644
98--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
99+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
100@@ -518,8 +518,13 @@
101 #define RX_DMA_SPORT_MASK 0x7
102 #endif
103
104+#if defined(CONFIG_MEDIATEK_NETSYS_V2)
105+#define MTK_WDMA0_BASE 0x4800
106+#define MTK_WDMA1_BASE 0x4c00
107+#else
108 #define MTK_WDMA0_BASE 0x2800
109 #define MTK_WDMA1_BASE 0x2c00
110+#endif
111
112 /* QDMA descriptor txd4 */
113 #define TX_DMA_CHKSUM (0x7 << 29)
114diff --git a/drivers/net/ethernet/mediatek/mtk_wed.c b/drivers/net/ethernet/mediatek/mtk_wed.c
115index ea1cbdf1a..48b0353bb 100644
116--- a/drivers/net/ethernet/mediatek/mtk_wed.c
117+++ b/drivers/net/ethernet/mediatek/mtk_wed.c
118@@ -18,15 +18,6 @@
119 #include "mtk_wed.h"
120 #include "mtk_ppe.h"
121
122-#define MTK_PCIE_BASE(n) (0x1a143000 + (n) * 0x2000)
123-
124-#define MTK_WED_PKT_SIZE 1900
125-#define MTK_WED_BUF_SIZE 2048
126-#define MTK_WED_BUF_PER_PAGE (PAGE_SIZE / 2048)
127-
128-#define MTK_WED_TX_RING_SIZE 2048
129-#define MTK_WED_WDMA_RING_SIZE 1024
130-
131 static struct mtk_wed_hw *hw_list[2];
132 static DEFINE_MUTEX(hw_lock);
133
134@@ -80,14 +71,19 @@ mtk_wed_reset(struct mtk_wed_device *dev, u32 mask)
135 static struct mtk_wed_hw *
136 mtk_wed_assign(struct mtk_wed_device *dev)
137 {
138- struct mtk_wed_hw *hw;
139+ int i;
140+
141+ for (i = 0; i < ARRAY_SIZE(hw_list); i++) {
142+ struct mtk_wed_hw *hw = hw_list[i];
143+
144+ if (!hw || hw->wed_dev)
145+ continue;
146
147- hw = hw_list[pci_domain_nr(dev->wlan.pci_dev->bus)];
148- if (!hw || hw->wed_dev)
149- return NULL;
150+ hw->wed_dev = dev;
151+ return hw;
152+ }
153
154- hw->wed_dev = dev;
155- return hw;
156+ return NULL;
157 }
158
159 static int
160@@ -96,19 +92,27 @@ mtk_wed_buffer_alloc(struct mtk_wed_device *dev)
161 struct mtk_wdma_desc *desc;
162 dma_addr_t desc_phys;
163 void **page_list;
164+ u32 last_seg = MTK_WDMA_DESC_CTRL_LAST_SEG1;
165 int token = dev->wlan.token_start;
166- int ring_size;
167- int n_pages;
168- int i, page_idx;
169+ int ring_size, n_pages, page_idx;
170+ int i;
171+
172+
173+ if (dev->ver == MTK_WED_V1) {
174+ ring_size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1);
175+ } else {
176+ ring_size = MTK_WED_VLD_GROUP_SIZE * MTK_WED_PER_GROUP_PKT +
177+ MTK_WED_WDMA_RING_SIZE * 2;
178+ last_seg = MTK_WDMA_DESC_CTRL_LAST_SEG0;
179+ }
180
181- ring_size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1);
182 n_pages = ring_size / MTK_WED_BUF_PER_PAGE;
183
184 page_list = kcalloc(n_pages, sizeof(*page_list), GFP_KERNEL);
185 if (!page_list)
186 return -ENOMEM;
187
188- dev->buf_ring.size = ring_size;
189+ dev->buf_ring.size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1);
190 dev->buf_ring.pages = page_list;
191
192 desc = dma_alloc_coherent(dev->hw->dev, ring_size * sizeof(*desc),
193@@ -154,7 +158,7 @@ mtk_wed_buffer_alloc(struct mtk_wed_device *dev)
194 txd_size) |
195 FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1,
196 MTK_WED_BUF_SIZE - txd_size) |
197- MTK_WDMA_DESC_CTRL_LAST_SEG1;
198+ last_seg;
199 desc->info = 0;
200 desc++;
201
202@@ -202,12 +206,12 @@ free_pagelist:
203 }
204
205 static void
206-mtk_wed_free_ring(struct mtk_wed_device *dev, struct mtk_wed_ring *ring)
207+mtk_wed_free_ring(struct mtk_wed_device *dev, struct mtk_wed_ring *ring, int scale)
208 {
209 if (!ring->desc)
210 return;
211
212- dma_free_coherent(dev->hw->dev, ring->size * sizeof(*ring->desc),
213+ dma_free_coherent(dev->hw->dev, ring->size * sizeof(*ring->desc) * scale,
214 ring->desc, ring->desc_phys);
215 }
216
217@@ -217,9 +221,69 @@ mtk_wed_free_tx_rings(struct mtk_wed_device *dev)
218 int i;
219
220 for (i = 0; i < ARRAY_SIZE(dev->tx_ring); i++)
221- mtk_wed_free_ring(dev, &dev->tx_ring[i]);
222+ mtk_wed_free_ring(dev, &dev->tx_ring[i], 1);
223 for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)
224- mtk_wed_free_ring(dev, &dev->tx_wdma[i]);
225+ mtk_wed_free_ring(dev, &dev->tx_wdma[i], dev->ver);
226+}
227+
228+static void
229+mtk_wed_set_int(struct mtk_wed_device *dev, u32 irq_mask)
230+{
231+ u32 wdma_mask;
232+
233+ wdma_mask = FIELD_PREP(MTK_WDMA_INT_MASK_RX_DONE, GENMASK(1, 0));
234+
235+ /* wed control cr set */
236+ wed_set(dev, MTK_WED_CTRL,
237+ MTK_WED_CTRL_WDMA_INT_AGENT_EN |
238+ MTK_WED_CTRL_WPDMA_INT_AGENT_EN |
239+ MTK_WED_CTRL_WED_TX_BM_EN |
240+ MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
241+
242+ if (dev->ver == MTK_WED_V1) {
243+ wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER,
244+ MTK_WED_PCIE_INT_TRIGGER_STATUS);
245+
246+ wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER,
247+ MTK_WED_WPDMA_INT_TRIGGER_RX_DONE |
248+ MTK_WED_WPDMA_INT_TRIGGER_TX_DONE);
249+
250+ wed_set(dev, MTK_WED_WPDMA_INT_CTRL,
251+ MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
252+ } else {
253+ /* initail tx interrupt trigger */
254+ wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX,
255+ MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN |
256+ MTK_WED_WPDMA_INT_CTRL_TX0_DONE_CLR |
257+ MTK_WED_WPDMA_INT_CTRL_TX1_DONE_EN |
258+ MTK_WED_WPDMA_INT_CTRL_TX1_DONE_CLR |
259+ FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX0_DONE_TRIG,
260+ dev->wlan.tx_tbit[0]) |
261+ FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX1_DONE_TRIG,
262+ dev->wlan.tx_tbit[1]));
263+
264+ /* initail txfree interrupt trigger */
265+ wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX_FREE,
266+ MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_EN |
267+ MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_CLR |
268+ FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG,
269+ dev->wlan.txfree_tbit));
270+ }
271+ /* initail wdma interrupt agent */
272+ wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, wdma_mask);
273+ if (dev->ver == MTK_WED_V1) {
274+ wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask);
275+ } else {
276+ wed_w32(dev, MTK_WED_WDMA_INT_CLR, wdma_mask);
277+ wed_set(dev, MTK_WED_WDMA_INT_CTRL,
278+ FIELD_PREP(MTK_WED_WDMA_INT_POLL_SRC_SEL,dev->wdma_idx));
279+
280+ }
281+
282+ wdma_w32(dev, MTK_WDMA_INT_MASK, wdma_mask);
283+ wdma_w32(dev, MTK_WDMA_INT_GRP2, wdma_mask);
284+ wed_w32(dev, MTK_WED_WPDMA_INT_MASK, irq_mask);
285+ wed_w32(dev, MTK_WED_INT_MASK, irq_mask);
286 }
287
288 static void
289@@ -234,10 +298,95 @@ mtk_wed_set_ext_int(struct mtk_wed_device *dev, bool en)
290 wed_r32(dev, MTK_WED_EXT_INT_MASK);
291 }
292
293+static void
294+mtk_wed_set_512_support(struct mtk_wed_device *dev, bool en)
295+{
296+ if (en) {
297+ wed_w32(dev, MTK_WED_TXDP_CTRL, MTK_WED_TXDP_DW9_OVERWR);
298+ wed_w32(dev, MTK_WED_TXP_DW1,
299+ FIELD_PREP(MTK_WED_WPDMA_WRITE_TXP, 0x0103));
300+ } else {
301+ wed_w32(dev, MTK_WED_TXP_DW1,
302+ FIELD_PREP(MTK_WED_WPDMA_WRITE_TXP, 0x0100));
303+ wed_clr(dev, MTK_WED_TXDP_CTRL, MTK_WED_TXDP_DW9_OVERWR);
304+ }
305+}
306+
307+static void
308+mtk_wed_dma_enable(struct mtk_wed_device *dev)
309+{
310+ wed_set(dev, MTK_WED_WPDMA_INT_CTRL,
311+ MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
312+
313+ wed_set(dev, MTK_WED_GLO_CFG,
314+ MTK_WED_GLO_CFG_TX_DMA_EN |
315+ MTK_WED_GLO_CFG_RX_DMA_EN);
316+ wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
317+ MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
318+ MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);
319+ wed_set(dev, MTK_WED_WDMA_GLO_CFG,
320+ MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
321+
322+ wdma_set(dev, MTK_WDMA_GLO_CFG,
323+ MTK_WDMA_GLO_CFG_TX_DMA_EN |
324+ MTK_WDMA_GLO_CFG_RX_INFO1_PRERES |
325+ MTK_WDMA_GLO_CFG_RX_INFO2_PRERES);
326+
327+ if (dev->ver == MTK_WED_V1) {
328+ wdma_set(dev, MTK_WDMA_GLO_CFG,
329+ MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
330+ } else {
331+ wed_set(dev, MTK_WED_WPDMA_CTRL,
332+ MTK_WED_WPDMA_CTRL_SDL1_FIXED);
333+
334+ wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
335+ MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC |
336+ MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC);
337+
338+ wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
339+ MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP |
340+ MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV);
341+ }
342+}
343+
344+static void
345+mtk_wed_dma_disable(struct mtk_wed_device *dev)
346+{
347+ wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
348+ MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
349+ MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);
350+
351+ wed_clr(dev, MTK_WED_WDMA_GLO_CFG,
352+ MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
353+
354+ wed_clr(dev, MTK_WED_GLO_CFG,
355+ MTK_WED_GLO_CFG_TX_DMA_EN |
356+ MTK_WED_GLO_CFG_RX_DMA_EN);
357+
358+ wdma_m32(dev, MTK_WDMA_GLO_CFG,
359+ MTK_WDMA_GLO_CFG_TX_DMA_EN |
360+ MTK_WDMA_GLO_CFG_RX_INFO1_PRERES |
361+ MTK_WDMA_GLO_CFG_RX_INFO2_PRERES, 0);
362+
363+ if (dev->ver == MTK_WED_V1) {
364+ regmap_write(dev->hw->mirror, dev->hw->index * 4, 0);
365+ wdma_m32(dev, MTK_WDMA_GLO_CFG,
366+ MTK_WDMA_GLO_CFG_RX_INFO3_PRERES, 0);
367+ } else {
368+ wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
369+ MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC |
370+ MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC);
371+ }
372+}
373+
374 static void
375 mtk_wed_stop(struct mtk_wed_device *dev)
376 {
377- regmap_write(dev->hw->mirror, dev->hw->index * 4, 0);
378+ mtk_wed_dma_disable(dev);
379+
380+ if (dev->ver > MTK_WED_V1)
381+ mtk_wed_set_512_support(dev, false);
382+
383 mtk_wed_set_ext_int(dev, false);
384
385 wed_clr(dev, MTK_WED_CTRL,
386@@ -245,26 +394,18 @@ mtk_wed_stop(struct mtk_wed_device *dev)
387 MTK_WED_CTRL_WPDMA_INT_AGENT_EN |
388 MTK_WED_CTRL_WED_TX_BM_EN |
389 MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
390+
391 wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0);
392 wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0);
393 wdma_w32(dev, MTK_WDMA_INT_MASK, 0);
394 wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
395 wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
396-
397- wed_clr(dev, MTK_WED_GLO_CFG,
398- MTK_WED_GLO_CFG_TX_DMA_EN |
399- MTK_WED_GLO_CFG_RX_DMA_EN);
400- wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
401- MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
402- MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);
403- wed_clr(dev, MTK_WED_WDMA_GLO_CFG,
404- MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
405 }
406
407 static void
408 mtk_wed_detach(struct mtk_wed_device *dev)
409 {
410- struct device_node *wlan_node = dev->wlan.pci_dev->dev.of_node;
411+ struct device_node *wlan_node;
412 struct mtk_wed_hw *hw = dev->hw;
413
414 mutex_lock(&hw_lock);
415@@ -279,9 +420,12 @@ mtk_wed_detach(struct mtk_wed_device *dev)
416 mtk_wed_free_buffer(dev);
417 mtk_wed_free_tx_rings(dev);
418
419- if (of_dma_is_coherent(wlan_node))
420- regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP,
421- BIT(hw->index), BIT(hw->index));
422+ if (dev->wlan.bus_type == MTK_BUS_TYPE_PCIE) {
423+ wlan_node = dev->wlan.pci_dev->dev.of_node;
424+ if (of_dma_is_coherent(wlan_node))
425+ regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP,
426+ BIT(hw->index), BIT(hw->index));
427+ }
428
429 if (!hw_list[!hw->index]->wed_dev &&
430 hw->eth->dma_dev != hw->eth->dev)
431@@ -294,15 +438,87 @@ mtk_wed_detach(struct mtk_wed_device *dev)
432 mutex_unlock(&hw_lock);
433 }
434
435+static void
436+mtk_wed_bus_init(struct mtk_wed_device *dev)
437+{
438+#define PCIE_BASE_ADDR0 0x11280000
439+
440+ if (dev->wlan.bus_type == MTK_BUS_TYPE_PCIE) {
441+ struct device_node *node;
442+ void __iomem * base_addr;
443+ u32 value = 0;
444+
445+ node = of_parse_phandle(dev->hw->node, "mediatek,wed_pcie", 0);
446+ if (!node) {
447+ pr_err("%s: no wed_pcie node\n", __func__);
448+ return;
449+ }
450+
451+ base_addr = of_iomap(node, 0);
452+
453+ value = readl(base_addr);
454+ value |= BIT(0);
455+ writel(value, base_addr);
456+
457+ wed_w32(dev, MTK_WED_PCIE_INT_CTRL,
458+ FIELD_PREP(MTK_WED_PCIE_INT_CTRL_POLL_EN, 2));
459+
460+ /* pcie interrupt control: pola/source selection */
461+ wed_set(dev, MTK_WED_PCIE_INT_CTRL,
462+ MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA |
463+ FIELD_PREP(MTK_WED_PCIE_INT_CTRL_SRC_SEL, 1));
464+ wed_r32(dev, MTK_WED_PCIE_INT_CTRL);
465+
466+ value = wed_r32(dev, MTK_WED_PCIE_CFG_INTM);
467+ value = wed_r32(dev, MTK_WED_PCIE_CFG_BASE);
468+ wed_w32(dev, MTK_WED_PCIE_CFG_INTM, PCIE_BASE_ADDR0 | 0x180);
469+ wed_w32(dev, MTK_WED_PCIE_CFG_BASE, PCIE_BASE_ADDR0 | 0x184);
470+
471+ value = wed_r32(dev, MTK_WED_PCIE_CFG_INTM);
472+ value = wed_r32(dev, MTK_WED_PCIE_CFG_BASE);
473+
474+ /* pcie interrupt status trigger register */
475+ wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(24));
476+ wed_r32(dev, MTK_WED_PCIE_INT_TRIGGER);
477+
478+ /* pola setting */
479+ value = wed_r32(dev, MTK_WED_PCIE_INT_CTRL);
480+ wed_set(dev, MTK_WED_PCIE_INT_CTRL,
481+ MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA);
482+ } else if (dev->wlan.bus_type == MTK_BUS_TYPE_AXI) {
483+ wed_set(dev, MTK_WED_WPDMA_INT_CTRL,
484+ MTK_WED_WPDMA_INT_CTRL_SIG_SRC |
485+ FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_SRC_SEL, 0));
486+ }
487+ return;
488+}
489+
490+static void
491+mtk_wed_set_wpdma(struct mtk_wed_device *dev)
492+{
493+ if (dev->ver > MTK_WED_V1) {
494+ wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_int);
495+ wed_w32(dev, MTK_WED_WPDMA_CFG_INT_MASK, dev->wlan.wpdma_mask);
496+ wed_w32(dev, MTK_WED_WPDMA_CFG_TX, dev->wlan.wpdma_tx);
497+ wed_w32(dev, MTK_WED_WPDMA_CFG_TX_FREE, dev->wlan.wpdma_txfree);
498+ } else {
499+ wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys);
500+ }
501+}
502+
503 static void
504 mtk_wed_hw_init_early(struct mtk_wed_device *dev)
505 {
506 u32 mask, set;
507- u32 offset;
508
509 mtk_wed_stop(dev);
510 mtk_wed_reset(dev, MTK_WED_RESET_WED);
511
512+ if (dev->ver > MTK_WED_V1)
513+ mtk_wed_bus_init(dev);
514+
515+ mtk_wed_set_wpdma(dev);
516+
517 mask = MTK_WED_WDMA_GLO_CFG_BT_SIZE |
518 MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE |
519 MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE;
520@@ -311,30 +527,54 @@ mtk_wed_hw_init_early(struct mtk_wed_device *dev)
521 MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY;
522 wed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set);
523
524- wdma_set(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_RX_INFO_PRERES);
525+ if (dev->ver == MTK_WED_V1) {
526+ u32 offset;
527+ offset = dev->hw->index ? 0x04000400 : 0;
528+ wed_w32(dev, MTK_WED_WDMA_OFFSET0, 0x2a042a20 + offset);
529+ wed_w32(dev, MTK_WED_WDMA_OFFSET1, 0x29002800 + offset);
530
531- offset = dev->hw->index ? 0x04000400 : 0;
532- wed_w32(dev, MTK_WED_WDMA_OFFSET0, 0x2a042a20 + offset);
533- wed_w32(dev, MTK_WED_WDMA_OFFSET1, 0x29002800 + offset);
534+ wed_w32(dev, MTK_WED_PCIE_CFG_BASE, MTK_PCIE_BASE(dev->hw->index));
535+ } else {
536+ wed_w32(dev, MTK_WED_WDMA_CFG_BASE, dev->hw->wdma_phy);
537+ wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_ETH_DMAD_FMT);
538+ wed_w32(dev, MTK_WED_WDMA_OFFSET0,
539+ FIELD_PREP(MTK_WED_WDMA_OFST0_GLO_INTS,
540+ MTK_WDMA_INT_STATUS) |
541+ FIELD_PREP(MTK_WED_WDMA_OFST0_GLO_CFG,
542+ MTK_WDMA_GLO_CFG));
543+
544+ wed_w32(dev, MTK_WED_WDMA_OFFSET1,
545+ FIELD_PREP(MTK_WED_WDMA_OFST1_TX_CTRL,
546+ MTK_WDMA_RING_TX(0)) |
547+ FIELD_PREP(MTK_WED_WDMA_OFST1_RX_CTRL,
548+ MTK_WDMA_RING_RX(0)));
549+ }
550
551- wed_w32(dev, MTK_WED_PCIE_CFG_BASE, MTK_PCIE_BASE(dev->hw->index));
552- wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys);
553 }
554
555 static void
556 mtk_wed_hw_init(struct mtk_wed_device *dev)
557 {
558+ int size = dev->buf_ring.size;
559+ int rev_size = MTK_WED_TX_RING_SIZE / 2;
560+ int thr = 1;
561+
562 if (dev->init_done)
563 return;
564
565 dev->init_done = true;
566 mtk_wed_set_ext_int(dev, false);
567+
568+ if (dev->ver > MTK_WED_V1) {
569+ size = MTK_WED_WDMA_RING_SIZE * 2 + dev->buf_ring.size;
570+ rev_size = size;
571+ thr = 0;
572+ }
573+
574 wed_w32(dev, MTK_WED_TX_BM_CTRL,
575 MTK_WED_TX_BM_CTRL_PAUSE |
576- FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM,
577- dev->buf_ring.size / 128) |
578- FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM,
579- MTK_WED_TX_RING_SIZE / 256));
580+ FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM, size / 128) |
581+ FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM, rev_size / 128));
582
583 wed_w32(dev, MTK_WED_TX_BM_BASE, dev->buf_ring.desc_phys);
584
585@@ -347,28 +587,38 @@ mtk_wed_hw_init(struct mtk_wed_device *dev)
586 wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE);
587
588 wed_w32(dev, MTK_WED_TX_BM_DYN_THR,
589- FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO, 1) |
590+ FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO, thr) |
591 MTK_WED_TX_BM_DYN_THR_HI);
592
593+ if (dev->ver > MTK_WED_V1) {
594+ wed_w32(dev, MTK_WED_TX_TKID_CTRL,
595+ MTK_WED_TX_TKID_CTRL_PAUSE |
596+ FIELD_PREP(MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM,
597+ dev->buf_ring.size / 128) |
598+ FIELD_PREP(MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM,
599+ dev->buf_ring.size / 128));
600+ wed_w32(dev, MTK_WED_TX_TKID_DYN_THR,
601+ FIELD_PREP(MTK_WED_TX_TKID_DYN_THR_LO, 0) |
602+ MTK_WED_TX_TKID_DYN_THR_HI);
603+ }
604 mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
605
606- wed_set(dev, MTK_WED_CTRL,
607- MTK_WED_CTRL_WED_TX_BM_EN |
608- MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
609-
610 wed_clr(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_PAUSE);
611+ if (dev->ver > MTK_WED_V1)
612+ wed_clr(dev, MTK_WED_TX_TKID_CTRL, MTK_WED_TX_TKID_CTRL_PAUSE);
613 }
614
615 static void
616-mtk_wed_ring_reset(struct mtk_wdma_desc *desc, int size)
617+mtk_wed_ring_reset(struct mtk_wdma_desc *desc, int size, int scale)
618 {
619 int i;
620
621 for (i = 0; i < size; i++) {
622- desc[i].buf0 = 0;
623- desc[i].ctrl = cpu_to_le32(MTK_WDMA_DESC_CTRL_DMA_DONE);
624- desc[i].buf1 = 0;
625- desc[i].info = 0;
626+ desc->buf0 = 0;
627+ desc->ctrl = cpu_to_le32(MTK_WDMA_DESC_CTRL_DMA_DONE);
628+ desc->buf1 = 0;
629+ desc->info = 0;
630+ desc += scale;
631 }
632 }
633
634@@ -424,7 +674,7 @@ mtk_wed_reset_dma(struct mtk_wed_device *dev)
635 if (!desc)
636 continue;
637
638- mtk_wed_ring_reset(desc, MTK_WED_TX_RING_SIZE);
639+ mtk_wed_ring_reset(desc, MTK_WED_TX_RING_SIZE, dev->ver);
640 }
641
642 if (mtk_wed_poll_busy(dev))
643@@ -481,16 +731,16 @@ mtk_wed_reset_dma(struct mtk_wed_device *dev)
644
645 static int
646 mtk_wed_ring_alloc(struct mtk_wed_device *dev, struct mtk_wed_ring *ring,
647- int size)
648+ int size, int scale)
649 {
650 ring->desc = dma_alloc_coherent(dev->hw->dev,
651- size * sizeof(*ring->desc),
652+ size * sizeof(*ring->desc) * scale,
653 &ring->desc_phys, GFP_KERNEL);
654 if (!ring->desc)
655 return -ENOMEM;
656
657 ring->size = size;
658- mtk_wed_ring_reset(ring->desc, size);
659+ mtk_wed_ring_reset(ring->desc, size, scale);
660
661 return 0;
662 }
663@@ -500,7 +750,7 @@ mtk_wed_wdma_ring_setup(struct mtk_wed_device *dev, int idx, int size)
664 {
665 struct mtk_wed_ring *wdma = &dev->tx_wdma[idx];
666
667- if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE))
668+ if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE, dev->ver))
669 return -ENOMEM;
670
671 wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,
672@@ -521,60 +771,36 @@ static void
673 mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask)
674 {
675 u32 wdma_mask;
676- u32 val;
677 int i;
678
679 for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)
680 if (!dev->tx_wdma[i].desc)
681 mtk_wed_wdma_ring_setup(dev, i, 16);
682
683- wdma_mask = FIELD_PREP(MTK_WDMA_INT_MASK_RX_DONE, GENMASK(1, 0));
684
685 mtk_wed_hw_init(dev);
686
687- wed_set(dev, MTK_WED_CTRL,
688- MTK_WED_CTRL_WDMA_INT_AGENT_EN |
689- MTK_WED_CTRL_WPDMA_INT_AGENT_EN |
690- MTK_WED_CTRL_WED_TX_BM_EN |
691- MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
692-
693- wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, MTK_WED_PCIE_INT_TRIGGER_STATUS);
694+ mtk_wed_set_int(dev, irq_mask);
695
696- wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER,
697- MTK_WED_WPDMA_INT_TRIGGER_RX_DONE |
698- MTK_WED_WPDMA_INT_TRIGGER_TX_DONE);
699-
700- wed_set(dev, MTK_WED_WPDMA_INT_CTRL,
701- MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
702-
703- wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, wdma_mask);
704- wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask);
705-
706- wdma_w32(dev, MTK_WDMA_INT_MASK, wdma_mask);
707- wdma_w32(dev, MTK_WDMA_INT_GRP2, wdma_mask);
708
709- wed_w32(dev, MTK_WED_WPDMA_INT_MASK, irq_mask);
710- wed_w32(dev, MTK_WED_INT_MASK, irq_mask);
711+ mtk_wed_set_ext_int(dev, true);
712
713- wed_set(dev, MTK_WED_GLO_CFG,
714- MTK_WED_GLO_CFG_TX_DMA_EN |
715- MTK_WED_GLO_CFG_RX_DMA_EN);
716- wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
717- MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
718- MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);
719- wed_set(dev, MTK_WED_WDMA_GLO_CFG,
720- MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
721+ if (dev->ver == MTK_WED_V1) {
722+ u32 val;
723
724- mtk_wed_set_ext_int(dev, true);
725- val = dev->wlan.wpdma_phys |
726- MTK_PCIE_MIRROR_MAP_EN |
727- FIELD_PREP(MTK_PCIE_MIRROR_MAP_WED_ID, dev->hw->index);
728+ val = dev->wlan.wpdma_phys |
729+ MTK_PCIE_MIRROR_MAP_EN |
730+ FIELD_PREP(MTK_PCIE_MIRROR_MAP_WED_ID, dev->hw->index);
731
732- if (dev->hw->index)
733- val |= BIT(1);
734- val |= BIT(0);
735- regmap_write(dev->hw->mirror, dev->hw->index * 4, val);
736+ if (dev->hw->index)
737+ val |= BIT(1);
738+ val |= BIT(0);
739+ regmap_write(dev->hw->mirror, dev->hw->index * 4, val);
740+ } else {
741+ mtk_wed_set_512_support(dev, true);
742+ }
743
744+ mtk_wed_dma_enable(dev);
745 dev->running = true;
746 }
747
748@@ -588,15 +814,11 @@ mtk_wed_attach(struct mtk_wed_device *dev)
749 RCU_LOCKDEP_WARN(!rcu_read_lock_held(),
750 "mtk_wed_attach without holding the RCU read lock");
751
752- if (pci_domain_nr(dev->wlan.pci_dev->bus) > 1 ||
753- !try_module_get(THIS_MODULE))
754- ret = -ENODEV;
755+ if (!try_module_get(THIS_MODULE))
756+ return -ENODEV;
757
758 rcu_read_unlock();
759
760- if (ret)
761- return ret;
762-
763 mutex_lock(&hw_lock);
764
765 hw = mtk_wed_assign(dev);
766@@ -606,8 +828,6 @@ mtk_wed_attach(struct mtk_wed_device *dev)
767 goto out;
768 }
769
770- dev_info(&dev->wlan.pci_dev->dev, "attaching wed device %d\n", hw->index);
771-
772 dev->hw = hw;
773 dev->dev = hw->dev;
774 dev->irq = hw->irq;
775@@ -617,6 +837,9 @@ mtk_wed_attach(struct mtk_wed_device *dev)
776 of_dma_is_coherent(hw->eth->dev->of_node))
777 mtk_eth_set_dma_device(hw->eth, hw->dev);
778
779+ dev->ver = FIELD_GET(MTK_WED_REV_ID_MAJOR,
780+ wed_r32(dev, MTK_WED_REV_ID));
781+
782 ret = mtk_wed_buffer_alloc(dev);
783 if (ret) {
784 mtk_wed_detach(dev);
785@@ -624,7 +847,10 @@ mtk_wed_attach(struct mtk_wed_device *dev)
786 }
787
788 mtk_wed_hw_init_early(dev);
789- regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP, BIT(hw->index), 0);
790+
791+ if (dev->ver == MTK_WED_V1)
792+ regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP,
793+ BIT(hw->index), 0);
794
795 out:
796 mutex_unlock(&hw_lock);
797@@ -651,7 +877,7 @@ mtk_wed_tx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs)
798
799 BUG_ON(idx > ARRAY_SIZE(dev->tx_ring));
800
801- if (mtk_wed_ring_alloc(dev, ring, MTK_WED_TX_RING_SIZE))
802+ if (mtk_wed_ring_alloc(dev, ring, MTK_WED_TX_RING_SIZE, 1))
803 return -ENOMEM;
804
805 if (mtk_wed_wdma_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE))
806@@ -678,21 +904,24 @@ static int
807 mtk_wed_txfree_ring_setup(struct mtk_wed_device *dev, void __iomem *regs)
808 {
809 struct mtk_wed_ring *ring = &dev->txfree_ring;
810- int i;
811+ int i, idx = 1;
812+
813+ if(dev->ver > MTK_WED_V1)
814+ idx = 0;
815
816 /*
817 * For txfree event handling, the same DMA ring is shared between WED
818 * and WLAN. The WLAN driver accesses the ring index registers through
819 * WED
820 */
821- ring->reg_base = MTK_WED_RING_RX(1);
822+ ring->reg_base = MTK_WED_RING_RX(idx);
823 ring->wpdma = regs;
824
825 for (i = 0; i < 12; i += 4) {
826 u32 val = readl(regs + i);
827
828- wed_w32(dev, MTK_WED_RING_RX(1) + i, val);
829- wed_w32(dev, MTK_WED_WPDMA_RING_RX(1) + i, val);
830+ wed_w32(dev, MTK_WED_RING_RX(idx) + i, val);
831+ wed_w32(dev, MTK_WED_WPDMA_RING_RX(idx) + i, val);
832 }
833
834 return 0;
835@@ -706,10 +935,8 @@ mtk_wed_irq_get(struct mtk_wed_device *dev, u32 mask)
836 val = wed_r32(dev, MTK_WED_EXT_INT_STATUS);
837 wed_w32(dev, MTK_WED_EXT_INT_STATUS, val);
838 val &= MTK_WED_EXT_INT_STATUS_ERROR_MASK;
839- if (!dev->hw->num_flows)
840- val &= ~MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD;
841- if (val && net_ratelimit())
842- pr_err("mtk_wed%d: error status=%08x\n", dev->hw->index, val);
843+ WARN_RATELIMIT(val, "mtk_wed%d: error status=%08x\n",
844+ dev->hw->index, val);
845
846 val = wed_r32(dev, MTK_WED_INT_STATUS);
847 val &= mask;
848@@ -780,7 +1007,8 @@ out:
849 }
850
851 void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
852- void __iomem *wdma, int index)
853+ void __iomem *wdma, u32 wdma_phy, int index)
854+
855 {
856 static const struct mtk_wed_ops wed_ops = {
857 .attach = mtk_wed_attach,
858@@ -830,21 +1058,27 @@ void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
859 hw->eth = eth;
860 hw->dev = &pdev->dev;
861 hw->wdma = wdma;
862+ hw->wdma_phy = wdma_phy;
863 hw->index = index;
864 hw->irq = irq;
865- hw->mirror = syscon_regmap_lookup_by_phandle(eth_np,
866- "mediatek,pcie-mirror");
867- hw->hifsys = syscon_regmap_lookup_by_phandle(eth_np,
868- "mediatek,hifsys");
869- if (IS_ERR(hw->mirror) || IS_ERR(hw->hifsys)) {
870- kfree(hw);
871- goto unlock;
872- }
873
874- if (!index) {
875- regmap_write(hw->mirror, 0, 0);
876- regmap_write(hw->mirror, 4, 0);
877+ if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
878+ hw->mirror = syscon_regmap_lookup_by_phandle(eth_np,
879+ "mediatek,pcie-mirror");
880+ hw->hifsys = syscon_regmap_lookup_by_phandle(eth_np,
881+ "mediatek,hifsys");
882+
883+ if (IS_ERR(hw->mirror) || IS_ERR(hw->hifsys)) {
884+ kfree(hw);
885+ goto unlock;
886+ }
887+
888+ if (!index) {
889+ regmap_write(hw->mirror, 0, 0);
890+ regmap_write(hw->mirror, 4, 0);
891+ }
892 }
893+
894 mtk_wed_hw_add_debugfs(hw);
895
896 hw_list[index] = hw;
897diff --git a/drivers/net/ethernet/mediatek/mtk_wed.h b/drivers/net/ethernet/mediatek/mtk_wed.h
898index 981ec613f..9b17b7405 100644
899--- a/drivers/net/ethernet/mediatek/mtk_wed.h
900+++ b/drivers/net/ethernet/mediatek/mtk_wed.h
901@@ -8,6 +8,19 @@
902 #include <linux/debugfs.h>
903 #include <linux/regmap.h>
904 #include <linux/netdevice.h>
905+#define MTK_PCIE_BASE(n) (0x1a143000 + (n) * 0x2000)
906+
907+#define MTK_WED_PKT_SIZE 1900
908+#define MTK_WED_BUF_SIZE 2048
909+#define MTK_WED_BUF_PER_PAGE (PAGE_SIZE / 2048)
910+
911+#define MTK_WED_TX_RING_SIZE 2048
912+#define MTK_WED_WDMA_RING_SIZE 512
913+#define MTK_WED_MAX_GROUP_SIZE 0x100
914+#define MTK_WED_VLD_GROUP_SIZE 0x40
915+#define MTK_WED_PER_GROUP_PKT 128
916+
917+#define MTK_WED_FBUF_SIZE 128
918
919 struct mtk_eth;
920
921@@ -23,6 +36,7 @@ struct mtk_wed_hw {
922 struct mtk_wed_device *wed_dev;
923 u32 debugfs_reg;
924 u32 num_flows;
925+ u32 wdma_phy;
926 char dirname[5];
927 int irq;
928 int index;
929@@ -101,14 +115,14 @@ wpdma_txfree_w32(struct mtk_wed_device *dev, u32 reg, u32 val)
930 }
931
932 void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
933- void __iomem *wdma, int index);
934+ void __iomem *wdma, u32 wdma_phy, int index);
935 void mtk_wed_exit(void);
936 int mtk_wed_flow_add(int index);
937 void mtk_wed_flow_remove(int index);
938 #else
939 static inline void
940 mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
941- void __iomem *wdma, int index)
942+ void __iomem *wdma, u32 wdma_phy, int index)
943 {
944 }
945 static inline void
946diff --git a/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
947index a81d3fd1a..f420f187e 100644
948--- a/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
949+++ b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
950@@ -116,6 +116,9 @@ wed_txinfo_show(struct seq_file *s, void *data)
951 DUMP_WDMA(WDMA_GLO_CFG),
952 DUMP_WDMA_RING(WDMA_RING_RX(0)),
953 DUMP_WDMA_RING(WDMA_RING_RX(1)),
954+
955+ DUMP_STR("TX FREE"),
956+ DUMP_WED(WED_RX_MIB(0)),
957 };
958 struct mtk_wed_hw *hw = s->private;
959 struct mtk_wed_device *dev = hw->wed_dev;
960diff --git a/drivers/net/ethernet/mediatek/mtk_wed_regs.h b/drivers/net/ethernet/mediatek/mtk_wed_regs.h
961index 0a0465ea5..69f136ed4 100644
962--- a/drivers/net/ethernet/mediatek/mtk_wed_regs.h
963+++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h
964@@ -4,9 +4,15 @@
965 #ifndef __MTK_WED_REGS_H
966 #define __MTK_WED_REGS_H
967
968+#if defined(CONFIG_MEDIATEK_NETSYS_V2)
969+#define MTK_WDMA_DESC_CTRL_LEN1 GENMASK(13, 0)
970+#define MTK_WDMA_DESC_CTRL_LAST_SEG1 BIT(14)
971+#define MTK_WDMA_DESC_CTRL_BURST BIT(15)
972+#else
973 #define MTK_WDMA_DESC_CTRL_LEN1 GENMASK(14, 0)
974 #define MTK_WDMA_DESC_CTRL_LAST_SEG1 BIT(15)
975 #define MTK_WDMA_DESC_CTRL_BURST BIT(16)
976+#endif
977 #define MTK_WDMA_DESC_CTRL_LEN0 GENMASK(29, 16)
978 #define MTK_WDMA_DESC_CTRL_LAST_SEG0 BIT(30)
979 #define MTK_WDMA_DESC_CTRL_DMA_DONE BIT(31)
980@@ -18,6 +24,10 @@ struct mtk_wdma_desc {
981 __le32 info;
982 } __packed __aligned(4);
983
984+#define MTK_WED_REV_ID 0x004
985+#define MTK_WED_REV_ID_MAJOR GENMASK(31, 28)
986+#define MTK_WED_REV_ID_MINOR GENMASK(27, 16)
987+
988 #define MTK_WED_RESET 0x008
989 #define MTK_WED_RESET_TX_BM BIT(0)
990 #define MTK_WED_RESET_TX_FREE_AGENT BIT(4)
991@@ -41,6 +51,7 @@ struct mtk_wdma_desc {
992 #define MTK_WED_CTRL_RESERVE_EN BIT(12)
993 #define MTK_WED_CTRL_RESERVE_BUSY BIT(13)
994 #define MTK_WED_CTRL_FINAL_DIDX_READ BIT(24)
995+#define MTK_WED_CTRL_ETH_DMAD_FMT BIT(25)
996 #define MTK_WED_CTRL_MIB_READ_CLEAR BIT(28)
997
998 #define MTK_WED_EXT_INT_STATUS 0x020
999@@ -49,6 +60,10 @@ struct mtk_wdma_desc {
1000 #define MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID BIT(4)
1001 #define MTK_WED_EXT_INT_STATUS_TX_FBUF_LO_TH BIT(8)
1002 #define MTK_WED_EXT_INT_STATUS_TX_FBUF_HI_TH BIT(9)
1003+#if defined(CONFIG_MEDIATEK_NETSYS_V2)
1004+#define MTK_WED_EXT_INT_STATUS_TX_TKID_LO_TH BIT(10)
1005+#define MTK_WED_EXT_INT_STATUS_TX_TKID_HI_TH BIT(11)
1006+#endif
1007 #define MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH BIT(12)
1008 #define MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH BIT(13)
1009 #define MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR BIT(16)
1010@@ -57,16 +72,24 @@ struct mtk_wdma_desc {
1011 #define MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN BIT(19)
1012 #define MTK_WED_EXT_INT_STATUS_RX_DRV_BM_DMAD_COHERENT BIT(20)
1013 #define MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR BIT(21)
1014-#define MTK_WED_EXT_INT_STATUS_TX_DRV_W_RESP_ERR BIT(22)
1015+#define MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR BIT(22)
1016+#define MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR BIT(23)
1017 #define MTK_WED_EXT_INT_STATUS_RX_DRV_DMA_RECYCLE BIT(24)
1018+#define MTK_WED_EXT_INT_STATUS_RX_DRV_GET_BM_DMAD_SKIP BIT(25)
1019+#define MTK_WED_EXT_INT_STATUS_WPDMA_RX_D_DRV_ERR BIT(26)
1020+#define MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY BIT(27)
1021+
1022 #define MTK_WED_EXT_INT_STATUS_ERROR_MASK (MTK_WED_EXT_INT_STATUS_TF_LEN_ERR | \
1023 MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD | \
1024 MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID | \
1025+ MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH | \
1026+ MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH | \
1027 MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR | \
1028 MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR | \
1029+ MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT | \
1030 MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN | \
1031- MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR | \
1032- MTK_WED_EXT_INT_STATUS_TX_DRV_W_RESP_ERR)
1033+ MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR | \
1034+ MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR)
1035
1036 #define MTK_WED_EXT_INT_MASK 0x028
1037
1038@@ -80,10 +103,6 @@ struct mtk_wdma_desc {
1039
1040 #define MTK_WED_TX_BM_BASE 0x084
1041
1042-#define MTK_WED_TX_BM_TKID 0x088
1043-#define MTK_WED_TX_BM_TKID_START GENMASK(15, 0)
1044-#define MTK_WED_TX_BM_TKID_END GENMASK(31, 16)
1045-
1046 #define MTK_WED_TX_BM_BUF_LEN 0x08c
1047
1048 #define MTK_WED_TX_BM_INTF 0x09c
1049@@ -93,9 +112,38 @@ struct mtk_wdma_desc {
1050 #define MTK_WED_TX_BM_INTF_TKID_READ BIT(29)
1051
1052 #define MTK_WED_TX_BM_DYN_THR 0x0a0
1053+#if defined(CONFIG_MEDIATEK_NETSYS_V2)
1054+#define MTK_WED_TX_BM_DYN_THR_LO GENMASK(8, 0)
1055+#define MTK_WED_TX_BM_DYN_THR_HI GENMASK(24, 16)
1056+
1057+#define MTK_WED_TX_BM_TKID 0x0c8
1058+#define MTK_WED_TX_BM_TKID_START GENMASK(15, 0)
1059+#define MTK_WED_TX_BM_TKID_END GENMASK(31, 16)
1060+#else
1061 #define MTK_WED_TX_BM_DYN_THR_LO GENMASK(6, 0)
1062 #define MTK_WED_TX_BM_DYN_THR_HI GENMASK(22, 16)
1063
1064+#define MTK_WED_TX_BM_TKID 0x088
1065+#define MTK_WED_TX_BM_TKID_START GENMASK(15, 0)
1066+#define MTK_WED_TX_BM_TKID_END GENMASK(31, 16)
1067+#endif
1068+
1069+#define MTK_WED_TX_TKID_CTRL 0x0c0
1070+#define MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM GENMASK(6, 0)
1071+#define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM GENMASK(22, 16)
1072+#define MTK_WED_TX_TKID_CTRL_PAUSE BIT(28)
1073+
1074+#define MTK_WED_TX_TKID_DYN_THR 0x0e0
1075+#define MTK_WED_TX_TKID_DYN_THR_LO GENMASK(6, 0)
1076+#define MTK_WED_TX_TKID_DYN_THR_HI GENMASK(22, 16)
1077+
1078+#define MTK_WED_TXP_DW0 0x120
1079+#define MTK_WED_TXP_DW1 0x124
1080+#define MTK_WED_WPDMA_WRITE_TXP GENMASK(31, 16)
1081+#define MTK_WED_TXDP_CTRL 0x130
1082+#define MTK_WED_TXDP_DW9_OVERWR BIT(9)
1083+#define MTK_WED_RX_BM_TKID_MIB 0x1cc
1084+
1085 #define MTK_WED_INT_STATUS 0x200
1086 #define MTK_WED_INT_MASK 0x204
1087
1088@@ -125,6 +173,7 @@ struct mtk_wdma_desc {
1089 #define MTK_WED_RESET_IDX_RX GENMASK(17, 16)
1090
1091 #define MTK_WED_TX_MIB(_n) (0x2a0 + (_n) * 4)
1092+#define MTK_WED_RX_MIB(_n) (0x2e0 + (_n) * 4)
1093
1094 #define MTK_WED_RING_TX(_n) (0x300 + (_n) * 0x10)
1095
1096@@ -139,6 +188,19 @@ struct mtk_wdma_desc {
1097 #define MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY BIT(1)
1098 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN BIT(2)
1099 #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_BUSY BIT(3)
1100+/* CONFIG_MEDIATEK_NETSYS_V2 */
1101+#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC BIT(4)
1102+#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_PKT_PROC BIT(5)
1103+#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC BIT(6)
1104+#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_CRX_SYNC BIT(7)
1105+#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_VER GENMASK(18, 16)
1106+#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNSUPPORT_FMT BIT(19)
1107+#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UEVENT_PKT_FMT_CHK BIT(20)
1108+#define MTK_WED_WPDMA_GLO_CFG_RX_DDONE2_WR BIT(21)
1109+#define MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP BIT(24)
1110+#define MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV BIT(28)
1111+
1112+/* CONFIG_MEDIATEK_NETSYS_V1 */
1113 #define MTK_WED_WPDMA_GLO_CFG_RX_BT_SIZE GENMASK(5, 4)
1114 #define MTK_WED_WPDMA_GLO_CFG_TX_WB_DDONE BIT(6)
1115 #define MTK_WED_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7)
1116@@ -152,24 +214,54 @@ struct mtk_wdma_desc {
1117 #define MTK_WED_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY BIT(26)
1118 #define MTK_WED_WPDMA_GLO_CFG_OMIT_RX_INFO BIT(27)
1119 #define MTK_WED_WPDMA_GLO_CFG_OMIT_TX_INFO BIT(28)
1120+
1121 #define MTK_WED_WPDMA_GLO_CFG_BYTE_SWAP BIT(29)
1122+#define MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK BIT(30)
1123 #define MTK_WED_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31)
1124
1125 #define MTK_WED_WPDMA_RESET_IDX 0x50c
1126 #define MTK_WED_WPDMA_RESET_IDX_TX GENMASK(3, 0)
1127 #define MTK_WED_WPDMA_RESET_IDX_RX GENMASK(17, 16)
1128
1129+#define MTK_WED_WPDMA_CTRL 0x518
1130+#define MTK_WED_WPDMA_CTRL_SDL1_FIXED BIT(31)
1131+
1132 #define MTK_WED_WPDMA_INT_CTRL 0x520
1133 #define MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV BIT(21)
1134+#define MTK_WED_WPDMA_INT_CTRL_SIG_SRC BIT(22)
1135+#define MTK_WED_WPDMA_INT_CTRL_SRC_SEL GENMASK(17, 16)
1136
1137 #define MTK_WED_WPDMA_INT_MASK 0x524
1138
1139-#define MTK_WED_PCIE_CFG_BASE 0x560
1140+#define MTK_WED_WPDMA_INT_CTRL_TX 0x530
1141+#define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN BIT(0)
1142+#define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_CLR BIT(1)
1143+#define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_TRIG GENMASK(6, 2)
1144+#define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_EN BIT(8)
1145+#define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_CLR BIT(9)
1146+#define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_TRIG GENMASK(14, 10)
1147+
1148+#define MTK_WED_WPDMA_INT_CTRL_RX 0x534
1149+
1150+#define MTK_WED_WPDMA_INT_CTRL_TX_FREE 0x538
1151+#define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_EN BIT(0)
1152+#define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_CLR BIT(1)
1153+#define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG GENMASK(6, 2)
1154
1155+#define MTK_WED_PCIE_CFG_BASE 0x560
1156+#define MTK_WED_PCIE_CFG_INTM 0x564
1157+#define MTK_WED_PCIE_CFG_MSIS 0x568
1158 #define MTK_WED_PCIE_INT_TRIGGER 0x570
1159 #define MTK_WED_PCIE_INT_TRIGGER_STATUS BIT(16)
1160
1161+#define MTK_WED_PCIE_INT_CTRL 0x57c
1162+#define MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA BIT(20)
1163+#define MTK_WED_PCIE_INT_CTRL_SRC_SEL GENMASK(17, 16)
1164+#define MTK_WED_PCIE_INT_CTRL_POLL_EN GENMASK(13, 12)
1165 #define MTK_WED_WPDMA_CFG_BASE 0x580
1166+#define MTK_WED_WPDMA_CFG_INT_MASK 0x584
1167+#define MTK_WED_WPDMA_CFG_TX 0x588
1168+#define MTK_WED_WPDMA_CFG_TX_FREE 0x58c
1169
1170 #define MTK_WED_WPDMA_TX_MIB(_n) (0x5a0 + (_n) * 4)
1171 #define MTK_WED_WPDMA_TX_COHERENT_MIB(_n) (0x5d0 + (_n) * 4)
1172@@ -203,14 +295,22 @@ struct mtk_wdma_desc {
1173 #define MTK_WED_WDMA_RESET_IDX_RX GENMASK(17, 16)
1174 #define MTK_WED_WDMA_RESET_IDX_DRV GENMASK(25, 24)
1175
1176+#define MTK_WED_WDMA_INT_CLR 0xa24
1177+#define MTK_WED_WDMA_INT_CLR_RX_DONE GENMASK(17, 16)
1178+
1179 #define MTK_WED_WDMA_INT_TRIGGER 0xa28
1180 #define MTK_WED_WDMA_INT_TRIGGER_RX_DONE GENMASK(17, 16)
1181
1182 #define MTK_WED_WDMA_INT_CTRL 0xa2c
1183-#define MTK_WED_WDMA_INT_CTRL_POLL_SRC_SEL GENMASK(17, 16)
1184+#define MTK_WED_WDMA_INT_POLL_SRC_SEL GENMASK(17, 16)
1185
1186+#define MTK_WED_WDMA_CFG_BASE 0xaa0
1187 #define MTK_WED_WDMA_OFFSET0 0xaa4
1188 #define MTK_WED_WDMA_OFFSET1 0xaa8
1189+#define MTK_WED_WDMA_OFST0_GLO_INTS GENMASK(15, 0)
1190+#define MTK_WED_WDMA_OFST0_GLO_CFG GENMASK(31, 16)
1191+#define MTK_WED_WDMA_OFST1_TX_CTRL GENMASK(15, 0)
1192+#define MTK_WED_WDMA_OFST1_RX_CTRL GENMASK(31, 16)
1193
1194 #define MTK_WED_WDMA_RX_MIB(_n) (0xae0 + (_n) * 4)
1195 #define MTK_WED_WDMA_RX_RECYCLE_MIB(_n) (0xae8 + (_n) * 4)
1196@@ -221,14 +321,21 @@ struct mtk_wdma_desc {
1197 #define MTK_WED_RING_OFS_CPU_IDX 0x08
1198 #define MTK_WED_RING_OFS_DMA_IDX 0x0c
1199
1200+#define MTK_WDMA_RING_TX(_n) (0x000 + (_n) * 0x10)
1201 #define MTK_WDMA_RING_RX(_n) (0x100 + (_n) * 0x10)
1202
1203 #define MTK_WDMA_GLO_CFG 0x204
1204-#define MTK_WDMA_GLO_CFG_RX_INFO_PRERES GENMASK(28, 26)
1205+#define MTK_WDMA_GLO_CFG_TX_DMA_EN BIT(0)
1206+#define MTK_WDMA_GLO_CFG_RX_DMA_EN BIT(2)
1207+#define MTK_WDMA_GLO_CFG_RX_INFO3_PRERES BIT(26)
1208+#define MTK_WDMA_GLO_CFG_RX_INFO2_PRERES BIT(27)
1209+#define MTK_WDMA_GLO_CFG_RX_INFO1_PRERES BIT(28)
1210+
1211
1212 #define MTK_WDMA_RESET_IDX 0x208
1213 #define MTK_WDMA_RESET_IDX_TX GENMASK(3, 0)
1214 #define MTK_WDMA_RESET_IDX_RX GENMASK(17, 16)
1215+#define MTK_WDMA_INT_STATUS 0x220
1216
1217 #define MTK_WDMA_INT_MASK 0x228
1218 #define MTK_WDMA_INT_MASK_TX_DONE GENMASK(3, 0)
1219diff --git a/include/linux/soc/mediatek/mtk_wed.h b/include/linux/soc/mediatek/mtk_wed.h
1220index 7e00cca06..24742604b 100644
1221--- a/include/linux/soc/mediatek/mtk_wed.h
1222+++ b/include/linux/soc/mediatek/mtk_wed.h
1223@@ -8,6 +8,19 @@
1224
1225 #define MTK_WED_TX_QUEUES 2
1226
1227+enum {
1228+ MTK_NO_WED,
1229+ MTK_WED_V1,
1230+ MTK_WED_V2,
1231+ MTK_WED_VMAX
1232+};
1233+
1234+enum {
1235+ MTK_BUS_TYPE_PCIE,
1236+ MTK_BUS_TYPE_AXI,
1237+ MTK_BUS_TYPE_MAX
1238+};
1239+
1240 struct mtk_wed_hw;
1241 struct mtk_wdma_desc;
1242
1243@@ -28,6 +41,7 @@ struct mtk_wed_device {
1244 bool init_done, running;
1245 int wdma_idx;
1246 int irq;
1247+ u8 ver;
1248
1249 struct mtk_wed_ring tx_ring[MTK_WED_TX_QUEUES];
1250 struct mtk_wed_ring txfree_ring;
1251@@ -43,8 +57,19 @@ struct mtk_wed_device {
1252 /* filled by driver: */
1253 struct {
1254 struct pci_dev *pci_dev;
1255-
1256- u32 wpdma_phys;
1257+ void __iomem *base;
1258+ u32 bus_type;
1259+
1260+ union {
1261+ u32 wpdma_phys;
1262+ u32 wpdma_int;
1263+ };
1264+ u32 wpdma_mask;
1265+ u32 wpdma_tx;
1266+ u32 wpdma_txfree;
1267+
1268+ u8 tx_tbit[MTK_WED_TX_QUEUES];
1269+ u8 txfree_tbit;
1270
1271 u16 token_start;
1272 unsigned int nbuf;
1273--
12742.18.0
1275