developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | #include <linux/bitfield.h> |
| 3 | #include <linux/firmware.h> |
| 4 | #include <linux/module.h> |
| 5 | #include <linux/nvmem-consumer.h> |
| 6 | #include <linux/of_address.h> |
| 7 | #include <linux/of_platform.h> |
developer | aec59ea | 2023-04-10 16:58:03 +0800 | [diff] [blame] | 8 | #include <linux/pinctrl/consumer.h> |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 9 | #include <linux/phy.h> |
| 10 | |
| 11 | #define MEDAITEK_2P5GE_PHY_DMB_FW "mediatek-2p5ge-phy-dmb.bin" |
| 12 | #define MEDIATEK_2P5GE_PHY_PMB_FW "mediatek-2p5ge-phy-pmb.bin" |
| 13 | |
| 14 | #define MD32_EN_CFG 0x18 |
| 15 | #define MD32_EN BIT(0) |
| 16 | |
developer | 284cd6e | 2022-12-15 22:19:39 +0800 | [diff] [blame] | 17 | #define BASE100T_STATUS_EXTEND (0x10) |
| 18 | #define BASE1000T_STATUS_EXTEND (0x11) |
| 19 | #define EXTEND_CTRL_AND_STATUS (0x16) |
| 20 | |
developer | e7f6161 | 2022-12-30 11:34:52 +0800 | [diff] [blame] | 21 | #define PHY_AUX_CTRL_STATUS (0x1d) |
| 22 | #define PHY_AUX_DPX_MASK GENMASK(5, 5) |
| 23 | #define PHY_AUX_SPEED_MASK GENMASK(4, 2) |
| 24 | |
developer | 5c0c062 | 2023-04-12 11:51:08 +0800 | [diff] [blame] | 25 | /* Registers on MDIO_MMD_VEND1 */ |
| 26 | #define MTK_PHY_LINK_STATUS_MISC (0xa2) |
| 27 | #define MTK_PHY_FDX_ENABLE BIT(5) |
| 28 | |
developer | aec59ea | 2023-04-10 16:58:03 +0800 | [diff] [blame] | 29 | /* Registers on MDIO_MMD_VEND2 */ |
| 30 | #define MTK_PHY_LED0_ON_CTRL (0x24) |
developer | 813ffc4 | 2023-05-17 13:39:48 +0800 | [diff] [blame] | 31 | #define MTK_PHY_LED0_ON_LINK1000 BIT(0) |
| 32 | #define MTK_PHY_LED0_ON_LINK100 BIT(1) |
| 33 | #define MTK_PHY_LED0_ON_LINK10 BIT(2) |
| 34 | #define MTK_PHY_LED0_ON_LINK2500 BIT(7) |
developer | aec59ea | 2023-04-10 16:58:03 +0800 | [diff] [blame] | 35 | #define MTK_PHY_LED0_POLARITY BIT(14) |
| 36 | |
developer | 813ffc4 | 2023-05-17 13:39:48 +0800 | [diff] [blame] | 37 | #define MTK_PHY_LED1_ON_CTRL (0x26) |
| 38 | #define MTK_PHY_LED1_ON_FDX BIT(4) |
| 39 | #define MTK_PHY_LED1_ON_HDX BIT(5) |
| 40 | #define MTK_PHY_LED1_POLARITY BIT(14) |
| 41 | |
developer | e7f6161 | 2022-12-30 11:34:52 +0800 | [diff] [blame] | 42 | enum { |
| 43 | PHY_AUX_SPD_10 = 0, |
| 44 | PHY_AUX_SPD_100, |
| 45 | PHY_AUX_SPD_1000, |
| 46 | PHY_AUX_SPD_2500, |
| 47 | }; |
| 48 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 49 | static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev) |
| 50 | { |
| 51 | int ret; |
| 52 | int i; |
| 53 | const struct firmware *fw; |
| 54 | struct device *dev = &phydev->mdio.dev; |
| 55 | struct device_node *np; |
| 56 | void __iomem *dmb_addr; |
| 57 | void __iomem *pmb_addr; |
| 58 | void __iomem *mcucsr_base; |
| 59 | u16 reg; |
developer | 813ffc4 | 2023-05-17 13:39:48 +0800 | [diff] [blame] | 60 | struct pinctrl *pinctrl; |
| 61 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 62 | |
| 63 | np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw"); |
| 64 | if (!np) |
| 65 | return -ENOENT; |
| 66 | |
| 67 | dmb_addr = of_iomap(np, 0); |
| 68 | if (!dmb_addr) |
| 69 | return -ENOMEM; |
| 70 | pmb_addr = of_iomap(np, 1); |
| 71 | if (!pmb_addr) |
| 72 | return -ENOMEM; |
| 73 | mcucsr_base = of_iomap(np, 2); |
| 74 | if (!mcucsr_base) |
| 75 | return -ENOMEM; |
| 76 | |
| 77 | ret = request_firmware(&fw, MEDAITEK_2P5GE_PHY_DMB_FW, dev); |
| 78 | if (ret) { |
| 79 | dev_err(dev, "failed to load firmware: %s, ret: %d\n", |
| 80 | MEDAITEK_2P5GE_PHY_DMB_FW, ret); |
| 81 | return ret; |
| 82 | } |
| 83 | for (i = 0; i < fw->size - 1; i += 4) |
| 84 | writel(*((uint32_t *)(fw->data + i)), dmb_addr + i); |
| 85 | release_firmware(fw); |
| 86 | |
| 87 | ret = request_firmware(&fw, MEDIATEK_2P5GE_PHY_PMB_FW, dev); |
| 88 | if (ret) { |
| 89 | dev_err(dev, "failed to load firmware: %s, ret: %d\n", |
| 90 | MEDIATEK_2P5GE_PHY_PMB_FW, ret); |
| 91 | return ret; |
| 92 | } |
| 93 | for (i = 0; i < fw->size - 1; i += 4) |
| 94 | writel(*((uint32_t *)(fw->data + i)), pmb_addr + i); |
| 95 | release_firmware(fw); |
| 96 | |
| 97 | reg = readw(mcucsr_base + MD32_EN_CFG); |
| 98 | writew(reg | MD32_EN, mcucsr_base + MD32_EN_CFG); |
| 99 | dev_info(dev, "Firmware loading/trigger ok.\n"); |
| 100 | |
developer | 813ffc4 | 2023-05-17 13:39:48 +0800 | [diff] [blame] | 101 | /* Setup LED */ |
| 102 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL, |
| 103 | MTK_PHY_LED0_POLARITY | MTK_PHY_LED0_ON_LINK10 | |
| 104 | MTK_PHY_LED0_ON_LINK100 | MTK_PHY_LED0_ON_LINK1000 | |
| 105 | MTK_PHY_LED0_ON_LINK2500); |
| 106 | phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL, |
| 107 | MTK_PHY_LED1_ON_FDX | MTK_PHY_LED1_ON_HDX); |
| 108 | |
| 109 | pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led"); |
| 110 | if (IS_ERR(pinctrl)) { |
| 111 | dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n"); |
| 112 | return PTR_ERR(pinctrl); |
| 113 | } |
| 114 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 115 | return 0; |
| 116 | } |
| 117 | |
developer | 1302b25 | 2022-12-30 19:04:55 +0800 | [diff] [blame] | 118 | static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev) |
| 119 | { |
| 120 | bool changed = false; |
| 121 | u32 adv; |
| 122 | int ret; |
| 123 | |
| 124 | if (phydev->autoneg == AUTONEG_DISABLE) { |
| 125 | /* Configure half duplex with genphy_setup_forced, |
| 126 | * because genphy_c45_pma_setup_forced does not support. |
| 127 | */ |
| 128 | return phydev->duplex != DUPLEX_FULL |
| 129 | ? genphy_setup_forced(phydev) |
| 130 | : genphy_c45_pma_setup_forced(phydev); |
| 131 | } |
| 132 | |
| 133 | ret = genphy_c45_an_config_aneg(phydev); |
| 134 | if (ret < 0) |
| 135 | return ret; |
| 136 | if (ret > 0) |
| 137 | changed = true; |
| 138 | |
| 139 | adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); |
| 140 | ret = phy_modify_changed(phydev, MII_CTRL1000, |
| 141 | ADVERTISE_1000FULL | ADVERTISE_1000HALF, |
| 142 | adv); |
| 143 | if (ret < 0) |
| 144 | return ret; |
| 145 | if (ret > 0) |
| 146 | changed = true; |
| 147 | |
| 148 | return genphy_c45_check_and_restart_aneg(phydev, changed); |
| 149 | } |
| 150 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 151 | static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev) |
| 152 | { |
| 153 | int ret; |
| 154 | |
| 155 | ret = genphy_read_abilities(phydev); |
| 156 | if (ret) |
| 157 | return ret; |
| 158 | |
developer | d4abc8c | 2022-10-28 10:45:36 +0800 | [diff] [blame] | 159 | /* We don't support HDX at MAC layer on mt798x. |
| 160 | * So mask phy's HDX capabilities, too. |
| 161 | */ |
| 162 | linkmode_set_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 163 | phydev->supported); |
| 164 | linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, |
| 165 | phydev->supported); |
| 166 | linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, |
| 167 | phydev->supported); |
| 168 | linkmode_set_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, |
| 169 | phydev->supported); |
| 170 | linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); |
| 171 | |
| 172 | return 0; |
| 173 | } |
| 174 | |
developer | 284cd6e | 2022-12-15 22:19:39 +0800 | [diff] [blame] | 175 | static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev) |
| 176 | { |
| 177 | int ret; |
developer | 284cd6e | 2022-12-15 22:19:39 +0800 | [diff] [blame] | 178 | |
developer | e7f6161 | 2022-12-30 11:34:52 +0800 | [diff] [blame] | 179 | ret = genphy_update_link(phydev); |
| 180 | if (ret) |
| 181 | return ret; |
developer | 284cd6e | 2022-12-15 22:19:39 +0800 | [diff] [blame] | 182 | |
developer | e7f6161 | 2022-12-30 11:34:52 +0800 | [diff] [blame] | 183 | phydev->speed = SPEED_UNKNOWN; |
| 184 | phydev->duplex = DUPLEX_UNKNOWN; |
| 185 | phydev->pause = 0; |
| 186 | phydev->asym_pause = 0; |
developer | 284cd6e | 2022-12-15 22:19:39 +0800 | [diff] [blame] | 187 | |
developer | e7f6161 | 2022-12-30 11:34:52 +0800 | [diff] [blame] | 188 | if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) { |
| 189 | ret = genphy_c45_read_lpa(phydev); |
| 190 | if (ret < 0) |
| 191 | return ret; |
| 192 | |
| 193 | /* Read the link partner's 1G advertisement */ |
| 194 | ret = phy_read(phydev, MII_STAT1000); |
| 195 | if (ret < 0) |
| 196 | return ret; |
| 197 | mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret); |
| 198 | } else if (phydev->autoneg == AUTONEG_DISABLE) { |
| 199 | linkmode_zero(phydev->lp_advertising); |
developer | 284cd6e | 2022-12-15 22:19:39 +0800 | [diff] [blame] | 200 | } |
| 201 | |
developer | e7f6161 | 2022-12-30 11:34:52 +0800 | [diff] [blame] | 202 | ret = phy_read(phydev, PHY_AUX_CTRL_STATUS); |
| 203 | if (ret < 0) |
| 204 | return ret; |
| 205 | |
developer | e7f6161 | 2022-12-30 11:34:52 +0800 | [diff] [blame] | 206 | switch (FIELD_GET(PHY_AUX_SPEED_MASK, ret)) { |
| 207 | case PHY_AUX_SPD_10: |
developer | 284cd6e | 2022-12-15 22:19:39 +0800 | [diff] [blame] | 208 | phydev->speed = SPEED_10; |
developer | e7f6161 | 2022-12-30 11:34:52 +0800 | [diff] [blame] | 209 | break; |
| 210 | case PHY_AUX_SPD_100: |
| 211 | phydev->speed = SPEED_100; |
| 212 | break; |
| 213 | case PHY_AUX_SPD_1000: |
| 214 | phydev->speed = SPEED_1000; |
| 215 | break; |
| 216 | case PHY_AUX_SPD_2500: |
| 217 | phydev->speed = SPEED_2500; |
developer | e7f6161 | 2022-12-30 11:34:52 +0800 | [diff] [blame] | 218 | break; |
developer | 284cd6e | 2022-12-15 22:19:39 +0800 | [diff] [blame] | 219 | } |
| 220 | |
developer | 5c0c062 | 2023-04-12 11:51:08 +0800 | [diff] [blame] | 221 | ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LINK_STATUS_MISC); |
| 222 | if (ret < 0) |
| 223 | return ret; |
| 224 | phydev->duplex = (ret & MTK_PHY_FDX_ENABLE) ? DUPLEX_FULL : DUPLEX_HALF; |
developer | d596967 | 2023-06-07 10:35:00 +0800 | [diff] [blame] | 225 | /* FIXME: The current firmware always enables rate adaptation mode. */ |
| 226 | phydev->rate_matching = RATE_MATCH_PAUSE; |
developer | 5c0c062 | 2023-04-12 11:51:08 +0800 | [diff] [blame] | 227 | |
developer | e7f6161 | 2022-12-30 11:34:52 +0800 | [diff] [blame] | 228 | return 0; |
developer | 284cd6e | 2022-12-15 22:19:39 +0800 | [diff] [blame] | 229 | } |
| 230 | |
developer | d596967 | 2023-06-07 10:35:00 +0800 | [diff] [blame] | 231 | static int mt798x_2p5ge_phy_get_rate_matching(struct phy_device *phydev, |
| 232 | phy_interface_t iface) |
| 233 | { |
| 234 | if (iface == PHY_INTERFACE_MODE_XGMII) |
| 235 | return RATE_MATCH_PAUSE; |
| 236 | return RATE_MATCH_NONE; |
| 237 | } |
| 238 | |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 239 | static struct phy_driver mtk_gephy_driver[] = { |
| 240 | { |
| 241 | PHY_ID_MATCH_EXACT(0x00339c11), |
| 242 | .name = "MediaTek MT798x 2.5GbE PHY", |
| 243 | .config_init = mt798x_2p5ge_phy_config_init, |
developer | 1302b25 | 2022-12-30 19:04:55 +0800 | [diff] [blame] | 244 | .config_aneg = mt798x_2p5ge_phy_config_aneg, |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 245 | .get_features = mt798x_2p5ge_phy_get_features, |
developer | 284cd6e | 2022-12-15 22:19:39 +0800 | [diff] [blame] | 246 | .read_status = mt798x_2p5ge_phy_read_status, |
developer | d596967 | 2023-06-07 10:35:00 +0800 | [diff] [blame] | 247 | .get_rate_matching = mt798x_2p5ge_phy_get_rate_matching, |
developer | 2cdaeb1 | 2022-10-04 20:25:05 +0800 | [diff] [blame] | 248 | //.config_intr = genphy_no_config_intr, |
| 249 | //.handle_interrupt = genphy_no_ack_interrupt, |
| 250 | //.suspend = genphy_suspend, |
| 251 | //.resume = genphy_resume, |
| 252 | }, |
| 253 | }; |
| 254 | |
| 255 | module_phy_driver(mtk_gephy_driver); |
| 256 | |
| 257 | static struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = { |
| 258 | { PHY_ID_MATCH_VENDOR(0x00339c00) }, |
| 259 | { } |
| 260 | }; |
| 261 | |
| 262 | MODULE_DESCRIPTION("MediaTek 2.5Gb Ethernet PHY driver"); |
| 263 | MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>"); |
| 264 | MODULE_LICENSE("GPL"); |
| 265 | |
| 266 | MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl); |