blob: 96778a50d1f855715ac98c5b9d46cc5060ab73cd [file] [log] [blame]
developerfd40db22021-04-29 10:08:25 +08001/dts-v1/;
developer565bacb2021-09-28 21:26:32 +08002#include "mt7986a.dtsi"
3#include "mt7986a-pinctrl.dtsi"
4#include "mt7986-spim-nor-partition.dtsi"
developerfd40db22021-04-29 10:08:25 +08005/ {
6 model = "MediaTek MT7986a RFB";
developer3395eb42021-06-15 16:01:34 +08007 compatible = "mediatek,mt7986a-nor-rfb";
developer565bacb2021-09-28 21:26:32 +08008 chosen {
9 bootargs = "console=ttyS0,115200n1 loglevel=8 \
10 earlycon=uart8250,mmio32,0x11002000";
11 };
12
13 memory {
14 reg = <0 0x40000000 0 0x10000000>;
15 };
16
developerbe797a32021-12-16 16:56:09 +080017 sound_wm8960 {
18 compatible = "mediatek,mt79xx-wm8960-machine";
developer565bacb2021-09-28 21:26:32 +080019 mediatek,platform = <&afe>;
20 audio-routing = "Headphone", "HP_L",
21 "Headphone", "HP_R",
22 "LINPUT1", "AMIC",
23 "RINPUT1", "AMIC";
24 mediatek,audio-codec = <&wm8960>;
25 status = "okay";
26 };
developerbe797a32021-12-16 16:56:09 +080027
28 sound_si3218x {
29 compatible = "mediatek,mt79xx-si3218x-machine";
30 mediatek,platform = <&afe>;
31 mediatek,ext-codec = <&proslic_spi>;
32 status = "okay";
33 };
developerfd40db22021-04-29 10:08:25 +080034};
developer298705c2021-06-05 18:48:19 +080035
developer209e52d2022-06-30 11:32:57 +080036&fan {
37 pwms = <&pwm 1 50000 0>;
38 status = "disabled";
39};
40
developer565bacb2021-09-28 21:26:32 +080041&pwm {
42 pinctrl-names = "default";
43 pinctrl-0 = <&pwm0_pin &pwm1_pin_g1>;
developer298705c2021-06-05 18:48:19 +080044 status = "okay";
developer565bacb2021-09-28 21:26:32 +080045};
developer5b91be72021-09-27 14:03:07 +080046
developer565bacb2021-09-28 21:26:32 +080047&uart0 {
48 status = "okay";
49};
50
51&uart1 {
52 pinctrl-names = "default";
53 pinctrl-0 = <&uart1_pins>;
54 status = "okay";
55};
56
57&uart2 {
58 pinctrl-names = "default";
59 pinctrl-0 = <&uart2_pins>;
60 status = "okay";
61};
62
63&i2c0 {
64 pinctrl-names = "default";
65 pinctrl-0 = <&i2c_pins>;
66 status = "okay";
67
68 wm8960: wm8960@1a {
69 compatible = "wlf,wm8960";
70 reg = <0x1a>;
71 };
72};
73
74&auxadc {
75 status = "okay";
76};
77
78&watchdog {
79 status = "okay";
80};
81
82&eth {
83 status = "okay";
84
85 gmac0: mac@0 {
86 compatible = "mediatek,eth-mac";
87 reg = <0>;
88 phy-mode = "2500base-x";
89
90 fixed-link {
91 speed = <2500>;
92 full-duplex;
93 pause;
94 };
95 };
96
97 gmac1: mac@1 {
98 compatible = "mediatek,eth-mac";
99 reg = <1>;
100 phy-mode = "2500base-x";
101
102 fixed-link {
103 speed = <2500>;
104 full-duplex;
105 pause;
106 };
107 };
108
109 mdio: mdio-bus {
110 #address-cells = <1>;
111 #size-cells = <0>;
112
113 phy5: phy@5 {
114 compatible = "ethernet-phy-id67c9.de0a";
115 reg = <5>;
116 reset-gpios = <&pio 6 1>;
developer8c5a08b2022-05-06 09:10:38 +0800117 reset-assert-us = <600>;
developer565bacb2021-09-28 21:26:32 +0800118 reset-deassert-us = <20000>;
119 phy-mode = "2500base-x";
120 };
121
122 phy6: phy@6 {
123 compatible = "ethernet-phy-id67c9.de0a";
124 reg = <6>;
125 phy-mode = "2500base-x";
126 };
127
128 switch@0 {
129 compatible = "mediatek,mt7531";
130 reg = <31>;
131 reset-gpios = <&pio 5 0>;
132
133 ports {
134 #address-cells = <1>;
135 #size-cells = <0>;
136
137 port@0 {
138 reg = <0>;
139 label = "lan0";
140 };
141
142 port@1 {
143 reg = <1>;
144 label = "lan1";
145 };
146
147 port@2 {
148 reg = <2>;
149 label = "lan2";
150 };
151
152 port@3 {
153 reg = <3>;
154 label = "lan3";
155 };
156
157 port@6 {
158 reg = <6>;
159 label = "cpu";
160 ethernet = <&gmac0>;
161 phy-mode = "2500base-x";
162
163 fixed-link {
164 speed = <2500>;
165 full-duplex;
166 pause;
167 };
168 };
developer5b91be72021-09-27 14:03:07 +0800169 };
170 };
171 };
172};
173
developer565bacb2021-09-28 21:26:32 +0800174&hnat {
175 mtketh-wan = "eth1";
176 mtketh-lan = "lan";
177 mtketh-max-gmac = <2>;
178 status = "okay";
developer5b91be72021-09-27 14:03:07 +0800179};
180
developer565bacb2021-09-28 21:26:32 +0800181&spi0 {
182 pinctrl-names = "default";
183 pinctrl-0 = <&spi_flash_pins>;
184 cs-gpios = <0>, <0>;
185 status = "okay";
186
187 spi_nor@0 {
188 #address-cells = <1>;
189 #size-cells = <1>;
190 compatible = "jedec,spi-nor";
191 reg = <0>;
developerb9b1ffc2021-12-16 14:19:08 +0800192 spi-max-frequency = <52000000>;
developer565bacb2021-09-28 21:26:32 +0800193 spi-tx-buswidth = <4>;
194 spi-rx-buswidth = <4>;
195 };
196};
197
198&spi1 {
199 pinctrl-names = "default";
200 pinctrl-0 = <&spic_pins_g2>;
201 status = "okay";
developerbe797a32021-12-16 16:56:09 +0800202
203 proslic_spi: proslic_spi@0 {
204 compatible = "silabs,proslic_spi";
205 reg = <0>;
206 spi-max-frequency = <10000000>;
207 spi-cpha = <1>;
208 spi-cpol = <1>;
209 channel_count = <1>;
210 debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */
211 reset_gpio = <&pio 7 0>;
212 ig,enable-spi = <1>; /* 1: Enable, 0: Disable */
213 };
developer565bacb2021-09-28 21:26:32 +0800214};
215
216&pcie0 {
217 pinctrl-names = "default";
218 pinctrl-0 = <&pcie0_pins>;
219 status = "okay";
220};
221
222&wbsys {
223 mediatek,mtd-eeprom = <&factory 0x0000>;
224 status = "okay";
225};
226
227&pio {
228 spi_flash_pins: spi-flash-pins-33-to-38 {
229 mux {
230 function = "flash";
231 groups = "spi0", "spi0_wp_hold";
232 };
233 conf-pu {
234 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
235 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800236 bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
developer565bacb2021-09-28 21:26:32 +0800237 };
238 conf-pd {
239 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
240 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800241 bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
developer565bacb2021-09-28 21:26:32 +0800242 };
243 };
developer298705c2021-06-05 18:48:19 +0800244};