blob: e56e5e0f44e653d576dc393722264ef3de17fd05 [file] [log] [blame]
developerfd40db22021-04-29 10:08:25 +08001/dts-v1/;
developer565bacb2021-09-28 21:26:32 +08002#include "mt7986a.dtsi"
3#include "mt7986a-pinctrl.dtsi"
4#include "mt7986-spim-nor-partition.dtsi"
developerfd40db22021-04-29 10:08:25 +08005/ {
6 model = "MediaTek MT7986a RFB";
developer3395eb42021-06-15 16:01:34 +08007 compatible = "mediatek,mt7986a-nor-rfb";
developer565bacb2021-09-28 21:26:32 +08008 chosen {
9 bootargs = "console=ttyS0,115200n1 loglevel=8 \
10 earlycon=uart8250,mmio32,0x11002000";
11 };
12
13 memory {
14 reg = <0 0x40000000 0 0x10000000>;
15 };
16
developerbe797a32021-12-16 16:56:09 +080017 sound_wm8960 {
18 compatible = "mediatek,mt79xx-wm8960-machine";
developer565bacb2021-09-28 21:26:32 +080019 mediatek,platform = <&afe>;
20 audio-routing = "Headphone", "HP_L",
21 "Headphone", "HP_R",
22 "LINPUT1", "AMIC",
23 "RINPUT1", "AMIC";
24 mediatek,audio-codec = <&wm8960>;
25 status = "okay";
26 };
developerbe797a32021-12-16 16:56:09 +080027
28 sound_si3218x {
29 compatible = "mediatek,mt79xx-si3218x-machine";
30 mediatek,platform = <&afe>;
31 mediatek,ext-codec = <&proslic_spi>;
32 status = "okay";
33 };
developerfd40db22021-04-29 10:08:25 +080034};
developer298705c2021-06-05 18:48:19 +080035
developer565bacb2021-09-28 21:26:32 +080036&pwm {
37 pinctrl-names = "default";
38 pinctrl-0 = <&pwm0_pin &pwm1_pin_g1>;
developer298705c2021-06-05 18:48:19 +080039 status = "okay";
developer565bacb2021-09-28 21:26:32 +080040};
developer5b91be72021-09-27 14:03:07 +080041
developer565bacb2021-09-28 21:26:32 +080042&uart0 {
43 status = "okay";
44};
45
46&uart1 {
47 pinctrl-names = "default";
48 pinctrl-0 = <&uart1_pins>;
49 status = "okay";
50};
51
52&uart2 {
53 pinctrl-names = "default";
54 pinctrl-0 = <&uart2_pins>;
55 status = "okay";
56};
57
58&i2c0 {
59 pinctrl-names = "default";
60 pinctrl-0 = <&i2c_pins>;
61 status = "okay";
62
63 wm8960: wm8960@1a {
64 compatible = "wlf,wm8960";
65 reg = <0x1a>;
66 };
67};
68
69&auxadc {
70 status = "okay";
71};
72
73&watchdog {
74 status = "okay";
75};
76
77&eth {
78 status = "okay";
79
80 gmac0: mac@0 {
81 compatible = "mediatek,eth-mac";
82 reg = <0>;
83 phy-mode = "2500base-x";
84
85 fixed-link {
86 speed = <2500>;
87 full-duplex;
88 pause;
89 };
90 };
91
92 gmac1: mac@1 {
93 compatible = "mediatek,eth-mac";
94 reg = <1>;
95 phy-mode = "2500base-x";
96
97 fixed-link {
98 speed = <2500>;
99 full-duplex;
100 pause;
101 };
102 };
103
104 mdio: mdio-bus {
105 #address-cells = <1>;
106 #size-cells = <0>;
107
108 phy5: phy@5 {
109 compatible = "ethernet-phy-id67c9.de0a";
110 reg = <5>;
111 reset-gpios = <&pio 6 1>;
developer8c5a08b2022-05-06 09:10:38 +0800112 reset-assert-us = <600>;
developer565bacb2021-09-28 21:26:32 +0800113 reset-deassert-us = <20000>;
114 phy-mode = "2500base-x";
115 };
116
117 phy6: phy@6 {
118 compatible = "ethernet-phy-id67c9.de0a";
119 reg = <6>;
120 phy-mode = "2500base-x";
121 };
122
123 switch@0 {
124 compatible = "mediatek,mt7531";
125 reg = <31>;
126 reset-gpios = <&pio 5 0>;
127
128 ports {
129 #address-cells = <1>;
130 #size-cells = <0>;
131
132 port@0 {
133 reg = <0>;
134 label = "lan0";
135 };
136
137 port@1 {
138 reg = <1>;
139 label = "lan1";
140 };
141
142 port@2 {
143 reg = <2>;
144 label = "lan2";
145 };
146
147 port@3 {
148 reg = <3>;
149 label = "lan3";
150 };
151
152 port@6 {
153 reg = <6>;
154 label = "cpu";
155 ethernet = <&gmac0>;
156 phy-mode = "2500base-x";
157
158 fixed-link {
159 speed = <2500>;
160 full-duplex;
161 pause;
162 };
163 };
developer5b91be72021-09-27 14:03:07 +0800164 };
165 };
166 };
167};
168
developer565bacb2021-09-28 21:26:32 +0800169&hnat {
170 mtketh-wan = "eth1";
171 mtketh-lan = "lan";
172 mtketh-max-gmac = <2>;
173 status = "okay";
developer5b91be72021-09-27 14:03:07 +0800174};
175
developer565bacb2021-09-28 21:26:32 +0800176&spi0 {
177 pinctrl-names = "default";
178 pinctrl-0 = <&spi_flash_pins>;
179 cs-gpios = <0>, <0>;
180 status = "okay";
181
182 spi_nor@0 {
183 #address-cells = <1>;
184 #size-cells = <1>;
185 compatible = "jedec,spi-nor";
186 reg = <0>;
developerb9b1ffc2021-12-16 14:19:08 +0800187 spi-max-frequency = <52000000>;
developer565bacb2021-09-28 21:26:32 +0800188 spi-tx-buswidth = <4>;
189 spi-rx-buswidth = <4>;
190 };
191};
192
193&spi1 {
194 pinctrl-names = "default";
195 pinctrl-0 = <&spic_pins_g2>;
196 status = "okay";
developerbe797a32021-12-16 16:56:09 +0800197
198 proslic_spi: proslic_spi@0 {
199 compatible = "silabs,proslic_spi";
200 reg = <0>;
201 spi-max-frequency = <10000000>;
202 spi-cpha = <1>;
203 spi-cpol = <1>;
204 channel_count = <1>;
205 debug_level = <4>; /* 1 = TRC, 2 = DBG, 4 = ERR */
206 reset_gpio = <&pio 7 0>;
207 ig,enable-spi = <1>; /* 1: Enable, 0: Disable */
208 };
developer565bacb2021-09-28 21:26:32 +0800209};
210
211&pcie0 {
212 pinctrl-names = "default";
213 pinctrl-0 = <&pcie0_pins>;
214 status = "okay";
215};
216
217&wbsys {
218 mediatek,mtd-eeprom = <&factory 0x0000>;
219 status = "okay";
220};
221
222&pio {
223 spi_flash_pins: spi-flash-pins-33-to-38 {
224 mux {
225 function = "flash";
226 groups = "spi0", "spi0_wp_hold";
227 };
228 conf-pu {
229 pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
230 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800231 bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
developer565bacb2021-09-28 21:26:32 +0800232 };
233 conf-pd {
234 pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
235 drive-strength = <MTK_DRIVE_8mA>;
developerb5a819c2022-05-16 19:16:07 +0800236 bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
developer565bacb2021-09-28 21:26:32 +0800237 };
238 };
developer298705c2021-06-05 18:48:19 +0800239};