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developer20747c12022-09-16 14:09:40 +08001From 781871b4690c21e24ba3a86b488efb46aaa402c5 Mon Sep 17 00:00:00 2001
developere2cc0fa2022-03-29 17:31:03 +08002From: MeiChia Chiu <meichia.chiu@mediatek.com>
developerf64861f2022-06-22 11:44:53 +08003Date: Wed, 22 Jun 2022 10:45:53 +0800
developer5ce5ea42022-08-31 14:12:29 +08004Subject: [PATCH 1004/1009] mt76: mt7915: add support for muru_onoff via
developerbd398d52022-06-06 20:53:24 +08005 debugfs
developere2cc0fa2022-03-29 17:31:03 +08006
7---
developer5ce5ea42022-08-31 14:12:29 +08008 mt7915/init.c | 1 +
9 mt7915/mcu.c | 9 +++++++--
10 mt7915/mcu.h | 6 ++++++
11 mt7915/mtk_debugfs.c | 33 +++++++++++++++++++++++++++++++++
developer4721e252022-06-21 16:41:28 +080012 4 files changed, 47 insertions(+), 2 deletions(-)
developere2cc0fa2022-03-29 17:31:03 +080013
14diff --git a/mt7915/init.c b/mt7915/init.c
developer20747c12022-09-16 14:09:40 +080015index 6efa28fe..37b7b54a 100644
developere2cc0fa2022-03-29 17:31:03 +080016--- a/mt7915/init.c
17+++ b/mt7915/init.c
developer5ce5ea42022-08-31 14:12:29 +080018@@ -582,6 +582,7 @@ static void mt7915_init_work(struct work_struct *work)
developere2cc0fa2022-03-29 17:31:03 +080019 mt7915_init_txpower(dev, &dev->mphy.sband_5g.sband);
20 mt7915_init_txpower(dev, &dev->mphy.sband_6g.sband);
21 mt7915_txbf_init(dev);
22+ dev->dbg.muru_onoff = OFDMA_DL | MUMIMO_UL | MUMIMO_DL;
23 }
24
25 void mt7915_wfsys_reset(struct mt7915_dev *dev)
26diff --git a/mt7915/mcu.c b/mt7915/mcu.c
developer20747c12022-09-16 14:09:40 +080027index 48e9e5ec..ed789707 100644
developere2cc0fa2022-03-29 17:31:03 +080028--- a/mt7915/mcu.c
29+++ b/mt7915/mcu.c
developerf64861f2022-06-22 11:44:53 +080030@@ -856,13 +856,18 @@ mt7915_mcu_sta_muru_tlv(struct mt7915_dev *dev, struct sk_buff *skb,
developere2cc0fa2022-03-29 17:31:03 +080031
32 muru = (struct sta_rec_muru *)tlv;
33
34- muru->cfg.mimo_dl_en = mvif->cap.he_mu_ebfer ||
35+ muru->cfg.mimo_dl_en = (mvif->cap.he_mu_ebfer ||
36 mvif->cap.vht_mu_ebfer ||
37- mvif->cap.vht_mu_ebfee;
developere2cc0fa2022-03-29 17:31:03 +080038+ mvif->cap.vht_mu_ebfee) &&
developer4721e252022-06-21 16:41:28 +080039+ !!(dev->dbg.muru_onoff & MUMIMO_DL);
developerf64861f2022-06-22 11:44:53 +080040 if (!is_mt7915(&dev->mt76))
41 muru->cfg.mimo_ul_en = true;
42 muru->cfg.ofdma_dl_en = true;
43
developere2cc0fa2022-03-29 17:31:03 +080044+ muru->cfg.mimo_ul_en = !!(dev->dbg.muru_onoff & MUMIMO_UL);
45+ muru->cfg.ofdma_dl_en = !!(dev->dbg.muru_onoff & OFDMA_DL);
46+ muru->cfg.ofdma_ul_en = !!(dev->dbg.muru_onoff & OFDMA_UL);
developerf64861f2022-06-22 11:44:53 +080047+
developere2cc0fa2022-03-29 17:31:03 +080048 if (sta->vht_cap.vht_supported)
49 muru->mimo_dl.vht_mu_bfee =
developerf64861f2022-06-22 11:44:53 +080050 !!(sta->vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE);
developere2cc0fa2022-03-29 17:31:03 +080051diff --git a/mt7915/mcu.h b/mt7915/mcu.h
developer20747c12022-09-16 14:09:40 +080052index a27129c2..d3cc8283 100644
developere2cc0fa2022-03-29 17:31:03 +080053--- a/mt7915/mcu.h
54+++ b/mt7915/mcu.h
developerd59e4772022-07-14 13:48:49 +080055@@ -556,4 +556,10 @@ struct csi_data {
developere2cc0fa2022-03-29 17:31:03 +080056 };
57 #endif
58
59+/* MURU */
developer4721e252022-06-21 16:41:28 +080060+#define OFDMA_DL BIT(0)
61+#define OFDMA_UL BIT(1)
62+#define MUMIMO_DL BIT(2)
63+#define MUMIMO_UL BIT(3)
developere2cc0fa2022-03-29 17:31:03 +080064+
65 #endif
developere2cc0fa2022-03-29 17:31:03 +080066diff --git a/mt7915/mtk_debugfs.c b/mt7915/mtk_debugfs.c
developer20747c12022-09-16 14:09:40 +080067index f18c8b6c..e239df95 100644
developere2cc0fa2022-03-29 17:31:03 +080068--- a/mt7915/mtk_debugfs.c
69+++ b/mt7915/mtk_debugfs.c
developer68e1eb22022-05-09 17:02:12 +080070@@ -2480,6 +2480,38 @@ static int mt7915_token_txd_read(struct seq_file *s, void *data)
developere2cc0fa2022-03-29 17:31:03 +080071 return 0;
72 }
73
74+static int mt7915_muru_onoff_get(void *data, u64 *val)
75+{
developer4721e252022-06-21 16:41:28 +080076+ struct mt7915_dev *dev = data;
developere2cc0fa2022-03-29 17:31:03 +080077+
developer4721e252022-06-21 16:41:28 +080078+ *val = dev->dbg.muru_onoff;
developere2cc0fa2022-03-29 17:31:03 +080079+
developer4721e252022-06-21 16:41:28 +080080+ printk("mumimo ul:%d, mumimo dl:%d, ofdma ul:%d, ofdma dl:%d\n",
81+ !!(dev->dbg.muru_onoff & MUMIMO_UL),
82+ !!(dev->dbg.muru_onoff & MUMIMO_DL),
83+ !!(dev->dbg.muru_onoff & OFDMA_UL),
84+ !!(dev->dbg.muru_onoff & OFDMA_DL));
developere2cc0fa2022-03-29 17:31:03 +080085+
developer4721e252022-06-21 16:41:28 +080086+ return 0;
developere2cc0fa2022-03-29 17:31:03 +080087+}
88+
89+static int mt7915_muru_onoff_set(void *data, u64 val)
90+{
developer4721e252022-06-21 16:41:28 +080091+ struct mt7915_dev *dev = data;
developere2cc0fa2022-03-29 17:31:03 +080092+
developer4721e252022-06-21 16:41:28 +080093+ if (val > 15) {
94+ printk("Wrong value! The value is between 0 ~ 15.\n");
95+ goto exit;
96+ }
developere2cc0fa2022-03-29 17:31:03 +080097+
developer4721e252022-06-21 16:41:28 +080098+ dev->dbg.muru_onoff = val;
developere2cc0fa2022-03-29 17:31:03 +080099+exit:
developer4721e252022-06-21 16:41:28 +0800100+ return 0;
developere2cc0fa2022-03-29 17:31:03 +0800101+}
102+
103+DEFINE_DEBUGFS_ATTRIBUTE(fops_muru_onoff, mt7915_muru_onoff_get,
developer4721e252022-06-21 16:41:28 +0800104+ mt7915_muru_onoff_set, "%llx\n");
developere2cc0fa2022-03-29 17:31:03 +0800105+
106 static int mt7915_amsduinfo_read(struct seq_file *s, void *data)
107 {
108 struct mt7915_dev *dev = dev_get_drvdata(s->private);
developer68e1eb22022-05-09 17:02:12 +0800109@@ -2857,6 +2889,7 @@ int mt7915_mtk_init_debugfs(struct mt7915_phy *phy, struct dentry *dir)
developere2cc0fa2022-03-29 17:31:03 +0800110
111 mt7915_mcu_fw_log_2_host(dev, MCU_FW_LOG_WM, 0);
112
113+ debugfs_create_file("muru_onoff", 0600, dir, dev, &fops_muru_onoff);
114 debugfs_create_file("fw_debug_module", 0600, dir, dev,
115 &fops_fw_debug_module);
116 debugfs_create_file("fw_debug_level", 0600, dir, dev,
117--
developer20747c12022-09-16 14:09:40 +08001182.25.1
developere2cc0fa2022-03-29 17:31:03 +0800119