developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020 MediaTek Inc. |
| 3 | * Author: Sam.Shih <sam.shih@mediatek.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
| 15 | #include <dt-bindings/interrupt-controller/irq.h> |
| 16 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 17 | #include <dt-bindings/phy/phy.h> |
| 18 | #include <dt-bindings/reset/ti-syscon.h> |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 19 | #include <dt-bindings/clock/mt7986-clk.h> |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 20 | #include <dt-bindings/thermal/thermal.h> |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 21 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 22 | / { |
| 23 | compatible = "mediatek,mt7986a-rfb"; |
| 24 | interrupt-parent = <&gic>; |
| 25 | #address-cells = <2>; |
| 26 | #size-cells = <2>; |
| 27 | cpus { |
| 28 | #address-cells = <1>; |
| 29 | #size-cells = <0>; |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 30 | cpu0: cpu@0 { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 31 | device_type = "cpu"; |
| 32 | compatible = "arm,cortex-a53"; |
| 33 | enable-method = "psci"; |
| 34 | reg = <0x0>; |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 35 | #cooling-cells = <2>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 36 | }; |
| 37 | |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 38 | cpu1: cpu@1 { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 39 | device_type = "cpu"; |
| 40 | compatible = "arm,cortex-a53"; |
| 41 | enable-method = "psci"; |
| 42 | reg = <0x1>; |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 43 | #cooling-cells = <2>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 44 | }; |
| 45 | |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 46 | cpu2: cpu@2 { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 47 | device_type = "cpu"; |
| 48 | compatible = "arm,cortex-a53"; |
| 49 | enable-method = "psci"; |
| 50 | reg = <0x2>; |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 51 | #cooling-cells = <2>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 52 | }; |
| 53 | |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 54 | cpu3: cpu@3 { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 55 | device_type = "cpu"; |
| 56 | enable-method = "psci"; |
| 57 | compatible = "arm,cortex-a53"; |
| 58 | reg = <0x3>; |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 59 | #cooling-cells = <2>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 60 | }; |
| 61 | }; |
| 62 | |
| 63 | wed: wed@15010000 { |
| 64 | compatible = "mediatek,wed"; |
| 65 | wed_num = <2>; |
| 66 | /* add this property for wed get the pci slot number. */ |
| 67 | pci_slot_map = <0>, <1>; |
| 68 | reg = <0 0x15010000 0 0x1000>, |
| 69 | <0 0x15011000 0 0x1000>; |
| 70 | interrupt-parent = <&gic>; |
| 71 | interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, |
| 72 | <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| 73 | }; |
| 74 | |
| 75 | wed2: wed2@15011000 { |
| 76 | compatible = "mediatek,wed2"; |
| 77 | wed_num = <2>; |
| 78 | reg = <0 0x15010000 0 0x1000>, |
| 79 | <0 0x15011000 0 0x1000>; |
| 80 | interrupt-parent = <&gic>; |
| 81 | interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, |
| 82 | <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| 83 | }; |
| 84 | |
| 85 | wdma: wdma@15104800 { |
| 86 | compatible = "mediatek,wed-wdma"; |
| 87 | reg = <0 0x15104800 0 0x400>, |
| 88 | <0 0x15104c00 0 0x400>; |
| 89 | }; |
| 90 | |
| 91 | ap2woccif: ap2woccif@151A5000 { |
| 92 | compatible = "mediatek,ap2woccif"; |
| 93 | reg = <0 0x151A5000 0 0x1000>, |
| 94 | <0 0x151AD000 0 0x1000>; |
| 95 | interrupt-parent = <&gic>; |
| 96 | interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, |
| 97 | <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; |
| 98 | }; |
| 99 | |
| 100 | wocpu0_ilm: wocpu0_ilm@151E0000 { |
| 101 | compatible = "mediatek,wocpu0_ilm"; |
| 102 | reg = <0 0x151E0000 0 0x8000>; |
| 103 | }; |
| 104 | |
| 105 | wocpu1_ilm: wocpu1_ilm@151F0000 { |
| 106 | compatible = "mediatek,wocpu1_ilm"; |
| 107 | reg = <0 0x151F0000 0 0x8000>; |
| 108 | }; |
| 109 | |
| 110 | wocpu_dlm: wocpu_dlm@151E8000 { |
| 111 | compatible = "mediatek,wocpu_dlm"; |
| 112 | reg = <0 0x151E8000 0 0x2000>, |
| 113 | <0 0x151F8000 0 0x2000>; |
| 114 | |
| 115 | resets = <ðsysrst 0>; |
| 116 | reset-names = "wocpu_rst"; |
| 117 | }; |
| 118 | |
| 119 | cpu_boot: wocpu_boot@15194000 { |
| 120 | compatible = "mediatek,wocpu_boot"; |
| 121 | reg = <0 0x15194000 0 0x1000>; |
| 122 | }; |
| 123 | |
| 124 | reserved-memory { |
| 125 | #address-cells = <2>; |
| 126 | #size-cells = <2>; |
| 127 | ranges; |
| 128 | |
| 129 | /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ |
| 130 | secmon_reserved: secmon@43000000 { |
| 131 | reg = <0 0x43000000 0 0x30000>; |
| 132 | no-map; |
| 133 | }; |
| 134 | |
| 135 | wmcpu_emi: wmcpu-reserved@4FC00000 { |
| 136 | compatible = "mediatek,wmcpu-reserved"; |
| 137 | no-map; |
| 138 | reg = <0 0x4FC00000 0 0x00100000>; |
| 139 | }; |
| 140 | |
| 141 | wocpu0_emi: wocpu0_emi@4FD00000 { |
| 142 | compatible = "mediatek,wocpu0_emi"; |
| 143 | no-map; |
| 144 | reg = <0 0x4FD00000 0 0x40000>; |
| 145 | shared = <0>; |
| 146 | }; |
| 147 | |
| 148 | wocpu1_emi: wocpu1_emi@4FD80000 { |
| 149 | compatible = "mediatek,wocpu1_emi"; |
| 150 | no-map; |
| 151 | reg = <0 0x4FD40000 0 0x40000>; |
| 152 | shared = <0>; |
| 153 | }; |
| 154 | |
| 155 | wocpu_data: wocpu_data@4FE00000 { |
| 156 | compatible = "mediatek,wocpu_data"; |
| 157 | no-map; |
| 158 | reg = <0 0x4FD80000 0 0x200000>; |
| 159 | shared = <1>; |
| 160 | }; |
| 161 | }; |
| 162 | |
| 163 | psci { |
| 164 | compatible = "arm,psci-0.2"; |
| 165 | method = "smc"; |
| 166 | }; |
| 167 | |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 168 | clk40m: oscillator@0 { |
| 169 | compatible = "fixed-clock"; |
| 170 | #clock-cells = <0>; |
| 171 | clock-frequency = <40000000>; |
| 172 | clock-output-names = "clkxtal"; |
| 173 | }; |
| 174 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 175 | system_clk: dummy_system_clk { |
| 176 | compatible = "fixed-clock"; |
| 177 | clock-frequency = <40000000>; |
| 178 | #clock-cells = <0>; |
| 179 | }; |
| 180 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 181 | timer { |
| 182 | compatible = "arm,armv8-timer"; |
| 183 | interrupt-parent = <&gic>; |
developer | f39022a | 2021-05-06 13:31:52 +0800 | [diff] [blame] | 184 | clock-frequency = <13000000>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 185 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| 186 | <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| 187 | <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| 188 | <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 189 | }; |
| 190 | |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 191 | infracfg_ao: infracfg_ao@10001000 { |
| 192 | compatible = "mediatek,mt7986-infracfg_ao", "syscon"; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 193 | reg = <0 0x10001000 0 0x68>; |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 194 | #clock-cells = <1>; |
| 195 | }; |
| 196 | |
| 197 | infracfg: infracfg@10001040 { |
| 198 | compatible = "mediatek,mt7986-infracfg", "syscon"; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 199 | reg = <0 0x1000106c 0 0x1000>; |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 200 | #clock-cells = <1>; |
| 201 | }; |
| 202 | |
| 203 | topckgen: topckgen@1001B000 { |
| 204 | compatible = "mediatek,mt7986-topckgen", "syscon"; |
| 205 | reg = <0 0x1001B000 0 0x1000>; |
| 206 | #clock-cells = <1>; |
| 207 | }; |
| 208 | |
| 209 | apmixedsys: apmixedsys@1001E000 { |
| 210 | compatible = "mediatek,mt7986-apmixedsys", "syscon"; |
| 211 | reg = <0 0x1001E000 0 0x1000>; |
| 212 | #clock-cells = <1>; |
| 213 | }; |
| 214 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 215 | watchdog: watchdog@1001c000 { |
| 216 | compatible = "mediatek,mt7622-wdt", |
| 217 | "mediatek,mt6589-wdt"; |
| 218 | reg = <0 0x1001c000 0 0x1000>; |
| 219 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
| 220 | #reset-cells = <1>; |
| 221 | }; |
| 222 | |
| 223 | gic: interrupt-controller@c000000 { |
| 224 | compatible = "arm,gic-v3"; |
| 225 | #interrupt-cells = <3>; |
| 226 | interrupt-parent = <&gic>; |
| 227 | interrupt-controller; |
| 228 | reg = <0 0x0c000000 0 0x40000>, /* GICD */ |
| 229 | <0 0x0c080000 0 0x200000>; /* GICR */ |
| 230 | |
| 231 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| 232 | }; |
| 233 | |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 234 | pwm: pwm@10048000 { |
| 235 | compatible = "mediatek,mt7986-pwm"; |
| 236 | reg = <0 0x10048000 0 0x1000>; |
| 237 | #clock-cells = <1>; |
| 238 | #pwm-cells = <2>; |
| 239 | interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; |
| 240 | clocks = <&infracfg CK_INFRA_PWM>, |
| 241 | <&infracfg_ao CK_INFRA_PWM_BSEL>, |
| 242 | <&infracfg_ao CK_INFRA_PWM1_CK>, |
| 243 | <&infracfg_ao CK_INFRA_PWM2_CK>; |
| 244 | assigned-clocks = <&topckgen CK_TOP_PWM_SEL>, |
| 245 | <&infracfg_ao CK_INFRA_PWM_BSEL>, |
| 246 | <&infracfg_ao CK_INFRA_PWM1_SEL>, |
| 247 | <&infracfg_ao CK_INFRA_PWM2_SEL>; |
| 248 | assigned-clock-parents = <&topckgen CK_TOP_CB_M_D4>, |
| 249 | <&infracfg CK_INFRA_PWM>, |
| 250 | <&infracfg CK_INFRA_PWM>, |
| 251 | <&infracfg CK_INFRA_PWM>; |
| 252 | clock-names = "top", "main", "pwm1", "pwm2"; |
| 253 | status = "disabled"; |
| 254 | }; |
| 255 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 256 | uart0: serial@11002000 { |
| 257 | compatible = "mediatek,mt7986-uart", |
| 258 | "mediatek,mt6577-uart"; |
| 259 | reg = <0 0x11002000 0 0x400>; |
| 260 | interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 261 | clocks = <&infracfg_ao CK_INFRA_UART0_CK>; |
| 262 | assigned-clocks = <&topckgen CK_TOP_UART_SEL>, |
| 263 | <&infracfg_ao CK_INFRA_UART0_SEL>; |
| 264 | assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, |
| 265 | <&infracfg CK_INFRA_UART>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 266 | status = "disabled"; |
| 267 | }; |
| 268 | |
| 269 | uart1: serial@11003000 { |
| 270 | compatible = "mediatek,mt7986-uart", |
| 271 | "mediatek,mt6577-uart"; |
| 272 | reg = <0 0x11003000 0 0x400>; |
| 273 | interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 274 | clocks = <&infracfg_ao CK_INFRA_UART1_CK>; |
| 275 | assigned-clocks = <&infracfg_ao CK_INFRA_UART1_SEL>; |
| 276 | assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 277 | status = "disabled"; |
| 278 | }; |
| 279 | |
| 280 | uart2: serial@11004000 { |
| 281 | compatible = "mediatek,mt7986-uart", |
| 282 | "mediatek,mt6577-uart"; |
| 283 | reg = <0 0x11004000 0 0x400>; |
| 284 | interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 285 | clocks = <&infracfg_ao CK_INFRA_UART2_CK>; |
| 286 | assigned-clocks = <&infracfg_ao CK_INFRA_UART2_SEL>; |
| 287 | assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 288 | status = "disabled"; |
| 289 | }; |
| 290 | |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 291 | i2c0: i2c@11008000 { |
| 292 | compatible = "mediatek,mt7986-i2c"; |
| 293 | reg = <0 0x11008000 0 0x90>, |
| 294 | <0 0x10217080 0 0x80>; |
| 295 | interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; |
| 296 | clock-div = <16>; |
| 297 | clocks = <&infracfg_ao CK_INFRA_I2CO_CK>, |
| 298 | <&infracfg_ao CK_INFRA_AP_DMA_CK>; |
| 299 | clock-names = "main", "dma"; |
| 300 | #address-cells = <1>; |
| 301 | #size-cells = <0>; |
| 302 | status = "disabled"; |
| 303 | }; |
| 304 | |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 305 | thermal-zones { |
| 306 | cpu_thermal: cpu-thermal { |
| 307 | polling-delay-passive = <1000>; |
| 308 | polling-delay = <1000>; |
| 309 | thermal-sensors = <&thermal 0>; |
| 310 | |
| 311 | trips { |
| 312 | cpu_passive: cpu-passive { |
| 313 | temperature = <47000>; |
| 314 | hysteresis = <2000>; |
| 315 | type = "passive"; |
| 316 | }; |
| 317 | |
| 318 | cpu_active: cpu-active { |
| 319 | temperature = <67000>; |
| 320 | hysteresis = <2000>; |
| 321 | type = "active"; |
| 322 | }; |
| 323 | |
| 324 | cpu_hot: cpu-hot { |
| 325 | temperature = <87000>; |
| 326 | hysteresis = <2000>; |
| 327 | type = "hot"; |
| 328 | }; |
| 329 | |
| 330 | cpu-crit { |
| 331 | temperature = <107000>; |
| 332 | hysteresis = <2000>; |
| 333 | type = "critical"; |
| 334 | }; |
| 335 | }; |
| 336 | |
| 337 | cooling-maps { |
| 338 | map0 { |
| 339 | trip = <&cpu_passive>; |
| 340 | cooling-device = <&cpu0 |
| 341 | THERMAL_NO_LIMIT |
| 342 | THERMAL_NO_LIMIT>, |
| 343 | <&cpu1 |
| 344 | THERMAL_NO_LIMIT |
| 345 | THERMAL_NO_LIMIT>, |
| 346 | <&cpu2 |
| 347 | THERMAL_NO_LIMIT |
| 348 | THERMAL_NO_LIMIT>, |
| 349 | <&cpu3 |
| 350 | THERMAL_NO_LIMIT |
| 351 | THERMAL_NO_LIMIT>; |
| 352 | }; |
| 353 | |
| 354 | map1 { |
| 355 | trip = <&cpu_active>; |
| 356 | cooling-device = <&cpu0 |
| 357 | THERMAL_NO_LIMIT |
| 358 | THERMAL_NO_LIMIT>, |
| 359 | <&cpu1 |
| 360 | THERMAL_NO_LIMIT |
| 361 | THERMAL_NO_LIMIT>, |
| 362 | <&cpu2 |
| 363 | THERMAL_NO_LIMIT |
| 364 | THERMAL_NO_LIMIT>, |
| 365 | <&cpu3 |
| 366 | THERMAL_NO_LIMIT |
| 367 | THERMAL_NO_LIMIT>; |
| 368 | }; |
| 369 | |
| 370 | map2 { |
| 371 | trip = <&cpu_hot>; |
| 372 | cooling-device = <&cpu0 |
| 373 | THERMAL_NO_LIMIT |
| 374 | THERMAL_NO_LIMIT>, |
| 375 | <&cpu1 |
| 376 | THERMAL_NO_LIMIT |
| 377 | THERMAL_NO_LIMIT>, |
| 378 | <&cpu2 |
| 379 | THERMAL_NO_LIMIT |
| 380 | THERMAL_NO_LIMIT>, |
| 381 | <&cpu3 |
| 382 | THERMAL_NO_LIMIT |
| 383 | THERMAL_NO_LIMIT>; |
| 384 | }; |
| 385 | }; |
| 386 | }; |
| 387 | }; |
| 388 | |
| 389 | thermal: thermal@1100c800 { |
| 390 | #thermal-sensor-cells = <1>; |
| 391 | compatible = "mediatek,mt7986-thermal"; |
| 392 | reg = <0 0x1100c800 0 0x1000>; |
| 393 | interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; |
| 394 | clocks = <&infracfg_ao CK_INFRA_THERM_CK>, |
| 395 | <&infracfg_ao CK_INFRA_ADC_26M_CK>; |
| 396 | clock-names = "therm", "auxadc"; |
| 397 | mediatek,auxadc = <&auxadc>; |
| 398 | mediatek,apmixedsys = <&apmixedsys>; |
| 399 | nvmem-cells = <&thermal_calibration>; |
| 400 | nvmem-cell-names = "calibration-data"; |
| 401 | }; |
| 402 | |
developer | e2ed434 | 2021-07-02 16:04:23 +0800 | [diff] [blame] | 403 | pcie0: pcie@11280000 { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 404 | compatible = "mediatek,mt7986-pcie"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 405 | reg = <0 0x11280000 0 0x5000>; |
developer | e2ed434 | 2021-07-02 16:04:23 +0800 | [diff] [blame] | 406 | reg-names = "pcie-mac"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 407 | #address-cells = <3>; |
| 408 | #size-cells = <2>; |
| 409 | interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; |
| 410 | bus-range = <0x00 0xff>; |
| 411 | ranges = <0x82000000 0 0x20000000 |
| 412 | 0x0 0x20000000 0 0x10000000>; |
developer | e2ed434 | 2021-07-02 16:04:23 +0800 | [diff] [blame] | 413 | status = "disabled"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 414 | |
developer | e2ed434 | 2021-07-02 16:04:23 +0800 | [diff] [blame] | 415 | clocks = <&infracfg_ao CK_INFRA_PCIE_SEL>, |
| 416 | <&infracfg_ao CK_INFRA_IPCIE_CK>, |
| 417 | <&infracfg_ao CK_INFRA_IPCIE_PIPE_CK>, |
| 418 | <&infracfg_ao CK_INFRA_IPCIER_CK>, |
| 419 | <&infracfg_ao CK_INFRA_IPCIEB_CK>; |
| 420 | |
| 421 | #interrupt-cells = <1>; |
| 422 | interrupt-map-mask = <0 0 0 7>; |
| 423 | interrupt-map = <0 0 0 1 &pcie_intc0 0>, |
| 424 | <0 0 0 2 &pcie_intc0 1>, |
| 425 | <0 0 0 3 &pcie_intc0 2>, |
| 426 | <0 0 0 4 &pcie_intc0 3>; |
| 427 | pcie_intc0: interrupt-controller { |
| 428 | interrupt-controller; |
| 429 | #address-cells = <0>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 430 | #interrupt-cells = <1>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 431 | }; |
| 432 | }; |
| 433 | |
developer | 3e91642 | 2021-05-27 16:40:29 +0800 | [diff] [blame] | 434 | crypto: crypto@10320000 { |
| 435 | compatible = "inside-secure,safexcel-eip97"; |
| 436 | reg = <0 0x10320000 0 0x40000>; |
| 437 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| 438 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| 439 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| 440 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; |
| 441 | interrupt-names = "ring0", "ring1", "ring2", "ring3"; |
developer | e1993bd | 2021-07-06 13:48:40 +0800 | [diff] [blame] | 442 | clocks = <&infracfg_ao CK_INFRA_EIP97_CK>; |
| 443 | clock-names = "infra_eip97_ck"; |
| 444 | assigned-clocks = <&topckgen CK_TOP_EIP_B_SEL>; |
| 445 | assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_800M>; |
developer | 3e91642 | 2021-05-27 16:40:29 +0800 | [diff] [blame] | 446 | }; |
| 447 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 448 | pio: pinctrl@1001f000 { |
| 449 | compatible = "mediatek,mt7986-pinctrl"; |
| 450 | reg = <0 0x1001f000 0 0x1000>, |
| 451 | <0 0x11c30000 0 0x1000>, |
| 452 | <0 0x11c40000 0 0x1000>, |
| 453 | <0 0x11e20000 0 0x1000>, |
| 454 | <0 0x11e30000 0 0x1000>, |
| 455 | <0 0x11f00000 0 0x1000>, |
| 456 | <0 0x11f10000 0 0x1000>, |
| 457 | <0 0x1000b000 0 0x1000>; |
| 458 | reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rb_base", |
| 459 | "iocfg_lt_base", "iocfg_lb_base", "iocfg_tr_base", |
| 460 | "iocfg_tl_base", "eint"; |
| 461 | gpio-controller; |
| 462 | #gpio-cells = <2>; |
| 463 | gpio-ranges = <&pio 0 0 100>; |
| 464 | interrupt-controller; |
developer | a7f8fa4 | 2021-06-07 16:46:34 +0800 | [diff] [blame] | 465 | interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 466 | interrupt-parent = <&gic>; |
| 467 | #interrupt-cells = <2>; |
| 468 | }; |
| 469 | |
| 470 | ethsys: syscon@15000000 { |
| 471 | #address-cells = <1>; |
| 472 | #size-cells = <1>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 473 | compatible = "mediatek,mt7986-ethsys_ck", |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 474 | "syscon"; |
| 475 | reg = <0 0x15000000 0 0x1000>; |
| 476 | #clock-cells = <1>; |
| 477 | #reset-cells = <1>; |
| 478 | |
| 479 | ethsysrst: reset-controller { |
| 480 | compatible = "ti,syscon-reset"; |
| 481 | #reset-cells = <1>; |
| 482 | ti,reset-bits = <0x34 4 0x34 4 0x34 4 (ASSERT_SET | DEASSERT_CLEAR | STATUS_SET)>; |
| 483 | }; |
| 484 | }; |
| 485 | |
| 486 | eth: ethernet@15100000 { |
| 487 | compatible = "mediatek,mt7986-eth"; |
| 488 | reg = <0 0x15100000 0 0x80000>; |
| 489 | interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, |
| 490 | <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, |
| 491 | <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, |
| 492 | <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 493 | clocks = <ðsys CK_ETH_FE_EN>, |
| 494 | <ðsys CK_ETH_GP2_EN>, |
| 495 | <ðsys CK_ETH_GP1_EN>, |
| 496 | <ðsys CK_ETH_WOCPU1_EN>, |
| 497 | <ðsys CK_ETH_WOCPU0_EN>, |
developer | 77bbf43 | 2021-06-28 18:39:08 +0800 | [diff] [blame] | 498 | <&sgmiisys0 CK_SGM0_TX_EN>, |
| 499 | <&sgmiisys0 CK_SGM0_RX_EN>, |
| 500 | <&sgmiisys0 CK_SGM0_CK0_EN>, |
| 501 | <&sgmiisys0 CK_SGM0_CDR_CK0_EN>, |
| 502 | <&sgmiisys1 CK_SGM1_TX_EN>, |
| 503 | <&sgmiisys1 CK_SGM1_RX_EN>, |
| 504 | <&sgmiisys1 CK_SGM1_CK1_EN>, |
| 505 | <&sgmiisys1 CK_SGM1_CDR_CK1_EN>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 506 | clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0", |
| 507 | "sgmii_tx250m", "sgmii_rx250m", |
| 508 | "sgmii_cdr_ref", "sgmii_cdr_fb", |
| 509 | "sgmii2_tx250m", "sgmii2_rx250m", |
| 510 | "sgmii2_cdr_ref", "sgmii2_cdr_fb"; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 511 | assigned-clocks = <&topckgen CK_TOP_NETSYS_2X_SEL>, |
| 512 | <&topckgen CK_TOP_SGM_325M_SEL>; |
| 513 | assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_800M>, |
| 514 | <&topckgen CK_TOP_CB_SGM_325M>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 515 | mediatek,ethsys = <ðsys>; |
| 516 | mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; |
| 517 | #reset-cells = <1>; |
| 518 | #address-cells = <1>; |
| 519 | #size-cells = <0>; |
| 520 | status = "disabled"; |
| 521 | }; |
| 522 | |
| 523 | hnat: hnat@15000000 { |
| 524 | compatible = "mediatek,mtk-hnat_v4"; |
| 525 | reg = <0 0x15100000 0 0x80000>; |
| 526 | resets = <ðsys 0>; |
| 527 | reset-names = "mtketh"; |
| 528 | status = "disabled"; |
| 529 | }; |
| 530 | |
| 531 | sgmiisys0: syscon@10060000 { |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 532 | compatible = "mediatek,mt7986-sgmiisys", |
| 533 | "mediatek,mt7986-sgmiisys_0", |
| 534 | "syscon"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 535 | reg = <0 0x10060000 0 0x1000>; |
| 536 | #clock-cells = <1>; |
| 537 | }; |
| 538 | |
| 539 | sgmiisys1: syscon@10070000 { |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 540 | compatible = "mediatek,mt7986-sgmiisys", |
| 541 | "mediatek,mt7986-sgmiisys_1", |
| 542 | "syscon"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 543 | reg = <0 0x10070000 0 0x1000>; |
| 544 | #clock-cells = <1>; |
| 545 | }; |
| 546 | |
| 547 | snand: snfi@11005000 { |
| 548 | compatible = "mediatek,mt7986-snand"; |
| 549 | reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>; |
| 550 | reg-names = "nfi", "ecc"; |
| 551 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 552 | clocks = <&topckgen CK_TOP_SPINFI_SEL>, |
| 553 | <&infracfg_ao CK_INFRA_SPINFI1_CK>, |
| 554 | <&topckgen CK_TOP_NFI1X_SEL>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 555 | clock-names = "nfi_clk", "pad_clk", "ecc_clk"; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 556 | assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>, |
| 557 | <&topckgen CK_TOP_NFI1X_SEL>; |
| 558 | assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M_D2>, |
| 559 | <&topckgen CK_TOP_CB_CKSQ_40M>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 560 | #address-cells = <1>; |
| 561 | #size-cells = <0>; |
| 562 | status = "disabled"; |
| 563 | }; |
| 564 | |
| 565 | wbsys: wbsys@18000000 { |
| 566 | compatible = "mediatek,wbsys"; |
| 567 | reg = <0 0x18000000 0 0x1000000>; |
| 568 | interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, |
| 569 | <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, |
| 570 | <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, |
| 571 | <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; |
| 572 | chip_id = <0x7986>; |
| 573 | }; |
| 574 | |
| 575 | wed_pcie: wed_pcie@10003000 { |
| 576 | compatible = "mediatek,wed_pcie"; |
| 577 | reg = <0 0x10003000 0 0x10>; |
| 578 | }; |
| 579 | |
| 580 | spi0: spi@1100a000 { |
| 581 | compatible = "mediatek,ipm-spi"; |
| 582 | reg = <0 0x1100a000 0 0x100>; |
| 583 | interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 584 | clocks = <&topckgen CK_TOP_CB_M_D2>, |
| 585 | <&infracfg_ao CK_INFRA_SPI0_CK>, |
| 586 | <&topckgen CK_TOP_SPI_SEL>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 587 | clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| 588 | status = "disabled"; |
| 589 | }; |
| 590 | |
| 591 | spi1: spi@1100b000 { |
| 592 | compatible = "mediatek,ipm-spi"; |
| 593 | reg = <0 0x1100b000 0 0x100>; |
| 594 | interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 595 | clocks = <&topckgen CK_TOP_CB_M_D2>, |
| 596 | <&infracfg_ao CK_INFRA_SPI1_CK>, |
| 597 | <&topckgen CK_TOP_SPIM_MST_SEL>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 598 | clock-names = "parent-clk", "sel-clk", "spi-clk"; |
| 599 | status = "disabled"; |
| 600 | }; |
| 601 | |
developer | 637f555 | 2021-05-27 17:45:27 +0800 | [diff] [blame] | 602 | mmc0: mmc@11230000 { |
| 603 | compatible = "mediatek,mt7986-mmc"; |
| 604 | reg = <0 0x11230000 0 0x1000>, |
| 605 | <0 0x11c20000 0 0x1000>; |
| 606 | interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 607 | clocks = <&topckgen CK_TOP_EMMC_416M>, |
| 608 | <&topckgen CK_TOP_EMMC_250M>, |
| 609 | <&infracfg_ao CK_INFRA_MSDC_CK>; |
developer | 637f555 | 2021-05-27 17:45:27 +0800 | [diff] [blame] | 610 | clock-names = "source", "hclk", "source_cg"; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 611 | assigned-clocks = <&topckgen CK_TOP_EMMC_416M_SEL>, |
| 612 | <&topckgen CK_TOP_EMMC_250M_SEL>; |
| 613 | assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, |
| 614 | <&topckgen CK_TOP_CB_CKSQ_40M>; |
developer | 637f555 | 2021-05-27 17:45:27 +0800 | [diff] [blame] | 615 | status = "disabled"; |
| 616 | }; |
| 617 | |
developer | ee2df73 | 2021-05-21 15:19:42 +0800 | [diff] [blame] | 618 | auxadc: adc@1100d000 { |
| 619 | compatible = "mediatek,mt7986-auxadc", |
| 620 | "mediatek,mt7622-auxadc"; |
| 621 | reg = <0 0x1100d000 0 0x1000>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 622 | clocks = <&infracfg_ao CK_INFRA_ADC_26M_CK>; |
developer | ee2df73 | 2021-05-21 15:19:42 +0800 | [diff] [blame] | 623 | clock-names = "main"; |
| 624 | #io-channel-cells = <1>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 625 | status = "disabled"; |
developer | ee2df73 | 2021-05-21 15:19:42 +0800 | [diff] [blame] | 626 | }; |
| 627 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 628 | consys: consys@10000000 { |
| 629 | compatible = "mediatek,mt7986-consys"; |
| 630 | reg = <0 0x10000000 0 0x8600000>; |
| 631 | memory-region = <&wmcpu_emi>; |
| 632 | }; |
| 633 | |
| 634 | xhci: xhci@11200000 { |
| 635 | compatible = "mediatek,mt7986-xhci", |
| 636 | "mediatek,mtk-xhci"; |
| 637 | reg = <0 0x11200000 0 0x2e00>, |
| 638 | <0 0x11203e00 0 0x0100>; |
| 639 | reg-names = "mac", "ippc"; |
| 640 | interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; |
| 641 | phys = <&u2port0 PHY_TYPE_USB2>, |
| 642 | <&u3port0 PHY_TYPE_USB3>, |
| 643 | <&u2port1 PHY_TYPE_USB2>; |
| 644 | clocks = <&system_clk>, |
| 645 | <&system_clk>, |
| 646 | <&system_clk>, |
| 647 | <&system_clk>, |
| 648 | <&system_clk>; |
| 649 | clock-names = "sys_ck", |
| 650 | "xhci_ck", |
| 651 | "ref_ck", |
| 652 | "mcu_ck", |
| 653 | "dma_ck"; |
| 654 | #address-cells = <2>; |
| 655 | #size-cells = <2>; |
| 656 | status = "okay"; |
| 657 | }; |
| 658 | |
| 659 | usbtphy: usb-phy@11e10000 { |
| 660 | compatible = "mediatek,mt7986", |
| 661 | "mediatek,generic-tphy-v2"; |
| 662 | #address-cells = <2>; |
| 663 | #size-cells = <2>; |
| 664 | ranges; |
| 665 | status = "okay"; |
| 666 | |
| 667 | u2port0: usb-phy@11e10000 { |
| 668 | reg = <0 0x11e10000 0 0x700>; |
| 669 | clocks = <&system_clk>; |
| 670 | clock-names = "ref"; |
| 671 | #phy-cells = <1>; |
| 672 | status = "okay"; |
| 673 | }; |
| 674 | |
| 675 | u3port0: usb-phy@11e10700 { |
| 676 | reg = <0 0x11e10700 0 0x900>; |
| 677 | clocks = <&system_clk>; |
| 678 | clock-names = "ref"; |
| 679 | #phy-cells = <1>; |
| 680 | status = "okay"; |
| 681 | }; |
| 682 | |
| 683 | u2port1: usb-phy@11e11000 { |
| 684 | reg = <0 0x11e11000 0 0x700>; |
| 685 | clocks = <&system_clk>; |
| 686 | clock-names = "ref"; |
| 687 | #phy-cells = <1>; |
| 688 | status = "okay"; |
| 689 | }; |
| 690 | }; |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 691 | |
| 692 | clkitg: clkitg { |
| 693 | compatible = "simple-bus"; |
| 694 | }; |
developer | fbbf02b | 2021-06-25 09:30:28 +0800 | [diff] [blame] | 695 | |
developer | e1993bd | 2021-07-06 13:48:40 +0800 | [diff] [blame] | 696 | afe: audio-controller@11210000 { |
| 697 | compatible = "mediatek,mt7986-audio"; |
| 698 | reg = <0 0x11210000 0 0x9000>; |
| 699 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
| 700 | clocks = <&infracfg_ao CK_INFRA_AUD_BUS_CK>, |
| 701 | <&infracfg_ao CK_INFRA_AUD_26M_CK>, |
| 702 | <&infracfg_ao CK_INFRA_AUD_L_CK>, |
| 703 | <&infracfg_ao CK_INFRA_AUD_AUD_CK>, |
| 704 | <&infracfg_ao CK_INFRA_AUD_EG2_CK>; |
| 705 | clock-names = "aud_bus_ck", |
| 706 | "aud_26m_ck", |
| 707 | "aud_l_ck", |
| 708 | "aud_aud_ck", |
| 709 | "aud_eg2_ck"; |
| 710 | assigned-clocks = <&topckgen CK_TOP_A1SYS_SEL>, |
| 711 | <&topckgen CK_TOP_AUD_L_SEL>, |
| 712 | <&topckgen CK_TOP_A_TUNER_SEL>; |
| 713 | assigned-clock-parents = <&topckgen CK_TOP_APLL2_D4>, |
| 714 | <&topckgen CK_TOP_CB_APLL2_196M>, |
| 715 | <&topckgen CK_TOP_APLL2_D4>; |
| 716 | }; |
| 717 | |
developer | fbbf02b | 2021-06-25 09:30:28 +0800 | [diff] [blame] | 718 | trng: trng@1020f000 { |
| 719 | compatible = "mediatek,mt7986-rng", |
| 720 | "mediatek,mt7623-rng"; |
| 721 | reg = <0 0x1020f000 0 0x100>; |
| 722 | clocks = <&infracfg_ao CK_INFRA_TRNG_CK>; |
| 723 | clock-names = "rng"; |
| 724 | }; |
developer | 86ee1e1 | 2021-06-30 11:18:53 +0800 | [diff] [blame] | 725 | |
| 726 | ice: ice_debug { |
| 727 | compatible = "mediatek,mt7986-ice_debug", |
| 728 | "mediatek,mt2701-ice_debug"; |
| 729 | clocks = <&infracfg_ao CK_INFRA_DBG_CK>; |
| 730 | clock-names = "ice_dbg"; |
| 731 | }; |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 732 | |
| 733 | efuse: efuse@11d00000 { |
| 734 | compatible = "mediatek,mt7986-efuse", |
| 735 | "mediatek,efuse"; |
| 736 | reg = <0 0x11d00000 0 0x1000>; |
| 737 | #address-cells = <1>; |
| 738 | #size-cells = <1>; |
| 739 | |
| 740 | thermal_calibration: calib@274 { |
| 741 | reg = <0x274 0xc>; |
| 742 | }; |
| 743 | }; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 744 | }; |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 745 | |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 746 | #include "mt7986-clkitg.dtsi" |