blob: c128bbe9f3cd3b6faa07da79a866c60777ae97be [file] [log] [blame]
developer5d148cb2023-06-02 13:08:11 +08001From 2fd17c806f5ad23f9958c358cdc26f618f05d5df Mon Sep 17 00:00:00 2001
2From: Sam Shih <sam.shih@mediatek.com>
3Date: Fri, 2 Jun 2023 13:06:32 +0800
4Subject: [PATCH]
5 [networking][999-2719-net-phy-aquantia-add-firmware-download.patch]
6
7---
8 drivers/net/phy/Kconfig | 33 +-
9 drivers/net/phy/Makefile | 3 +
10 drivers/net/phy/aquantia.h | 64 ++
11 drivers/net/phy/aquantia_firmware.c | 1090 +++++++++++++++++++++++++++
12 drivers/net/phy/aquantia_main.c | 92 ++-
13 5 files changed, 1241 insertions(+), 41 deletions(-)
14 create mode 100644 drivers/net/phy/aquantia_firmware.c
15
developer122ffbb2022-11-14 12:07:10 +080016diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
developer5d148cb2023-06-02 13:08:11 +080017index c0e09c99d..d467834eb 100644
developer122ffbb2022-11-14 12:07:10 +080018--- a/drivers/net/phy/Kconfig
19+++ b/drivers/net/phy/Kconfig
developer301205c2023-05-24 15:39:32 +080020@@ -372,7 +372,38 @@ config AMD_PHY
developer122ffbb2022-11-14 12:07:10 +080021 config AQUANTIA_PHY
22 tristate "Aquantia PHYs"
23 ---help---
24- Currently supports the Aquantia AQ1202, AQ2104, AQR105, AQR405
25+ Currently supports the Aquantia AQ1202, AQ2104, AQR105, AQR405, AQR113C
26+
27+config AQUANTIA_PHY_FW_DOWNLOAD
28+ tristate "Firmware Download Enable"
29+ depends on AQUANTIA_PHY
30+ ---help---
31+ Currently supports the Aquantia AQR113C
32+
33+choice
34+ prompt "Download mode"
35+ default AQUANTIA_PHY_FW_DOWNLOAD_GANG
36+ depends on AQUANTIA_PHY_FW_DOWNLOAD
37+
38+ config AQUANTIA_PHY_FW_DOWNLOAD_SINGLE
39+ bool "Single"
40+ ---help---
41+ If you would like to download firmware in sequential way,
42+ please select this option.
43+
44+ config AQUANTIA_PHY_FW_DOWNLOAD_GANG
45+ bool "Gang"
46+ ---help---
47+ If you would like to download firmware in parallel way,
48+ please select this option.
49+endchoice
50+
51+config AQUANTIA_PHY_FW_FILE
52+ string "FW File"
53+ depends on AQUANTIA_PHY
54+ default "Rhe-05.06-Candidate7-AQR_Mediatek_23B_StartOff_ID45623_VER36657.cld"
55+ ---help---
56+ Currently supports the Aquantia AQR113c
57
58 config AX88796B_PHY
59 tristate "Asix PHYs"
60diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
developer5d148cb2023-06-02 13:08:11 +080061index 8b57d6105..e9653de36 100644
developer122ffbb2022-11-14 12:07:10 +080062--- a/drivers/net/phy/Makefile
63+++ b/drivers/net/phy/Makefile
developer5d148cb2023-06-02 13:08:11 +080064@@ -68,6 +68,9 @@ aquantia-objs += aquantia_main.o
developer122ffbb2022-11-14 12:07:10 +080065 ifdef CONFIG_HWMON
66 aquantia-objs += aquantia_hwmon.o
67 endif
68+ifdef CONFIG_AQUANTIA_PHY_FW_DOWNLOAD
69+aquantia-objs += aquantia_firmware.o
70+endif
developer122ffbb2022-11-14 12:07:10 +080071 obj-$(CONFIG_AIROHA_EN8801SC_PHY) += en8801sc.o
developer5d148cb2023-06-02 13:08:11 +080072 obj-$(CONFIG_AIROHA_EN8811H_PHY) += air_en8811h.o
developer122ffbb2022-11-14 12:07:10 +080073 obj-$(CONFIG_AQUANTIA_PHY) += aquantia.o
74diff --git a/drivers/net/phy/aquantia.h b/drivers/net/phy/aquantia.h
developer5d148cb2023-06-02 13:08:11 +080075index 5a16caab7..ab1c241d3 100644
developer122ffbb2022-11-14 12:07:10 +080076--- a/drivers/net/phy/aquantia.h
77+++ b/drivers/net/phy/aquantia.h
developer08abacf2023-05-18 15:52:22 +080078@@ -9,8 +9,72 @@
developer122ffbb2022-11-14 12:07:10 +080079 #include <linux/device.h>
80 #include <linux/phy.h>
81
developer08abacf2023-05-18 15:52:22 +080082+#define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4
83+
developer94316402022-11-21 08:58:41 +080084+#define PMAPMD_RSVD_VEND_PROV 0xe400
85+#define PMAPMD_RSVD_VEND_PROV_MDI_CONF BIT(0)
86+
developer122ffbb2022-11-14 12:07:10 +080087+/* MDIO_MMD_C22EXT */
88+#define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292
89+#define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294
90+#define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297
91+#define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313
92+#define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315
93+#define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317
94+#define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318
95+#define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319
96+#define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a
97+#define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b
98+
99+struct aqr107_hw_stat {
100+ const char *name;
101+ int reg;
102+ int size;
103+};
104+
105+#define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s }
106+static const struct aqr107_hw_stat aqr107_hw_stats[] = {
107+ SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26),
108+ SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26),
109+ SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8),
110+ SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26),
111+ SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26),
112+ SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8),
113+ SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8),
114+ SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8),
115+ SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16),
116+ SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22),
117+};
118+#define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats)
119+
120+struct aqr107_priv {
121+ u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
122+#ifdef CONFIG_AQUANTIA_PHY_FW_DOWNLOAD
123+ struct phy_device *phydevs[1];
developer7ddeff02023-03-22 15:28:46 +0800124+ struct task_struct *heartbeat_thread;
developer08abacf2023-05-18 15:52:22 +0800125+ spinlock_t lock;
developer122ffbb2022-11-14 12:07:10 +0800126+ bool fw_initialized;
developer093e9b32022-12-13 16:08:34 +0800127+ int fw_dl_mode;
developer7ddeff02023-03-22 15:28:46 +0800128+ u16 heartbeat;
developer122ffbb2022-11-14 12:07:10 +0800129+#endif
130+};
131+
developer08abacf2023-05-18 15:52:22 +0800132+int aqr107_set_downshift(struct phy_device *phydev, u8 cnt);
133+void aqr107_chip_info(struct phy_device *phydev);
developer94316402022-11-21 08:58:41 +0800134+int aqr107_config_mdi(struct phy_device *phydev);
135+
developer122ffbb2022-11-14 12:07:10 +0800136 #if IS_REACHABLE(CONFIG_HWMON)
137 int aqr_hwmon_probe(struct phy_device *phydev);
138 #else
139 static inline int aqr_hwmon_probe(struct phy_device *phydev) { return 0; }
140 #endif
141+
142+#ifdef CONFIG_AQUANTIA_PHY_FW_DOWNLOAD
developer093e9b32022-12-13 16:08:34 +0800143+enum {
144+ FW_DL_SINGLE = 0,
145+ FW_DL_GNAGLOAD,
146+};
147+
developer08abacf2023-05-18 15:52:22 +0800148+int aqr_firmware_heartbeat_thread(void *data);
developer122ffbb2022-11-14 12:07:10 +0800149+int aqr_firmware_download(struct phy_device *phydev);
150+#endif
151diff --git a/drivers/net/phy/aquantia_firmware.c b/drivers/net/phy/aquantia_firmware.c
152new file mode 100644
developer5d148cb2023-06-02 13:08:11 +0800153index 000000000..d2828aad4
developer122ffbb2022-11-14 12:07:10 +0800154--- /dev/null
155+++ b/drivers/net/phy/aquantia_firmware.c
developerf3048b62023-06-05 18:00:04 +0800156@@ -0,0 +1,1091 @@
developer122ffbb2022-11-14 12:07:10 +0800157+// SPDX-License-Identifier: GPL-2.0
158+/* FW download driver for Aquantia PHY
159+ */
160+
161+#include <linux/phy.h>
162+#include <linux/of.h>
163+#include <linux/device.h>
164+#include <linux/firmware.h>
165+#include <linux/kthread.h>
166+
167+#include "aquantia.h"
168+
169+#undef AQ_VERBOSE
170+
171+#ifdef CONFIG_AQUANTIA_PHY_FW_DOWNLOAD_SINGLE
172+#define MAX_GANGLOAD_DEVICES 1
173+#elif CONFIG_AQUANTIA_PHY_FW_DOWNLOAD_GANG
174+#define MAX_GANGLOAD_DEVICES 2
175+#endif
176+
177+#define AQR_FIRMWARE CONFIG_AQUANTIA_PHY_FW_FILE
178+
179+/* Vendor specific 1, MDIO_MMD_VEND1 */
180+#define VEND1_STD_CONTROL1 0x0000
181+#define VEND1_STD_CONTROL1_SOFT_RESET BIT(15)
182+
183+#define VEND1_MAILBOX_INTERFACE1 0x0200
184+#define VEND1_MAILBOX_INTERFACE1_START BIT(15)
185+#define VEND1_MAILBOX_INTERFACE1_WRITE FIELD_PREP(BIT(14), 1)
186+#define VEND1_MAILBOX_INTERFACE1_READ FIELD_PREP(BIT(14), 0)
187+#define VEND1_MAILBOX_INTERFACE1_RESET_CRC BIT(12)
188+
189+#define VEND1_MAILBOX_INTERFACE2 0x0201
190+#define VEND1_MAILBOX_INTERFACE2_CRC GENMASK(15, 0)
191+
192+#define VEND1_MAILBOX_INTERFACE3 0x0202
193+#define VEND1_MAILBOX_INTERFACE3_ADDR_MSW GENMASK(15, 0)
194+
195+#define VEND1_MAILBOX_INTERFACE4 0x0203
196+#define VEND1_MAILBOX_INTERFACE4_ADDR_LSW GENMASK(15, 2)
197+
198+#define VEND1_MAILBOX_INTERFACE5 0x0204
199+#define VEND1_MAILBOX_INTERFACE5_DATA_MSW GENMASK(15, 0)
200+
201+#define VEND1_MAILBOX_INTERFACE6 0x0205
202+#define VEND1_MAILBOX_INTERFACE6_DATA_LSW GENMASK(15, 0)
203+
204+#define VEND1_CONTROL2 0xc001
205+#define VEND1_CONTROL2_UP_RESET BIT(15)
206+#define VEND1_CONTROL2_UP_RUNSTALL_OVERRIDE BIT(6)
207+#define VEND1_CONTROL2_UP_RUNSTALL BIT(0)
208+
209+#define VEND1_RESET_CONTROL 0xc006
210+#define VEND1_RESET_CONTROL_MMD_RESET_DISABLE BIT(14)
211+
212+#define VEND1_GENERAL_PROV2 0xc441
213+#define VEND1_GENERAL_PROV2_MDIO_BROADCAST_ENABLE BIT(14)
214+
215+#define VEND1_GENERAL_PROV8 0xc447
216+#define VEND1_GENERAL_PROV8_MDIO_BROADCAST_ADDRESS GENMASK(4, 0)
217+
218+#define VEND1_NVR_PROV3 0xc452
219+#define VEND1_NVR_PROV3_DAISYCHAIN_DISABLE BIT(0)
220+
221+#define VEND1_RSVD_PROV2 0xc471
222+#define VEND1_RSVD_PROV2_DAISYCHAIN_HOPCOUNT GENMASK(5, 0)
223+#define VEND1_RSVD_PROV2_DAISYCHAIN_HOPCOUNT_OVERRIDE BIT(6)
224+
developeraafac652023-01-18 09:41:27 +0800225+#define VEND1_GLOBAL_RSVD_STAT2 0xc886
226+
developer122ffbb2022-11-14 12:07:10 +0800227+/*! The byte address, in processor memory, of the start of the IRAM segment. */
228+#define AQ_IRAM_BASE_ADDRESS 0x40000000
229+
230+/*! The byte address, in processor memory, of the start of the DRAM segment. */
231+#define AQ_DRAM_BASE_ADDRESS 0x3FFE0000
232+
233+/*! The byte offset from the top of the PHY image to the header content (HHD & EUR devices). */
234+#define AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_HHD 0x300
235+
236+/*! The offset, from the start of DRAM, where the provisioning block begins. */
237+#define AQ_PHY_IMAGE_PROVTABLE_OFFSET 0x680
238+
239+/*! The offset, from the start of DRAM, where the provisioning block's ending address is recorded. */
240+#define AQ_PHY_IMAGE_PROVTABLE_TERM_OFFSET 0x028C
241+
242+/*! The size of the space alloted within the PHY image for the provisioning table. */
243+#define AQ_PHY_IMAGE_PROVTABLE_MAXSIZE 0x800
244+
245+/*! The maximum number of ports that can be MDIO bootloaded at once. */
246+#define AQ_MAX_NUM_PHY_IDS 48
247+
248+/*! This enumeration is used to describe the different types of
249+ Aquantia PHY.*/
250+typedef enum
251+{
252+ /*! 1/2/4-port package, 40nm architechture.*/
253+ AQ_DEVICE_APPIA,
254+ /*! 1/2/4-port package, first-generation 28nm architechture.*/
255+ AQ_DEVICE_HHD,
256+ /*! 1/2/4-port package, second-generation 28nm architechture.*/
257+ AQ_DEVICE_EUR,
258+ /*! 1/2/4-port package, third-generation 28nm architechture.*/
259+ AQ_DEVICE_CAL,
260+ /*! 1/2/4/8-port package, forth-generation 14nm architechture.*/
261+ AQ_DEVICE_RHEA,
262+ /*! 8-port package, fifth-generation 14nm architechture.*/
263+ AQ_DEVICE_DIONE
264+} AQ_API_Device;
265+
266+/*! The table used to compute CRC's within the PHY. */
267+const uint16_t AQ_CRC16Table[256] = {0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50a5, 0x60c6, 0x70e7,
268+ 0x8108, 0x9129, 0xa14a, 0xb16b, 0xc18c, 0xd1ad, 0xe1ce, 0xf1ef,
269+ 0x1231, 0x0210, 0x3273, 0x2252, 0x52b5, 0x4294, 0x72f7, 0x62d6,
270+ 0x9339, 0x8318, 0xb37b, 0xa35a, 0xd3bd, 0xc39c, 0xf3ff, 0xe3de,
271+ 0x2462, 0x3443, 0x0420, 0x1401, 0x64e6, 0x74c7, 0x44a4, 0x5485,
272+ 0xa56a, 0xb54b, 0x8528, 0x9509, 0xe5ee, 0xf5cf, 0xc5ac, 0xd58d,
273+ 0x3653, 0x2672, 0x1611, 0x0630, 0x76d7, 0x66f6, 0x5695, 0x46b4,
274+ 0xb75b, 0xa77a, 0x9719, 0x8738, 0xf7df, 0xe7fe, 0xd79d, 0xc7bc,
275+ 0x48c4, 0x58e5, 0x6886, 0x78a7, 0x0840, 0x1861, 0x2802, 0x3823,
276+ 0xc9cc, 0xd9ed, 0xe98e, 0xf9af, 0x8948, 0x9969, 0xa90a, 0xb92b,
277+ 0x5af5, 0x4ad4, 0x7ab7, 0x6a96, 0x1a71, 0x0a50, 0x3a33, 0x2a12,
278+ 0xdbfd, 0xcbdc, 0xfbbf, 0xeb9e, 0x9b79, 0x8b58, 0xbb3b, 0xab1a,
279+ 0x6ca6, 0x7c87, 0x4ce4, 0x5cc5, 0x2c22, 0x3c03, 0x0c60, 0x1c41,
280+ 0xedae, 0xfd8f, 0xcdec, 0xddcd, 0xad2a, 0xbd0b, 0x8d68, 0x9d49,
281+ 0x7e97, 0x6eb6, 0x5ed5, 0x4ef4, 0x3e13, 0x2e32, 0x1e51, 0x0e70,
282+ 0xff9f, 0xefbe, 0xdfdd, 0xcffc, 0xbf1b, 0xaf3a, 0x9f59, 0x8f78,
283+ 0x9188, 0x81a9, 0xb1ca, 0xa1eb, 0xd10c, 0xc12d, 0xf14e, 0xe16f,
284+ 0x1080, 0x00a1, 0x30c2, 0x20e3, 0x5004, 0x4025, 0x7046, 0x6067,
285+ 0x83b9, 0x9398, 0xa3fb, 0xb3da, 0xc33d, 0xd31c, 0xe37f, 0xf35e,
286+ 0x02b1, 0x1290, 0x22f3, 0x32d2, 0x4235, 0x5214, 0x6277, 0x7256,
287+ 0xb5ea, 0xa5cb, 0x95a8, 0x8589, 0xf56e, 0xe54f, 0xd52c, 0xc50d,
288+ 0x34e2, 0x24c3, 0x14a0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
289+ 0xa7db, 0xb7fa, 0x8799, 0x97b8, 0xe75f, 0xf77e, 0xc71d, 0xd73c,
290+ 0x26d3, 0x36f2, 0x0691, 0x16b0, 0x6657, 0x7676, 0x4615, 0x5634,
291+ 0xd94c, 0xc96d, 0xf90e, 0xe92f, 0x99c8, 0x89e9, 0xb98a, 0xa9ab,
292+ 0x5844, 0x4865, 0x7806, 0x6827, 0x18c0, 0x08e1, 0x3882, 0x28a3,
293+ 0xcb7d, 0xdb5c, 0xeb3f, 0xfb1e, 0x8bf9, 0x9bd8, 0xabbb, 0xbb9a,
294+ 0x4a75, 0x5a54, 0x6a37, 0x7a16, 0x0af1, 0x1ad0, 0x2ab3, 0x3a92,
295+ 0xfd2e, 0xed0f, 0xdd6c, 0xcd4d, 0xbdaa, 0xad8b, 0x9de8, 0x8dc9,
296+ 0x7c26, 0x6c07, 0x5c64, 0x4c45, 0x3ca2, 0x2c83, 0x1ce0, 0x0cc1,
297+ 0xef1f, 0xff3e, 0xcf5d, 0xdf7c, 0xaf9b, 0xbfba, 0x8fd9, 0x9ff8,
298+ 0x6e17, 0x7e36, 0x4e55, 0x5e74, 0x2e93, 0x3eb2, 0x0ed1, 0x1ef0};
299+
300+struct task_struct *gangload_kthread = NULL;
301+struct phy_device *gangload_phydevs[MAX_GANGLOAD_DEVICES];
302+static int gangload = 0;
303+
developeraafac652023-01-18 09:41:27 +0800304+static int aqr_firmware_download_single(struct phy_device *phydev);
305+
developer122ffbb2022-11-14 12:07:10 +0800306+void AQ_API_EnableMDIO_BootLoadMode
307+(
308+ /*! The target PHY port.*/
309+ struct phy_device *phydev,
310+ /*! The provisioning address to use when the FW starts and applies the
311+ * bootloaded image's provisioned values. */
312+ unsigned int provisioningAddress
313+)
314+{
315+ uint16_t globalNvrProvisioning;
316+ uint16_t globalReservedProvisioning;
317+
318+ /* disable the daisy-chain */
319+ globalNvrProvisioning = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_NVR_PROV3);
320+ globalNvrProvisioning |= VEND1_NVR_PROV3_DAISYCHAIN_DISABLE;
321+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_NVR_PROV3, globalNvrProvisioning);
322+
323+ /* override the hop-count */
324+ globalReservedProvisioning = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_RSVD_PROV2);
325+ globalReservedProvisioning &= ~VEND1_RSVD_PROV2_DAISYCHAIN_HOPCOUNT;
326+ globalReservedProvisioning |= FIELD_PREP(VEND1_RSVD_PROV2_DAISYCHAIN_HOPCOUNT,
327+ provisioningAddress);
328+ globalReservedProvisioning |= VEND1_RSVD_PROV2_DAISYCHAIN_HOPCOUNT_OVERRIDE;
329+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_RSVD_PROV2, globalReservedProvisioning);
330+
331+ return;
332+}
333+
334+/*! Prepare the specified port for MDIO bootloading, and set the temporary MDIO
335+ * address to be used during the bootload process. Disables the daisy-chain,
336+ * and explicitly sets the port's provisioningAddress. */
337+void AQ_API_EnableGangLoadMode
338+(
339+ /*! The target PHY port.*/
340+ struct phy_device *phydev,
341+ /*! The PHY's MDIO address will be changed to this value during the
342+ * bootload process. */
343+ unsigned int gangLoadAddress
344+)
345+{
346+ uint16_t globalGeneralProvisioning;
347+
348+ /* Enable gangload mode. After doing this, the PHY will be
349+ * addressable at the MDIO address indicated by gangLoadAddress.
350+ * Now that the PHY is in gangload mode, MDIO reads are prohibited
351+ * until AQ_API_DisableGangLoadMode is called. */
352+ globalGeneralProvisioning = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GENERAL_PROV8);
353+ globalGeneralProvisioning &= ~VEND1_GENERAL_PROV8_MDIO_BROADCAST_ADDRESS;
354+ globalGeneralProvisioning |= FIELD_PREP(VEND1_GENERAL_PROV8_MDIO_BROADCAST_ADDRESS,
355+ gangLoadAddress);
356+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GENERAL_PROV8, globalGeneralProvisioning);
357+
358+ globalGeneralProvisioning = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GENERAL_PROV2);
359+ globalGeneralProvisioning |= VEND1_GENERAL_PROV2_MDIO_BROADCAST_ENABLE;
360+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GENERAL_PROV2, globalGeneralProvisioning);
361+
362+ return;
363+}
364+
365+/*! Restore the PHY's MDIO address to the pin-specified value. Should be
366+ * called when MDIO bootloading is complete, to return to normal MDIO
367+ * addressing.
368+ * <b>This is a gang-load function, hence write-only!</b> */
369+void AQ_API_DisableGangLoadMode
370+(
371+ /*! The target PHY port.*/
372+ struct phy_device *phydev,
373+ /*! The value to write to of AQ_GlobalGeneralProvisioning.u1.word_1. */
374+ uint16_t origVal_GGP1
375+)
376+{
377+ uint16_t globalGeneralProvisioning;
378+
379+ /* Restore the original value of globalGeneralProvisioning.u1, and set
380+ * the MDIO address reset bit. This will cause the MDIO address to be
381+ * reset to the value indicated by the pins. */
382+ globalGeneralProvisioning = origVal_GGP1;
383+ globalGeneralProvisioning &= ~VEND1_GENERAL_PROV2_MDIO_BROADCAST_ENABLE;
384+ phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GENERAL_PROV2, globalGeneralProvisioning);
385+
386+ /* The PHY has now exited gang-load mode. */
387+ return;
388+}
389+
390+/* Common implementation of MDIO bootload routine, for the entry points:
391+ * AQ_API_WriteBootLoadImage
392+ * AQ_API_WriteBootLoadImageWithProvTable
393+ * AQ_API_WriteBootLoadImageDRAMOnly
394+ * AQ_API_WriteBootLoadImageWithProvTableDRAMOnly */
395+static int AQ_API_WriteBootLoadImage_impl
396+(
397+ struct phy_device **phydevs,
398+ int num_phydevs,
399+ struct phy_device *gandload_phydev,
400+ int *result,
401+ const uint32_t* imageSizePointer,
402+ const uint8_t* image,
403+ const uint32_t* provTableSizePointer,
404+ const uint8_t* provTableImage,
405+ bool dramOnly
406+)
407+{
408+ uint32_t primaryHeaderPtr = 0x00000000;
409+ uint32_t primaryIramPtr = 0x00000000;
410+ uint32_t primaryDramPtr = 0x00000000;
411+ uint32_t primaryIramSize = 0x00000000;
412+ uint32_t primaryDramSize = 0x00000000;
413+ uint32_t terminatorPtr = 0x00000000;
414+ uint32_t phyImageHeaderContentOffset = 0x00000000;
415+ uint32_t i, j;
416+ uint32_t imageSize;
417+ uint32_t provTableImageSize = 0;
418+ uint32_t bytePointer;
419+ uint32_t byteSize;
420+ uint32_t dWordSize;
421+#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE
422+ uint32_t countPendingOps; /* A count of block MDIO operation pending... necessary to keep a count
423+ in order to ensure we don't exceed the maximum pending operations. */
424+#endif
425+ uint16_t globalControl;
426+ uint16_t msw;
427+ uint16_t lsw;
428+ uint16_t crc16Calculated;
429+ uint16_t provTableCrc16Calculated;
430+ uint16_t fileCRC;
431+ uint16_t provTableFileCRC;
432+ uint16_t mailboxCRC;
433+ uint16_t mailboxWrite;
434+ uint16_t recordedGGP1Values[AQ_MAX_NUM_PHY_IDS]; /* When entering/exiting gangload mode, we record and restore
435+ the AQ_GlobalGeneralProvisioning.u1 register values. */
436+
437+ /* store the CRC-16 for the image, which is the last two bytes */
438+ imageSize = *imageSizePointer;
439+
440+ /*
441+ * If the imageSize is less than 2, we don't do anything
442+ */
443+ if (imageSize < 2) {
444+ result[0] = -EINVAL;
445+ return -EINVAL;
446+ }
447+
448+ fileCRC = image[imageSize-2] << 8 | image[imageSize-1];
449+
450+ /*------------------------------------- Check the image integrity ------------------------------------------------*/
451+ crc16Calculated = 0x0000;
452+ for (i = 0; i < imageSize-2; i++)
453+ {
454+ crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ image[i]];
455+ }
456+
457+ if (crc16Calculated != fileCRC)
458+ {
459+ phydev_err(phydevs[0], "CRC check failed on image file (expected 0x%X, found 0x%X)\n",
460+ fileCRC, crc16Calculated);
461+ result[0] = -EINVAL;
462+ return -EINVAL;
463+ }
464+ else
465+ {
466+ phydev_info(phydevs[0], "CRC check good on image file (0x%04X)\n", crc16Calculated);
467+ }
468+
469+ /*-------------------------------- Check the provisioning table image integrity ----------------------------------*/
470+ if (provTableSizePointer != NULL && provTableImage != NULL)
471+ {
472+ provTableImageSize = (*provTableSizePointer) - 2;
473+ provTableFileCRC = provTableImage[provTableImageSize + 1] << 8 |
474+ provTableImage[provTableImageSize];
475+
476+ provTableCrc16Calculated = 0x0000;
477+ for (i = 0; i < provTableImageSize; i++)
478+ {
479+ provTableCrc16Calculated = ((provTableCrc16Calculated & 0xFF) << 8) ^
480+ AQ_CRC16Table[(provTableCrc16Calculated >> 8) ^ provTableImage[i]];
481+ }
482+
483+ if (provTableCrc16Calculated != provTableFileCRC)
484+ {
485+ phydev_err(phydevs[0], "CRC check failed on provisioning table file (expected 0x%X, found 0x%X)\n",
486+ provTableFileCRC, provTableCrc16Calculated);
487+ result[0] = -EINVAL;
488+ return -EINVAL;
489+ }
490+ else
491+ {
492+ phydev_info(phydevs[0], "CRC check good on provisioning table file (0x%04X)\n",
493+ provTableCrc16Calculated);
494+ }
495+ }
496+
497+ /*--------------------------- Store 1E.C441 values for later use. Enforce uniformity. ---------------------------*/
498+ for (j = 0; j < num_phydevs; j++)
499+ {
500+ /* Record the original value of AQ_GlobalGeneralProvisioning.u1.word_1,
501+ * so that we can restore it later after exiting gangload mode. */
502+ recordedGGP1Values[j] = phy_read_mmd(phydevs[j], MDIO_MMD_VEND1, VEND1_GENERAL_PROV2);
503+
504+ /* If any of the PHYs' GGP1 values don't match the others, set the appropriate
505+ * error code and return. */
506+ if (j > 0 && recordedGGP1Values[j] != recordedGGP1Values[0])
507+ {
508+ phydev_err(phydevs[j], "Non-uniform value of 1E.C441 found (expected 0x%X, found 0x%X)\n",
509+ recordedGGP1Values[0], recordedGGP1Values[j]);
510+ result[j] = -EINVAL;
511+ return -EINVAL;
512+ }
513+ }
514+
515+ /*--------------------------- Put each PHY into gangload mode at the specified address ---------------------------*/
516+ for (j = 0; j < num_phydevs; j++) {
517+ AQ_API_EnableMDIO_BootLoadMode(phydevs[j], 0);
518+ AQ_API_EnableGangLoadMode(phydevs[j], gandload_phydev->mdio.addr);
519+ }
520+
521+ /*------------------------------------- Stall the uP ------------------------------------------------------------*/
522+ globalControl = 0x0000;
523+ globalControl |= VEND1_CONTROL2_UP_RUNSTALL_OVERRIDE;
524+ globalControl |= VEND1_CONTROL2_UP_RUNSTALL;
525+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_CONTROL2, globalControl);
526+
527+ /*------------------------------------- Initialize the mailbox write command -------------------------------------*/
528+ mailboxWrite = 0x0000;
529+ mailboxWrite |= VEND1_MAILBOX_INTERFACE1_WRITE;
530+ mailboxWrite |= VEND1_MAILBOX_INTERFACE1_START;
531+
532+ /*------------------------------------- Read the segment addresses and sizes -------------------------------------*/
533+ primaryHeaderPtr = (((image[0x9] & 0x0F) << 8) | image[0x8]) << 12;
534+
535+ /* setup image header content offset for HHD/EUR/CAL/RHEA */
536+ phyImageHeaderContentOffset = AQ_PHY_IMAGE_HEADER_CONTENT_OFFSET_HHD;
537+
538+ primaryIramPtr = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x4 + 2] << 16) |
539+ (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x4 + 1] << 8) |
540+ image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x4];
541+ primaryIramSize = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x7 + 2] << 16) |
542+ (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x7 + 1] << 8) |
543+ image[primaryHeaderPtr + phyImageHeaderContentOffset + 0x7];
544+ primaryDramPtr = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xA + 2] << 16) |
545+ (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xA + 1] << 8) |
546+ image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xA];
547+ primaryDramSize = (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xD + 2] << 16) |
548+ (image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xD + 1] << 8) |
549+ image[primaryHeaderPtr + phyImageHeaderContentOffset + 0xD];
550+
551+ /* setup primary image pointer for HHD/EUR/CAL/RHEA */
552+ primaryIramPtr += primaryHeaderPtr;
553+ primaryDramPtr += primaryHeaderPtr;
554+
555+ phydev_info(gandload_phydev, "Segment Addresses and Sizes as read from the PHY ROM image header:\n");
556+ phydev_info(gandload_phydev, "Primary Iram Address: 0x%x\n", primaryIramPtr);
557+ phydev_info(gandload_phydev, "Primary Iram Size: 0x%x\n", primaryIramSize);
558+ phydev_info(gandload_phydev, "Primary Dram Address: 0x%x\n", primaryDramPtr);
559+ phydev_info(gandload_phydev, "Primary Dram Size: 0x%x\n", primaryDramSize);
560+
561+ /*------------------ Prepare to merge the provisioning table into the main image ---------------------------------*/
562+ if (provTableSizePointer != NULL && provTableImage != NULL)
563+ {
564+ /* Locate the terminator of the built-in provisioning table */
565+ terminatorPtr = primaryDramPtr +
566+ ((image[primaryDramPtr + AQ_PHY_IMAGE_PROVTABLE_TERM_OFFSET + 1] << 8) |
567+ image[primaryDramPtr + AQ_PHY_IMAGE_PROVTABLE_TERM_OFFSET]);
568+
569+ phydev_info(gandload_phydev, "Supplied Provisioning Table At Address: 0x%x\n\n", terminatorPtr);
570+
571+ /* Check that the supplied provisioning table will fit within the alloted
572+ * space. */
573+ if (terminatorPtr - (primaryDramPtr + AQ_PHY_IMAGE_PROVTABLE_OFFSET) +
574+ provTableImageSize > AQ_PHY_IMAGE_PROVTABLE_MAXSIZE)
575+ {
576+ result[0] = -EINVAL;
577+ return -EINVAL;
578+ }
579+ }
580+
581+ /*------------------------------------- Load IRAM and DRAM -------------------------------------------------------*/
582+ /* clear the mailbox CRC */
583+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE1, VEND1_MAILBOX_INTERFACE1_RESET_CRC);
584+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE1, 0x0000);
585+
586+ crc16Calculated = 0; /* This is to calculate what was written through the mailbox */
587+
588+ if (!dramOnly)
589+ {
590+ /* load the IRAM */
591+ phydev_info(gandload_phydev, "Loading IRAM:\n");
592+
593+ /* dWord align the address: note the image addressing is byte based, but is properly aligned on dWord
594+ boundaries, so the 2 LSbits of the block start are always zero. */
595+ msw = (uint16_t) (AQ_IRAM_BASE_ADDRESS >> 16);
596+ lsw = (AQ_IRAM_BASE_ADDRESS & 0xFFFF) >> 2;
597+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE3, msw);
598+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE4, lsw);
599+
600+ /* set block size so that there are from 0-3 bytes remaining */
601+ byteSize = primaryIramSize;
602+ dWordSize = byteSize >> 2;
603+
604+ bytePointer = primaryIramPtr;
605+ #ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE
606+ countPendingOps = 0;
607+ #endif
608+ for (i = 0; i < dWordSize; i++)
609+ {
610+ /* write 4 bytes of data */
611+ if (terminatorPtr && (bytePointer >= terminatorPtr) && (bytePointer < terminatorPtr + provTableImageSize))
612+ lsw = provTableImage[bytePointer - terminatorPtr];
613+ else
614+ lsw = image[bytePointer];
615+
616+ if (terminatorPtr && ((bytePointer+1) >= terminatorPtr) && ((bytePointer+1) < terminatorPtr + provTableImageSize))
617+ lsw |= provTableImage[bytePointer + 1 - terminatorPtr] << 8;
618+ else
619+ lsw |= image[bytePointer+1] << 8;
620+
621+ bytePointer += 2;
622+
623+ if (terminatorPtr && (bytePointer >= terminatorPtr) && (bytePointer < terminatorPtr + provTableImageSize))
624+ msw = provTableImage[bytePointer - terminatorPtr];
625+ else
626+ msw = image[bytePointer];
627+
628+ if (terminatorPtr && ((bytePointer+1) >= terminatorPtr) && ((bytePointer+1) < terminatorPtr + provTableImageSize))
629+ msw |= provTableImage[bytePointer + 1 - terminatorPtr] << 8;
630+ else
631+ msw |= image[bytePointer+1] << 8;
632+
633+ bytePointer += 2;
634+
635+ #ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE
636+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE5, msw);
637+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE6, lsw);
638+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE1, mailboxWrite);
639+
640+ countPendingOps += 3;
641+ /* Check if we've filled our output buffer, and if so, flush. */
642+ #ifdef AQ_EXTRA_FLAGS
643+ if (countPendingOps >= AQ_API_MDIO_MaxBlockOperations(0) - 3)
644+ #else
645+ if (countPendingOps >= AQ_API_MDIO_MaxBlockOperations() - 3)
646+ #endif
647+ {
648+ AQ_API_MDIO_BlockOperationExecute(gandload_phydev);
649+ countPendingOps = 0;
650+ }
651+ #else
652+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE5, msw);
653+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE6, lsw);
654+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE1, mailboxWrite);
655+ #endif
656+
657+ /* update the calculated CRC */
658+ crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)];
659+ crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)];
660+ crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)];
661+ crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)];
662+
663+ #ifdef AQ_VERBOSE
664+ if (i && ((i % 512) == 0)) phydev_info(gandload_phydev, " Byte: %X:\n", i << 2);
665+ #endif
666+ }
667+
668+ #ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE
669+ /* flush the output buffer one last time. */
670+ AQ_API_MDIO_BlockOperationExecute(gandload_phydev);
671+ countPendingOps = 0;
672+ #endif
673+
674+ /* Note: this final write right-justifies non-dWord data in the final dWord */
675+ switch (byteSize & 0x3)
676+ {
677+ case 0x1:
678+ /* write 1 byte of data */
679+ if (terminatorPtr && (bytePointer >= terminatorPtr) && (bytePointer < terminatorPtr + provTableImageSize))
680+ lsw = provTableImage[bytePointer - terminatorPtr];
681+ else
682+ lsw = image[bytePointer];
683+
684+ bytePointer += 1;
685+
686+ msw = 0x0000;
687+
688+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE5, msw);
689+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE6, lsw);
690+
691+ /* no polling */
692+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE1, mailboxWrite);
693+ break;
694+
695+ case 0x2:
696+ /* write 2 bytes of data */
697+ if (terminatorPtr && (bytePointer >= terminatorPtr) && (bytePointer < terminatorPtr + provTableImageSize))
698+ lsw = provTableImage[bytePointer - terminatorPtr];
699+ else
700+ lsw = image[bytePointer];
701+
702+ if (terminatorPtr && ((bytePointer+1) >= terminatorPtr) && ((bytePointer+1) < terminatorPtr + provTableImageSize))
703+ lsw |= provTableImage[bytePointer + 1 - terminatorPtr] << 8;
704+ else
705+ lsw |= image[bytePointer+1] << 8;
706+
707+ bytePointer += 2;
708+
709+ msw = 0x0000;
710+
711+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE5, msw);
712+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE6, lsw);
713+
714+ /* no polling */
715+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE1, mailboxWrite);
716+ break;
717+
718+ case 0x3:
719+ /* write 3 bytes of data */
720+ if (terminatorPtr && (bytePointer >= terminatorPtr) && (bytePointer < terminatorPtr + provTableImageSize))
721+ lsw = provTableImage[bytePointer - terminatorPtr];
722+ else
723+ lsw = image[bytePointer];
724+
725+ if (terminatorPtr && ((bytePointer+1) >= terminatorPtr) && ((bytePointer+1) < terminatorPtr + provTableImageSize))
726+ lsw |= provTableImage[bytePointer + 1 - terminatorPtr] << 8;
727+ else
728+ lsw |= image[bytePointer+1] << 8;
729+
730+ bytePointer += 2;
731+
732+ if (terminatorPtr && (bytePointer >= terminatorPtr) && (bytePointer < terminatorPtr + provTableImageSize))
733+ msw = provTableImage[bytePointer - terminatorPtr];
734+ else
735+ msw = image[bytePointer];
736+
737+ bytePointer += 1;
738+
739+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE5, msw);
740+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE6, lsw);
741+
742+ /* no polling */
743+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE1, mailboxWrite);
744+ break;
745+ }
746+
747+ if (byteSize & 0x3)
748+ {
749+ /* update the calculated CRC */
750+ crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)];
751+ crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)];
752+ crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)];
753+ crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)];
754+ }
755+
756+ phydev_info(gandload_phydev, "CRC-16 after loading IRAM: 0x%X\n", crc16Calculated);
757+ }
758+
759+ /* load the DRAM */
760+ phydev_info(gandload_phydev, "Loading DRAM:\n");
761+
762+ /* dWord align the address: note the image addressing is byte based, but is properly aligned on dWord
763+ boundaries, so the 2 LSbits of the block start are always zero. */
764+ msw = (uint16_t) (AQ_DRAM_BASE_ADDRESS >> 16);
765+ lsw = (AQ_DRAM_BASE_ADDRESS & 0xFFFF) >> 2;
766+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE3, msw);
767+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE4, lsw);
768+
769+ /* set block size so that there are from 0-3 bytes remaining */
770+ byteSize = primaryDramSize;
771+ dWordSize = byteSize >> 2;
772+
773+ bytePointer = primaryDramPtr;
774+#ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE
775+ countPendingOps = 0;
776+#endif
777+ for (i = 0; i < dWordSize; i++)
778+ {
779+ /* write 4 bytes of data */
780+ if (terminatorPtr && (bytePointer >= terminatorPtr) && (bytePointer < terminatorPtr + provTableImageSize))
781+ lsw = provTableImage[bytePointer - terminatorPtr];
782+ else
783+ lsw = image[bytePointer];
784+
785+ if (terminatorPtr && ((bytePointer+1) >= terminatorPtr) && ((bytePointer+1) < terminatorPtr + provTableImageSize))
786+ lsw |= provTableImage[bytePointer + 1 - terminatorPtr] << 8;
787+ else
788+ lsw |= image[bytePointer+1] << 8;
789+
790+ bytePointer += 2;
791+
792+ if (terminatorPtr && (bytePointer >= terminatorPtr) && (bytePointer < terminatorPtr + provTableImageSize))
793+ msw = provTableImage[bytePointer - terminatorPtr];
794+ else
795+ msw = image[bytePointer];
796+
797+ if (terminatorPtr && ((bytePointer+1) >= terminatorPtr) && ((bytePointer+1) < terminatorPtr + provTableImageSize))
798+ msw |= provTableImage[bytePointer + 1 - terminatorPtr] << 8;
799+ else
800+ msw |= image[bytePointer+1] << 8;
801+
802+ bytePointer += 2;
803+
804+ #ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE
805+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE5, msw);
806+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE6, lsw);
807+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE1, mailboxWrite);
808+
809+ countPendingOps += 3;
810+ /* Check if we've filled our output buffer, and if so, flush. */
811+ #ifdef AQ_EXTRA_FLAGS
812+ if (countPendingOps >= AQ_API_MDIO_MaxBlockOperations(0) - 3)
813+ #else
814+ if (countPendingOps >= AQ_API_MDIO_MaxBlockOperations() - 3)
815+ #endif
816+ {
817+ AQ_API_MDIO_BlockOperationExecute(gandload_phydev);
818+ countPendingOps = 0;
819+ }
820+ #else
821+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE5, msw);
822+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE6, lsw);
823+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE1, mailboxWrite);
824+ #endif
825+
826+ /* update the calculated CRC */
827+ crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)];
828+ crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)];
829+ crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)];
830+ crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)];
831+
832+ #ifdef AQ_VERBOSE
833+ if (i && ((i % 512) == 0)) phydev_info(gandload_phydev, " Byte: %X:\n", i << 2);
834+ #endif
835+ }
836+
837+ #ifdef AQ_PHY_SUPPORTS_BLOCK_READ_WRITE
838+ /* flush the output buffer one last time. */
839+ AQ_API_MDIO_BlockOperationExecute(gandload_phydev);
840+ countPendingOps = 0;
841+ #endif
842+
843+ /* Note: this final write right-justifies non-dWord data in the final dWord */
844+ switch (byteSize & 0x3)
845+ {
846+ case 0x1:
847+ /* write 1 byte of data */
848+ if (terminatorPtr && (bytePointer >= terminatorPtr) && (bytePointer < terminatorPtr + provTableImageSize))
849+ lsw = provTableImage[bytePointer - terminatorPtr];
850+ else
851+ lsw = image[bytePointer];
852+
853+ bytePointer += 1;
854+
855+ msw = 0x0000;
856+
857+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE5, msw);
858+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE6, lsw);
859+
860+ /* no polling */
861+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE1, mailboxWrite);
862+ break;
863+
864+ case 0x2:
865+ /* write 2 bytes of data */
866+ if (terminatorPtr && (bytePointer >= terminatorPtr) && (bytePointer < terminatorPtr + provTableImageSize))
867+ lsw = provTableImage[bytePointer - terminatorPtr];
868+ else
869+ lsw = image[bytePointer];
870+
871+ if (terminatorPtr && ((bytePointer+1) >= terminatorPtr) && ((bytePointer+1) < terminatorPtr + provTableImageSize))
872+ lsw |= provTableImage[bytePointer + 1 - terminatorPtr] << 8;
873+ else
874+ lsw |= image[bytePointer+1] << 8;
875+
876+ bytePointer += 2;
877+
878+ msw = 0x0000;
879+
880+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE5, msw);
881+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE6, lsw);
882+
883+ /* no polling */
884+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE1, mailboxWrite);
885+ break;
886+
887+ case 0x3:
888+ /* write 3 bytes of data */
889+ if (terminatorPtr && (bytePointer >= terminatorPtr) && (bytePointer < terminatorPtr + provTableImageSize))
890+ lsw = provTableImage[bytePointer - terminatorPtr];
891+ else
892+ lsw = image[bytePointer];
893+
894+ if (terminatorPtr && ((bytePointer+1) >= terminatorPtr) && ((bytePointer+1) < terminatorPtr + provTableImageSize))
895+ lsw |= provTableImage[bytePointer + 1 - terminatorPtr] << 8;
896+ else
897+ lsw |= image[bytePointer+1] << 8;
898+
899+ bytePointer += 2;
900+
901+ msw = image[bytePointer];
902+ bytePointer += 1;
903+
904+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE5, msw);
905+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE6, lsw);
906+
907+ /* no polling */
908+ phy_write_mmd(gandload_phydev, MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE1, mailboxWrite);
909+ break;
910+ }
911+
912+ if (byteSize & 0x3)
913+ {
914+ /* update the calculated CRC */
915+ crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw >> 8)];
916+ crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (msw & 0xFF)];
917+ crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw >> 8)];
918+ crc16Calculated = ((crc16Calculated & 0xFF) << 8) ^ AQ_CRC16Table[(crc16Calculated >> 8) ^ (lsw & 0xFF)];
919+ }
920+
921+ /*------------------------------------- Exit gangload mode -------------------------------------------------------*/
922+ AQ_API_DisableGangLoadMode(gandload_phydev, recordedGGP1Values[0]);
923+
924+ /*------------------------------------- Check mailbox CRCs -------------------------------------------------------*/
925+ /* check to make sure the mailbox CRC matches the calculated CRC */
926+ for (j = 0; j < num_phydevs; j++) {
927+ mailboxCRC = phy_read_mmd(phydevs[j], MDIO_MMD_VEND1, VEND1_MAILBOX_INTERFACE2);
928+ if (mailboxCRC != crc16Calculated)
929+ {
930+ phydev_err(phydevs[j], "%uth port: Mailbox CRC-16 (0x%X) does not match calculated CRC-16 (0x%X)\n",
931+ j, mailboxCRC, crc16Calculated);
932+ result[j] = -EIO;
933+ }
934+ else
935+ {
936+ phydev_info(phydevs[j], "%uth port: Image load good - mailbox CRC-16 matches (0x%X)\n",
937+ j, mailboxCRC);
938+ }
939+ }
940+
941+ /*------------------------------------- Clear any resets ---------------------------------------------------------*/
942+ for (j = 0; j < num_phydevs; j++) {
943+ phy_write_mmd(phydevs[j], MDIO_MMD_VEND1, VEND1_STD_CONTROL1, 0x0000);
944+ }
945+
946+ /*------------------------------------- Release the uP -----------------------------------------------------------*/
947+ globalControl = 0x0000;
948+ globalControl |= VEND1_CONTROL2_UP_RUNSTALL_OVERRIDE;
949+ globalControl |= VEND1_CONTROL2_UP_RUNSTALL;
950+ for (j = 0; j < num_phydevs; j++) {
951+ globalControl &= ~VEND1_CONTROL2_UP_RESET;
952+ phy_write_mmd(phydevs[j], MDIO_MMD_VEND1, VEND1_CONTROL2, globalControl);
953+ globalControl |= VEND1_CONTROL2_UP_RESET;
954+ phy_write_mmd(phydevs[j], MDIO_MMD_VEND1, VEND1_CONTROL2, globalControl);
955+ }
956+
957+ /* Need to wait at least 100us. */
958+ udelay(100);
959+
960+ globalControl &= ~VEND1_CONTROL2_UP_RESET;
961+ globalControl &= ~VEND1_CONTROL2_UP_RUNSTALL;
962+ /* For post-APPIA devices, always set the uP stall override bit to
963+ * smooth over any packaging differences WRT the boot load pin. */
964+ /* REGDOC: Assign to local representation of bitfield (HHD/APPIA/EUR/CAL/RHEA: 1E.C001.6) */
965+ globalControl |= VEND1_CONTROL2_UP_RUNSTALL_OVERRIDE;
966+
967+ for (j = 0; j < num_phydevs; j++) {
968+ phy_write_mmd(phydevs[j], MDIO_MMD_VEND1, VEND1_CONTROL2, globalControl);
969+ }
970+
971+ /* NOTE!!! We can't re-enable the daisy-chain here, as this will overwrite the IRAM and DRAM with the FLASH contents*/
972+
973+ /* If any of the ports was not bootloaded successfully, return AQ_RET_ERROR */
974+ for (j = 0; j < num_phydevs; j++) {
975+ if (result[j] != 0)
976+ return -EIO;
977+ }
978+
979+ /* All ports were bootloaded successfully. */
980+ return 0;
981+}
982+
983+static int AQ_API_WriteBootLoadImage(
984+ struct phy_device **phydevs,
985+ int num_phydevs,
986+ struct phy_device *gandload_phydev,
987+ int *result,
988+ const uint8_t* data,
989+ size_t size)
990+{
991+ unsigned int val;
992+ int j;
993+
994+ for (j = 0; j < num_phydevs; j++) {
developer3c737eb2022-12-09 09:44:16 +0800995+ /* stall the uP */
996+ val = phy_read_mmd(phydevs[j], MDIO_MMD_VEND1, VEND1_CONTROL2);
997+ val |= VEND1_CONTROL2_UP_RUNSTALL_OVERRIDE;
998+ val |= VEND1_CONTROL2_UP_RUNSTALL;
999+ phy_write_mmd(phydevs[j], MDIO_MMD_VEND1, VEND1_CONTROL2, val);
1000+
developer122ffbb2022-11-14 12:07:10 +08001001+ /* disable the S/W reset to the Global MMD registers */
1002+ val = phy_read_mmd(phydevs[j], MDIO_MMD_VEND1, VEND1_RESET_CONTROL);
1003+ val |= VEND1_RESET_CONTROL_MMD_RESET_DISABLE;
1004+ phy_write_mmd(phydevs[j], MDIO_MMD_VEND1, VEND1_RESET_CONTROL, val);
1005+
developer3c737eb2022-12-09 09:44:16 +08001006+ /* de-assert Global S/W reset */
1007+ val = phy_read_mmd(phydevs[j], MDIO_MMD_VEND1, VEND1_STD_CONTROL1);
1008+ val &= ~VEND1_STD_CONTROL1_SOFT_RESET;
1009+ phy_write_mmd(phydevs[j], MDIO_MMD_VEND1, VEND1_STD_CONTROL1, val);
1010+
developer122ffbb2022-11-14 12:07:10 +08001011+ /* assert Global S/W reset */
1012+ val = phy_read_mmd(phydevs[j], MDIO_MMD_VEND1, VEND1_STD_CONTROL1);
1013+ val |= VEND1_STD_CONTROL1_SOFT_RESET;
1014+ phy_write_mmd(phydevs[j], MDIO_MMD_VEND1, VEND1_STD_CONTROL1, val);
1015+
1016+ /* de-assert Global S/W reset */
1017+ val = phy_read_mmd(phydevs[j], MDIO_MMD_VEND1, VEND1_STD_CONTROL1);
1018+ val &= ~VEND1_STD_CONTROL1_SOFT_RESET;
1019+ phy_write_mmd(phydevs[j], MDIO_MMD_VEND1, VEND1_STD_CONTROL1, val);
1020+
1021+ /* wait 100ms */
1022+ mdelay(100);
1023+
1024+ /* enable the S/W reset to the Global MMD registers */
1025+ val = phy_read_mmd(phydevs[j], MDIO_MMD_VEND1, VEND1_RESET_CONTROL);
1026+ val &= ~VEND1_RESET_CONTROL_MMD_RESET_DISABLE;
1027+ phy_write_mmd(phydevs[j], MDIO_MMD_VEND1, VEND1_RESET_CONTROL, val);
1028+ }
1029+
1030+ return AQ_API_WriteBootLoadImage_impl(phydevs, num_phydevs, gandload_phydev,
1031+ result, (const uint32_t *)&size, data,
1032+ NULL, NULL, 0);
1033+}
1034+
developeraafac652023-01-18 09:41:27 +08001035+static int aqr_firmware_check_heartbeat(struct phy_device *phydev)
1036+{
developer7ddeff02023-03-22 15:28:46 +08001037+ struct aqr107_priv *priv = phydev->priv;
1038+ int stopped = 0, ret;
developeraafac652023-01-18 09:41:27 +08001039+
1040+ ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT2);
1041+ if (ret < 0)
1042+ return ret;
1043+
developer08abacf2023-05-18 15:52:22 +08001044+ /* heartbeat stopped if the current heartbeat is equal to the previous */
developer7ddeff02023-03-22 15:28:46 +08001045+ if (priv->heartbeat == ret)
1046+ stopped = 1;
developeraafac652023-01-18 09:41:27 +08001047+
developer08abacf2023-05-18 15:52:22 +08001048+ /* update heartbeat to the private data */
developer7ddeff02023-03-22 15:28:46 +08001049+ priv->heartbeat = ret;
developeraafac652023-01-18 09:41:27 +08001050+
developer7ddeff02023-03-22 15:28:46 +08001051+ return stopped;
developeraafac652023-01-18 09:41:27 +08001052+}
1053+
developer08abacf2023-05-18 15:52:22 +08001054+int aqr_firmware_heartbeat_thread(void *data)
developeraafac652023-01-18 09:41:27 +08001055+{
1056+ struct phy_device *phydev = data;
1057+ struct aqr107_priv *priv = phydev->priv;
developer7ddeff02023-03-22 15:28:46 +08001058+ struct device *dev;
developeraafac652023-01-18 09:41:27 +08001059+ int ret = 0;
1060+
developer7ddeff02023-03-22 15:28:46 +08001061+ dev = &phydev->mdio.dev;
1062+
developeraafac652023-01-18 09:41:27 +08001063+ for (;;) {
1064+ if (kthread_should_stop())
1065+ break;
1066+
developer08abacf2023-05-18 15:52:22 +08001067+ if (priv->fw_initialized == true &&
developera3617672023-01-31 10:46:41 +08001068+ aqr_firmware_check_heartbeat(phydev) == 1) {
developer7ddeff02023-03-22 15:28:46 +08001069+ dev_err(dev, "Detect heartbeat stopped, start to realod firmware...\n");
developeraafac652023-01-18 09:41:27 +08001070+ priv->fw_initialized = false;
developer08abacf2023-05-18 15:52:22 +08001071+ priv->fw_dl_mode = FW_DL_SINGLE;
developeraafac652023-01-18 09:41:27 +08001072+ aqr_firmware_download_single(phydev);
1073+ }
1074+
1075+ set_current_state(TASK_INTERRUPTIBLE);
developer05838f02023-03-23 15:54:37 +08001076+ schedule_timeout(2 * HZ);
developeraafac652023-01-18 09:41:27 +08001077+ }
1078+
1079+ return ret;
1080+}
1081+
developer122ffbb2022-11-14 12:07:10 +08001082+static void aqr_firmware_download_cb(const struct firmware *fw, void *context)
1083+{
1084+ struct phy_device **phydevs = context;
1085+ struct phy_device *gandload_phydev = phydevs[0];
developer08abacf2023-05-18 15:52:22 +08001086+ struct device *dev = &phydevs[0]->mdio.dev;
developer093e9b32022-12-13 16:08:34 +08001087+ struct aqr107_priv *priv = phydevs[0]->priv;
developer122ffbb2022-11-14 12:07:10 +08001088+ int result[MAX_GANGLOAD_DEVICES];
developer093e9b32022-12-13 16:08:34 +08001089+ int i, num_phydevs = 0, ret = 0;
developer122ffbb2022-11-14 12:07:10 +08001090+
developer94316402022-11-21 08:58:41 +08001091+ if (!fw)
1092+ return;
1093+
developer093e9b32022-12-13 16:08:34 +08001094+ num_phydevs = priv->fw_dl_mode == FW_DL_GNAGLOAD ?
1095+ MAX_GANGLOAD_DEVICES : 1;
developer3c737eb2022-12-09 09:44:16 +08001096+
developer122ffbb2022-11-14 12:07:10 +08001097+retry:
developer7ddeff02023-03-22 15:28:46 +08001098+ if (gandload_phydev->state == PHY_HALTED) {
developer7ddeff02023-03-22 15:28:46 +08001099+ dev_info(dev, "Detect PHY power down, stop to reload firmware...\n");
1100+ goto out;
1101+ }
1102+
developer122ffbb2022-11-14 12:07:10 +08001103+ memset(result, 0, sizeof(result));
1104+
developer093e9b32022-12-13 16:08:34 +08001105+ ret = AQ_API_WriteBootLoadImage(phydevs, num_phydevs, gandload_phydev,
developer122ffbb2022-11-14 12:07:10 +08001106+ result, fw->data, fw->size);
1107+ if (ret) {
developer093e9b32022-12-13 16:08:34 +08001108+ for (i = 0; i < num_phydevs; i++) {
developer94316402022-11-21 08:58:41 +08001109+ if (result[i] == 0)
developer122ffbb2022-11-14 12:07:10 +08001110+ continue;
developer122ffbb2022-11-14 12:07:10 +08001111+
1112+ dev = &phydevs[i]->mdio.dev;
1113+ dev_err(dev, "failed to download firmware %s, ret: %d\n",
1114+ AQR_FIRMWARE, ret);
1115+ goto retry;
1116+ }
1117+ }
1118+
developer55398292022-12-14 19:03:08 +08001119+ /* wait firmware initialization completed */
developer94316402022-11-21 08:58:41 +08001120+ mdelay(250);
developer55398292022-12-14 19:03:08 +08001121+
developer093e9b32022-12-13 16:08:34 +08001122+ for (i = 0; i < num_phydevs; i++) {
developer94316402022-11-21 08:58:41 +08001123+ if (result[i] == 0) {
developer08abacf2023-05-18 15:52:22 +08001124+ dev = &phydevs[i]->mdio.dev;
developer94316402022-11-21 08:58:41 +08001125+ priv = phydevs[i]->priv;
1126+ priv->fw_initialized = true;
developer3c737eb2022-12-09 09:44:16 +08001127+
developer08abacf2023-05-18 15:52:22 +08001128+ aqr107_chip_info(phydevs[i]);
1129+
developer94316402022-11-21 08:58:41 +08001130+ aqr107_config_mdi(phydevs[i]);
developer3c737eb2022-12-09 09:44:16 +08001131+
developer08abacf2023-05-18 15:52:22 +08001132+ aqr107_set_downshift(phydevs[i],
1133+ MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
1134+
1135+ if (phy_is_started(phydevs[i])) {
developer093e9b32022-12-13 16:08:34 +08001136+ phydevs[i]->state = PHY_UP;
1137+ phy_queue_state_machine(phydevs[i], 0);
1138+ }
developer94316402022-11-21 08:58:41 +08001139+ }
1140+ }
developer7ddeff02023-03-22 15:28:46 +08001141+out:
developer122ffbb2022-11-14 12:07:10 +08001142+ release_firmware(fw);
1143+}
1144+
developeraafac652023-01-18 09:41:27 +08001145+static int aqr_firmware_download_single(struct phy_device *phydev)
developer122ffbb2022-11-14 12:07:10 +08001146+{
1147+ struct aqr107_priv *priv = phydev->priv;
1148+ struct device *dev = &phydev->mdio.dev;
developer093e9b32022-12-13 16:08:34 +08001149+ const struct firmware *fw;
developer122ffbb2022-11-14 12:07:10 +08001150+ int ret = 0;
1151+
1152+ if (priv->fw_initialized == true)
1153+ return 0;
1154+
developer08abacf2023-05-18 15:52:22 +08001155+ spin_lock_init(&priv->lock);
developer093e9b32022-12-13 16:08:34 +08001156+ priv->fw_dl_mode = FW_DL_SINGLE;
developer122ffbb2022-11-14 12:07:10 +08001157+ priv->phydevs[0] = phydev;
developer7ddeff02023-03-22 15:28:46 +08001158+ priv->heartbeat = -1;
developer122ffbb2022-11-14 12:07:10 +08001159+
developer093e9b32022-12-13 16:08:34 +08001160+ ret = request_firmware(&fw, AQR_FIRMWARE, dev);
developer122ffbb2022-11-14 12:07:10 +08001161+ if (ret) {
developer08abacf2023-05-18 15:52:22 +08001162+ dev_err(dev, "failed to request firmware %s, ret: %d\n",
developer122ffbb2022-11-14 12:07:10 +08001163+ AQR_FIRMWARE, ret);
1164+ }
1165+
developer093e9b32022-12-13 16:08:34 +08001166+ aqr_firmware_download_cb(fw, priv->phydevs);
1167+
developer122ffbb2022-11-14 12:07:10 +08001168+ return ret;
1169+}
1170+
1171+static int aqr_firmware_gandload_thread(void *data)
1172+{
1173+ struct phy_device **phydevs = data;
1174+ struct device *dev = &phydevs[0]->mdio.dev;
1175+ int ret = 0;
1176+
1177+ for (;;) {
1178+ if (kthread_should_stop())
1179+ break;
1180+
1181+ /* reach maximum gangload phy devices */
1182+ if (gangload == MAX_GANGLOAD_DEVICES) {
1183+ ret = request_firmware_nowait(THIS_MODULE, true, AQR_FIRMWARE, dev,
1184+ GFP_KERNEL, phydevs, aqr_firmware_download_cb);
1185+ if (ret) {
developer08abacf2023-05-18 15:52:22 +08001186+ dev_err(dev, "failed to request firmware %s, ret: %d\n",
developer122ffbb2022-11-14 12:07:10 +08001187+ AQR_FIRMWARE, ret);
1188+ }
1189+ break;
1190+ }
1191+
1192+ set_current_state(TASK_INTERRUPTIBLE);
1193+ msleep(1);
1194+ }
1195+
1196+ return ret;
1197+}
1198+
1199+static int aqr_firmware_download_gang(struct phy_device *phydev)
1200+{
1201+ struct aqr107_priv *priv = phydev->priv;
1202+ struct device *dev = &phydev->mdio.dev;
developer3c737eb2022-12-09 09:44:16 +08001203+ int i;
developer122ffbb2022-11-14 12:07:10 +08001204+
1205+ if (priv->fw_initialized == true)
1206+ return 0;
1207+
1208+ if (!gangload_kthread) {
1209+ /* create a thread for monitor gangload devices */
1210+ gangload_kthread = kthread_create(aqr_firmware_gandload_thread,
1211+ gangload_phydevs,
1212+ "aqr_firmware_gandload_thread");
1213+ if (IS_ERR(gangload_kthread)) {
1214+ dev_err(dev,
developerf3048b62023-06-05 18:00:04 +08001215+ "failed to create aqr_firmware_gandload_thread(%ld)\n",
1216+ PTR_ERR(gangload_kthread));
developer122ffbb2022-11-14 12:07:10 +08001217+ return PTR_ERR(gangload_kthread);
1218+ }
1219+ wake_up_process(gangload_kthread);
1220+ }
1221+
developer3c737eb2022-12-09 09:44:16 +08001222+ for (i = 0; i < gangload; i++) {
1223+ if (gangload_phydevs[i] == phydev) {
developer08abacf2023-05-18 15:52:22 +08001224+ dev_warn(dev, "Detect duplicate gangload phydev\n");
developer3c737eb2022-12-09 09:44:16 +08001225+ return -EINVAL;
1226+ }
1227+ }
1228+
developer08abacf2023-05-18 15:52:22 +08001229+ spin_lock_init(&priv->lock);
developer093e9b32022-12-13 16:08:34 +08001230+ priv->fw_dl_mode = FW_DL_GNAGLOAD;
developer7ddeff02023-03-22 15:28:46 +08001231+ priv->heartbeat = -1;
developer122ffbb2022-11-14 12:07:10 +08001232+ gangload_phydevs[gangload] = phydev;
1233+ gangload++;
1234+
1235+ return 0;
1236+}
1237+
1238+int aqr_firmware_download(struct phy_device *phydev)
1239+{
1240+ int ret = 0;
1241+#ifdef CONFIG_AQUANTIA_PHY_FW_DOWNLOAD_SINGLE
1242+ ret = aqr_firmware_download_single(phydev);
1243+#elif CONFIG_AQUANTIA_PHY_FW_DOWNLOAD_GANG
1244+ ret = aqr_firmware_download_gang(phydev);
1245+#endif
1246+ return ret;
1247+}
1248diff --git a/drivers/net/phy/aquantia_main.c b/drivers/net/phy/aquantia_main.c
developer5d148cb2023-06-02 13:08:11 +08001249index e7495c9a7..36f1aac4f 100644
developer122ffbb2022-11-14 12:07:10 +08001250--- a/drivers/net/phy/aquantia_main.c
1251+++ b/drivers/net/phy/aquantia_main.c
developer301205c2023-05-24 15:39:32 +08001252@@ -8,10 +8,12 @@
developeraafac652023-01-18 09:41:27 +08001253 */
developer08abacf2023-05-18 15:52:22 +08001254
developeraafac652023-01-18 09:41:27 +08001255 #include <linux/kernel.h>
1256+#include <linux/kthread.h>
1257 #include <linux/module.h>
1258 #include <linux/delay.h>
1259 #include <linux/bitfield.h>
developer301205c2023-05-24 15:39:32 +08001260 #include <linux/phy.h>
1261+#include <linux/of.h>
1262
1263 #include "aquantia.h"
1264
developer5d148cb2023-06-02 13:08:11 +08001265@@ -39,7 +41,6 @@
developer08abacf2023-05-18 15:52:22 +08001266 #define MDIO_AN_VEND_PROV_2500BASET_FULL BIT(10)
1267 #define MDIO_AN_VEND_PROV_DOWNSHIFT_EN BIT(4)
1268 #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK GENMASK(3, 0)
1269-#define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT 4
1270
1271 #define MDIO_AN_TX_VEND_STATUS1 0xc800
1272 #define MDIO_AN_TX_VEND_STATUS1_RATE_MASK GENMASK(3, 1)
developer5d148cb2023-06-02 13:08:11 +08001273@@ -73,18 +74,6 @@
developer122ffbb2022-11-14 12:07:10 +08001274 #define MDIO_AN_RX_VEND_STAT3 0xe832
1275 #define MDIO_AN_RX_VEND_STAT3_AFR BIT(0)
1276
1277-/* MDIO_MMD_C22EXT */
1278-#define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES 0xd292
1279-#define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES 0xd294
1280-#define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER 0xd297
1281-#define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES 0xd313
1282-#define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES 0xd315
1283-#define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER 0xd317
1284-#define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS 0xd318
1285-#define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS 0xd319
1286-#define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR 0xd31a
1287-#define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES 0xd31b
1288-
1289 /* Vendor specific 1, MDIO_MMD_VEND1 */
1290 #define VEND1_GLOBAL_FW_ID 0x0020
1291 #define VEND1_GLOBAL_FW_ID_MAJOR GENMASK(15, 8)
developer5d148cb2023-06-02 13:08:11 +08001292@@ -124,31 +113,6 @@
developer122ffbb2022-11-14 12:07:10 +08001293 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2 BIT(1)
1294 #define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 BIT(0)
1295
1296-struct aqr107_hw_stat {
1297- const char *name;
1298- int reg;
1299- int size;
1300-};
1301-
1302-#define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s }
1303-static const struct aqr107_hw_stat aqr107_hw_stats[] = {
1304- SGMII_STAT("sgmii_rx_good_frames", RX_GOOD_FRAMES, 26),
1305- SGMII_STAT("sgmii_rx_bad_frames", RX_BAD_FRAMES, 26),
1306- SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER, 8),
1307- SGMII_STAT("sgmii_tx_good_frames", TX_GOOD_FRAMES, 26),
1308- SGMII_STAT("sgmii_tx_bad_frames", TX_BAD_FRAMES, 26),
1309- SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER, 8),
1310- SGMII_STAT("sgmii_tx_collisions", TX_COLLISIONS, 8),
1311- SGMII_STAT("sgmii_tx_line_collisions", TX_LINE_COLLISIONS, 8),
1312- SGMII_STAT("sgmii_tx_frame_alignment_err", TX_FRAME_ALIGN_ERR, 16),
1313- SGMII_STAT("sgmii_tx_runt_frames", TX_RUNT_FRAMES, 22),
1314-};
1315-#define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats)
1316-
1317-struct aqr107_priv {
1318- u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
1319-};
1320-
1321 static int aqr107_get_sset_count(struct phy_device *phydev)
1322 {
1323 return AQR107_SGMII_STAT_SZ;
developer5d148cb2023-06-02 13:08:11 +08001324@@ -398,7 +362,7 @@ static int aqr107_get_downshift(struct phy_device *phydev, u8 *data)
developer08abacf2023-05-18 15:52:22 +08001325 return 0;
1326 }
1327
1328-static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt)
1329+int aqr107_set_downshift(struct phy_device *phydev, u8 cnt)
1330 {
1331 int val = 0;
1332
developer5d148cb2023-06-02 13:08:11 +08001333@@ -458,7 +422,7 @@ static int aqr107_wait_reset_complete(struct phy_device *phydev)
developer08abacf2023-05-18 15:52:22 +08001334 return val ? 0 : -ETIMEDOUT;
1335 }
1336
1337-static void aqr107_chip_info(struct phy_device *phydev)
1338+void aqr107_chip_info(struct phy_device *phydev)
1339 {
1340 u8 fw_major, fw_minor, build_id, prov_id;
1341 int val;
developer5d148cb2023-06-02 13:08:11 +08001342@@ -481,6 +445,21 @@ static void aqr107_chip_info(struct phy_device *phydev)
developer94316402022-11-21 08:58:41 +08001343 fw_major, fw_minor, build_id, prov_id);
1344 }
1345
1346+int aqr107_config_mdi(struct phy_device *phydev)
1347+{
developer301205c2023-05-24 15:39:32 +08001348+ struct device_node *np = phydev->mdio.dev.of_node;
1349+ u16 val;
1350+
1351+ if (of_property_read_u16(np, "mdi-reversal", &val))
1352+ return -ENOENT;
1353+
1354+ if (!FIELD_FIT(PMAPMD_RSVD_VEND_PROV_MDI_CONF, val))
1355+ return -E2BIG;
1356+
developer94316402022-11-21 08:58:41 +08001357+ return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, PMAPMD_RSVD_VEND_PROV,
developer301205c2023-05-24 15:39:32 +08001358+ PMAPMD_RSVD_VEND_PROV_MDI_CONF, val);
developer94316402022-11-21 08:58:41 +08001359+}
1360+
1361 static int aqr107_config_init(struct phy_device *phydev)
1362 {
1363 int ret;
developer5d148cb2023-06-02 13:08:11 +08001364@@ -499,6 +478,12 @@ static int aqr107_config_init(struct phy_device *phydev)
developer08abacf2023-05-18 15:52:22 +08001365 ret = aqr107_wait_reset_complete(phydev);
developer122ffbb2022-11-14 12:07:10 +08001366 if (!ret)
1367 aqr107_chip_info(phydev);
developer122ffbb2022-11-14 12:07:10 +08001368+#ifdef CONFIG_AQUANTIA_PHY_FW_DOWNLOAD
developer08abacf2023-05-18 15:52:22 +08001369+ else
1370+ return aqr_firmware_download(phydev);
developer122ffbb2022-11-14 12:07:10 +08001371+#endif
1372+
developer08abacf2023-05-18 15:52:22 +08001373+ aqr107_config_mdi(phydev);
developer08abacf2023-05-18 15:52:22 +08001374
developerd7641da2023-02-24 13:56:03 +08001375 return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
1376 }
developerf3048b62023-06-05 18:00:04 +08001377@@ -574,12 +559,41 @@ static void aqr107_link_change_notify(struct phy_device *phydev)
developer122ffbb2022-11-14 12:07:10 +08001378
developer08abacf2023-05-18 15:52:22 +08001379 static int aqr107_suspend(struct phy_device *phydev)
1380 {
developeraafac652023-01-18 09:41:27 +08001381+#ifdef CONFIG_AQUANTIA_PHY_FW_DOWNLOAD
1382+ struct aqr107_priv *priv = phydev->priv;
1383+
developer08abacf2023-05-18 15:52:22 +08001384+ spin_lock(&priv->lock);
1385+ if (priv->heartbeat_thread) {
1386+ kthread_stop(priv->heartbeat_thread);
1387+ priv->heartbeat_thread = NULL;
1388+ priv->heartbeat = -1;
1389+ }
1390+ spin_unlock(&priv->lock);
developeraafac652023-01-18 09:41:27 +08001391+#endif
developer08abacf2023-05-18 15:52:22 +08001392 return phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
1393 MDIO_CTRL1_LPOWER);
1394 }
developeraafac652023-01-18 09:41:27 +08001395
developer08abacf2023-05-18 15:52:22 +08001396 static int aqr107_resume(struct phy_device *phydev)
1397 {
1398+#ifdef CONFIG_AQUANTIA_PHY_FW_DOWNLOAD
1399+ struct aqr107_priv *priv = phydev->priv;
1400+
1401+ spin_lock(&priv->lock);
1402+ if (!priv->heartbeat_thread) {
1403+ priv->heartbeat_thread = kthread_create(aqr_firmware_heartbeat_thread,
1404+ phydev,
1405+ "aqr_firmware_heartbeat_thread");
1406+ if (IS_ERR(priv->heartbeat_thread)) {
1407+ phydev_err(phydev,
developerf3048b62023-06-05 18:00:04 +08001408+ "Failed to create aqr_firmware_heartbeat_thread(%ld)\n",
1409+ PTR_ERR(priv->heartbeat_thread));
1410+ priv->heartbeat_thread = NULL;
1411+ } else
1412+ wake_up_process(priv->heartbeat_thread);
developer08abacf2023-05-18 15:52:22 +08001413+ }
1414+ spin_unlock(&priv->lock);
1415+#endif
1416 return phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
1417 MDIO_CTRL1_LPOWER);
1418 }
developer5d148cb2023-06-02 13:08:11 +08001419--
14202.34.1
1421