developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 1 | From c6b43d63c3d4229b5f15cb7391192494b07e0fa7 Mon Sep 17 00:00:00 2001 |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 2 | From: Bo Jiao <Bo.Jiao@mediatek.com> |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 3 | Date: Mon, 27 Jun 2022 14:53:54 +0800 |
| 4 | Subject: [PATCH 7/8] 9996-add-wed-tx-support-for-mt7986 |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 5 | |
| 6 | --- |
| 7 | arch/arm64/boot/dts/mediatek/mt7986a.dtsi | 2 + |
| 8 | arch/arm64/boot/dts/mediatek/mt7986b.dtsi | 2 + |
developer | 0158738 | 2023-08-24 14:46:09 +0800 | [diff] [blame] | 9 | drivers/net/ethernet/mediatek/mtk_eth_soc.c | 17 +- |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 10 | drivers/net/ethernet/mediatek/mtk_eth_soc.h | 5 + |
developer | 0158738 | 2023-08-24 14:46:09 +0800 | [diff] [blame] | 11 | drivers/net/ethernet/mediatek/mtk_wed.c | 496 +++++++++++++----- |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 12 | drivers/net/ethernet/mediatek/mtk_wed.h | 18 +- |
| 13 | .../net/ethernet/mediatek/mtk_wed_debugfs.c | 3 + |
developer | 0158738 | 2023-08-24 14:46:09 +0800 | [diff] [blame] | 14 | drivers/net/ethernet/mediatek/mtk_wed_regs.h | 130 ++++- |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 15 | include/linux/soc/mediatek/mtk_wed.h | 29 +- |
| 16 | 9 files changed, 546 insertions(+), 150 deletions(-) |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 17 | |
| 18 | diff --git a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 19 | index 381136c21..644255b35 100644 |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 20 | --- a/arch/arm64/boot/dts/mediatek/mt7986a.dtsi |
| 21 | +++ b/arch/arm64/boot/dts/mediatek/mt7986a.dtsi |
| 22 | @@ -64,6 +64,7 @@ |
| 23 | reg = <0 0x15010000 0 0x1000>; |
| 24 | interrupt-parent = <&gic>; |
| 25 | interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; |
| 26 | + mediatek,wed_pcie = <&wed_pcie>; |
| 27 | }; |
| 28 | |
| 29 | wed1: wed@15011000 { |
| 30 | @@ -72,6 +73,7 @@ |
| 31 | reg = <0 0x15011000 0 0x1000>; |
| 32 | interrupt-parent = <&gic>; |
| 33 | interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| 34 | + mediatek,wed_pcie = <&wed_pcie>; |
| 35 | }; |
| 36 | |
| 37 | ap2woccif: ap2woccif@151A5000 { |
| 38 | diff --git a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 39 | index 0e5f116a2..67bf86f6a 100644 |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 40 | --- a/arch/arm64/boot/dts/mediatek/mt7986b.dtsi |
| 41 | +++ b/arch/arm64/boot/dts/mediatek/mt7986b.dtsi |
| 42 | @@ -64,6 +64,7 @@ |
| 43 | reg = <0 0x15010000 0 0x1000>; |
| 44 | interrupt-parent = <&gic>; |
| 45 | interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; |
| 46 | + mediatek,wed_pcie = <&wed_pcie>; |
| 47 | }; |
| 48 | |
| 49 | wed1: wed@15011000 { |
| 50 | @@ -72,6 +73,7 @@ |
| 51 | reg = <0 0x15011000 0 0x1000>; |
| 52 | interrupt-parent = <&gic>; |
| 53 | interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| 54 | + mediatek,wed_pcie = <&wed_pcie>; |
| 55 | }; |
| 56 | |
| 57 | ap2woccif: ap2woccif@151A5000 { |
| 58 | diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 59 | index 3f67bebfe..ac021e2ed 100644 |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 60 | --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c |
| 61 | +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c |
developer | 0158738 | 2023-08-24 14:46:09 +0800 | [diff] [blame] | 62 | @@ -4807,6 +4807,7 @@ static int mtk_probe(struct platform_device *pdev) |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 63 | { |
| 64 | struct device_node *mac_np; |
| 65 | struct mtk_eth *eth; |
developer | f50c180 | 2022-07-05 20:35:53 +0800 | [diff] [blame] | 66 | + struct resource *res = NULL; |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 67 | int err, i; |
| 68 | |
| 69 | eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL); |
developer | 0158738 | 2023-08-24 14:46:09 +0800 | [diff] [blame] | 70 | @@ -4827,13 +4828,12 @@ static int mtk_probe(struct platform_device *pdev) |
| 71 | return PTR_ERR(eth->sram_base); |
| 72 | } |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 73 | |
developer | 0158738 | 2023-08-24 14:46:09 +0800 | [diff] [blame] | 74 | - if(eth->soc->has_sram) { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 75 | - struct resource *res; |
developer | 0158738 | 2023-08-24 14:46:09 +0800 | [diff] [blame] | 76 | - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 77 | - if (unlikely(!res)) |
| 78 | - return -EINVAL; |
| 79 | + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 80 | + if (unlikely(!res)) |
| 81 | + return -EINVAL; |
| 82 | + |
| 83 | + if(eth->soc->has_sram) |
| 84 | eth->phy_scratch_ring = res->start + MTK_ETH_SRAM_OFFSET; |
| 85 | - } |
| 86 | |
| 87 | mtk_get_hwver(eth); |
| 88 | |
| 89 | @@ -4929,12 +4929,15 @@ static int mtk_probe(struct platform_device *pdev) |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 90 | MTK_WDMA1_BASE |
| 91 | }; |
| 92 | void __iomem *wdma; |
| 93 | + u32 wdma_phy; |
| 94 | |
| 95 | if (!np || i >= ARRAY_SIZE(wdma_regs)) |
| 96 | break; |
| 97 | |
| 98 | wdma = eth->base + wdma_regs[i]; |
| 99 | - mtk_wed_add_hw(np, eth, wdma, i); |
developer | 0158738 | 2023-08-24 14:46:09 +0800 | [diff] [blame] | 100 | + wdma_phy = res->start + wdma_regs[i]; |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 101 | + |
| 102 | + mtk_wed_add_hw(np, eth, wdma, wdma_phy, i); |
| 103 | } |
| 104 | |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 105 | for (i = 0; i < MTK_MAX_IRQ_NUM; i++) { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 106 | diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 107 | index b4de7c0c6..4a69bd0cf 100644 |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 108 | --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h |
| 109 | +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 110 | @@ -518,8 +518,13 @@ |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 111 | #define RX_DMA_SPORT_MASK 0x7 |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 112 | #endif |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 113 | |
| 114 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 115 | +#define MTK_WDMA0_BASE 0x4800 |
| 116 | +#define MTK_WDMA1_BASE 0x4c00 |
| 117 | +#else |
| 118 | #define MTK_WDMA0_BASE 0x2800 |
| 119 | #define MTK_WDMA1_BASE 0x2c00 |
| 120 | +#endif |
| 121 | |
| 122 | /* QDMA descriptor txd4 */ |
| 123 | #define TX_DMA_CHKSUM (0x7 << 29) |
| 124 | diff --git a/drivers/net/ethernet/mediatek/mtk_wed.c b/drivers/net/ethernet/mediatek/mtk_wed.c |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 125 | index ea1cbdf1a..48b0353bb 100644 |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 126 | --- a/drivers/net/ethernet/mediatek/mtk_wed.c |
| 127 | +++ b/drivers/net/ethernet/mediatek/mtk_wed.c |
| 128 | @@ -18,15 +18,6 @@ |
| 129 | #include "mtk_wed.h" |
| 130 | #include "mtk_ppe.h" |
| 131 | |
| 132 | -#define MTK_PCIE_BASE(n) (0x1a143000 + (n) * 0x2000) |
| 133 | - |
| 134 | -#define MTK_WED_PKT_SIZE 1900 |
| 135 | -#define MTK_WED_BUF_SIZE 2048 |
| 136 | -#define MTK_WED_BUF_PER_PAGE (PAGE_SIZE / 2048) |
| 137 | - |
| 138 | -#define MTK_WED_TX_RING_SIZE 2048 |
| 139 | -#define MTK_WED_WDMA_RING_SIZE 1024 |
| 140 | - |
| 141 | static struct mtk_wed_hw *hw_list[2]; |
| 142 | static DEFINE_MUTEX(hw_lock); |
| 143 | |
| 144 | @@ -80,14 +71,19 @@ mtk_wed_reset(struct mtk_wed_device *dev, u32 mask) |
| 145 | static struct mtk_wed_hw * |
| 146 | mtk_wed_assign(struct mtk_wed_device *dev) |
| 147 | { |
| 148 | - struct mtk_wed_hw *hw; |
| 149 | + int i; |
| 150 | + |
| 151 | + for (i = 0; i < ARRAY_SIZE(hw_list); i++) { |
| 152 | + struct mtk_wed_hw *hw = hw_list[i]; |
| 153 | + |
| 154 | + if (!hw || hw->wed_dev) |
| 155 | + continue; |
| 156 | |
| 157 | - hw = hw_list[pci_domain_nr(dev->wlan.pci_dev->bus)]; |
| 158 | - if (!hw || hw->wed_dev) |
| 159 | - return NULL; |
| 160 | + hw->wed_dev = dev; |
| 161 | + return hw; |
| 162 | + } |
| 163 | |
| 164 | - hw->wed_dev = dev; |
| 165 | - return hw; |
| 166 | + return NULL; |
| 167 | } |
| 168 | |
| 169 | static int |
| 170 | @@ -96,19 +92,27 @@ mtk_wed_buffer_alloc(struct mtk_wed_device *dev) |
| 171 | struct mtk_wdma_desc *desc; |
| 172 | dma_addr_t desc_phys; |
| 173 | void **page_list; |
| 174 | + u32 last_seg = MTK_WDMA_DESC_CTRL_LAST_SEG1; |
| 175 | int token = dev->wlan.token_start; |
| 176 | - int ring_size; |
| 177 | - int n_pages; |
| 178 | - int i, page_idx; |
| 179 | + int ring_size, n_pages, page_idx; |
| 180 | + int i; |
| 181 | + |
| 182 | + |
| 183 | + if (dev->ver == MTK_WED_V1) { |
| 184 | + ring_size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1); |
| 185 | + } else { |
| 186 | + ring_size = MTK_WED_VLD_GROUP_SIZE * MTK_WED_PER_GROUP_PKT + |
| 187 | + MTK_WED_WDMA_RING_SIZE * 2; |
| 188 | + last_seg = MTK_WDMA_DESC_CTRL_LAST_SEG0; |
| 189 | + } |
| 190 | |
| 191 | - ring_size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1); |
| 192 | n_pages = ring_size / MTK_WED_BUF_PER_PAGE; |
| 193 | |
| 194 | page_list = kcalloc(n_pages, sizeof(*page_list), GFP_KERNEL); |
| 195 | if (!page_list) |
| 196 | return -ENOMEM; |
| 197 | |
| 198 | - dev->buf_ring.size = ring_size; |
| 199 | + dev->buf_ring.size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1); |
| 200 | dev->buf_ring.pages = page_list; |
| 201 | |
| 202 | desc = dma_alloc_coherent(dev->hw->dev, ring_size * sizeof(*desc), |
| 203 | @@ -154,7 +158,7 @@ mtk_wed_buffer_alloc(struct mtk_wed_device *dev) |
| 204 | txd_size) | |
| 205 | FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1, |
| 206 | MTK_WED_BUF_SIZE - txd_size) | |
| 207 | - MTK_WDMA_DESC_CTRL_LAST_SEG1; |
| 208 | + last_seg; |
| 209 | desc->info = 0; |
| 210 | desc++; |
| 211 | |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 212 | @@ -202,12 +206,12 @@ free_pagelist: |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 213 | } |
| 214 | |
| 215 | static void |
| 216 | -mtk_wed_free_ring(struct mtk_wed_device *dev, struct mtk_wed_ring *ring) |
| 217 | +mtk_wed_free_ring(struct mtk_wed_device *dev, struct mtk_wed_ring *ring, int scale) |
| 218 | { |
| 219 | if (!ring->desc) |
| 220 | return; |
| 221 | |
| 222 | - dma_free_coherent(dev->hw->dev, ring->size * sizeof(*ring->desc), |
| 223 | + dma_free_coherent(dev->hw->dev, ring->size * sizeof(*ring->desc) * scale, |
| 224 | ring->desc, ring->desc_phys); |
| 225 | } |
| 226 | |
| 227 | @@ -217,9 +221,69 @@ mtk_wed_free_tx_rings(struct mtk_wed_device *dev) |
| 228 | int i; |
| 229 | |
| 230 | for (i = 0; i < ARRAY_SIZE(dev->tx_ring); i++) |
| 231 | - mtk_wed_free_ring(dev, &dev->tx_ring[i]); |
| 232 | + mtk_wed_free_ring(dev, &dev->tx_ring[i], 1); |
| 233 | for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++) |
| 234 | - mtk_wed_free_ring(dev, &dev->tx_wdma[i]); |
| 235 | + mtk_wed_free_ring(dev, &dev->tx_wdma[i], dev->ver); |
| 236 | +} |
| 237 | + |
| 238 | +static void |
| 239 | +mtk_wed_set_int(struct mtk_wed_device *dev, u32 irq_mask) |
| 240 | +{ |
| 241 | + u32 wdma_mask; |
| 242 | + |
| 243 | + wdma_mask = FIELD_PREP(MTK_WDMA_INT_MASK_RX_DONE, GENMASK(1, 0)); |
| 244 | + |
| 245 | + /* wed control cr set */ |
| 246 | + wed_set(dev, MTK_WED_CTRL, |
| 247 | + MTK_WED_CTRL_WDMA_INT_AGENT_EN | |
| 248 | + MTK_WED_CTRL_WPDMA_INT_AGENT_EN | |
| 249 | + MTK_WED_CTRL_WED_TX_BM_EN | |
| 250 | + MTK_WED_CTRL_WED_TX_FREE_AGENT_EN); |
| 251 | + |
| 252 | + if (dev->ver == MTK_WED_V1) { |
| 253 | + wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, |
| 254 | + MTK_WED_PCIE_INT_TRIGGER_STATUS); |
| 255 | + |
| 256 | + wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, |
| 257 | + MTK_WED_WPDMA_INT_TRIGGER_RX_DONE | |
| 258 | + MTK_WED_WPDMA_INT_TRIGGER_TX_DONE); |
| 259 | + |
| 260 | + wed_set(dev, MTK_WED_WPDMA_INT_CTRL, |
| 261 | + MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV); |
| 262 | + } else { |
| 263 | + /* initail tx interrupt trigger */ |
| 264 | + wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX, |
| 265 | + MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN | |
| 266 | + MTK_WED_WPDMA_INT_CTRL_TX0_DONE_CLR | |
| 267 | + MTK_WED_WPDMA_INT_CTRL_TX1_DONE_EN | |
| 268 | + MTK_WED_WPDMA_INT_CTRL_TX1_DONE_CLR | |
| 269 | + FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX0_DONE_TRIG, |
| 270 | + dev->wlan.tx_tbit[0]) | |
| 271 | + FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX1_DONE_TRIG, |
| 272 | + dev->wlan.tx_tbit[1])); |
| 273 | + |
| 274 | + /* initail txfree interrupt trigger */ |
| 275 | + wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX_FREE, |
| 276 | + MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_EN | |
| 277 | + MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_CLR | |
| 278 | + FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG, |
| 279 | + dev->wlan.txfree_tbit)); |
| 280 | + } |
| 281 | + /* initail wdma interrupt agent */ |
| 282 | + wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, wdma_mask); |
| 283 | + if (dev->ver == MTK_WED_V1) { |
| 284 | + wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask); |
| 285 | + } else { |
| 286 | + wed_w32(dev, MTK_WED_WDMA_INT_CLR, wdma_mask); |
| 287 | + wed_set(dev, MTK_WED_WDMA_INT_CTRL, |
| 288 | + FIELD_PREP(MTK_WED_WDMA_INT_POLL_SRC_SEL,dev->wdma_idx)); |
| 289 | + |
| 290 | + } |
| 291 | + |
| 292 | + wdma_w32(dev, MTK_WDMA_INT_MASK, wdma_mask); |
| 293 | + wdma_w32(dev, MTK_WDMA_INT_GRP2, wdma_mask); |
| 294 | + wed_w32(dev, MTK_WED_WPDMA_INT_MASK, irq_mask); |
| 295 | + wed_w32(dev, MTK_WED_INT_MASK, irq_mask); |
| 296 | } |
| 297 | |
| 298 | static void |
| 299 | @@ -234,10 +298,95 @@ mtk_wed_set_ext_int(struct mtk_wed_device *dev, bool en) |
| 300 | wed_r32(dev, MTK_WED_EXT_INT_MASK); |
| 301 | } |
| 302 | |
| 303 | +static void |
| 304 | +mtk_wed_set_512_support(struct mtk_wed_device *dev, bool en) |
| 305 | +{ |
| 306 | + if (en) { |
| 307 | + wed_w32(dev, MTK_WED_TXDP_CTRL, MTK_WED_TXDP_DW9_OVERWR); |
| 308 | + wed_w32(dev, MTK_WED_TXP_DW1, |
| 309 | + FIELD_PREP(MTK_WED_WPDMA_WRITE_TXP, 0x0103)); |
| 310 | + } else { |
| 311 | + wed_w32(dev, MTK_WED_TXP_DW1, |
| 312 | + FIELD_PREP(MTK_WED_WPDMA_WRITE_TXP, 0x0100)); |
| 313 | + wed_clr(dev, MTK_WED_TXDP_CTRL, MTK_WED_TXDP_DW9_OVERWR); |
| 314 | + } |
| 315 | +} |
| 316 | + |
| 317 | +static void |
| 318 | +mtk_wed_dma_enable(struct mtk_wed_device *dev) |
| 319 | +{ |
| 320 | + wed_set(dev, MTK_WED_WPDMA_INT_CTRL, |
| 321 | + MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV); |
| 322 | + |
| 323 | + wed_set(dev, MTK_WED_GLO_CFG, |
| 324 | + MTK_WED_GLO_CFG_TX_DMA_EN | |
| 325 | + MTK_WED_GLO_CFG_RX_DMA_EN); |
| 326 | + wed_set(dev, MTK_WED_WPDMA_GLO_CFG, |
| 327 | + MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN | |
| 328 | + MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN); |
| 329 | + wed_set(dev, MTK_WED_WDMA_GLO_CFG, |
| 330 | + MTK_WED_WDMA_GLO_CFG_RX_DRV_EN); |
| 331 | + |
| 332 | + wdma_set(dev, MTK_WDMA_GLO_CFG, |
| 333 | + MTK_WDMA_GLO_CFG_TX_DMA_EN | |
| 334 | + MTK_WDMA_GLO_CFG_RX_INFO1_PRERES | |
| 335 | + MTK_WDMA_GLO_CFG_RX_INFO2_PRERES); |
| 336 | + |
| 337 | + if (dev->ver == MTK_WED_V1) { |
| 338 | + wdma_set(dev, MTK_WDMA_GLO_CFG, |
| 339 | + MTK_WDMA_GLO_CFG_RX_INFO3_PRERES); |
| 340 | + } else { |
| 341 | + wed_set(dev, MTK_WED_WPDMA_CTRL, |
| 342 | + MTK_WED_WPDMA_CTRL_SDL1_FIXED); |
| 343 | + |
| 344 | + wed_set(dev, MTK_WED_WPDMA_GLO_CFG, |
| 345 | + MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC | |
| 346 | + MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC); |
| 347 | + |
| 348 | + wed_clr(dev, MTK_WED_WPDMA_GLO_CFG, |
| 349 | + MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP | |
| 350 | + MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV); |
| 351 | + } |
| 352 | +} |
| 353 | + |
| 354 | +static void |
| 355 | +mtk_wed_dma_disable(struct mtk_wed_device *dev) |
| 356 | +{ |
| 357 | + wed_clr(dev, MTK_WED_WPDMA_GLO_CFG, |
| 358 | + MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN | |
| 359 | + MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN); |
| 360 | + |
| 361 | + wed_clr(dev, MTK_WED_WDMA_GLO_CFG, |
| 362 | + MTK_WED_WDMA_GLO_CFG_RX_DRV_EN); |
| 363 | + |
| 364 | + wed_clr(dev, MTK_WED_GLO_CFG, |
| 365 | + MTK_WED_GLO_CFG_TX_DMA_EN | |
| 366 | + MTK_WED_GLO_CFG_RX_DMA_EN); |
| 367 | + |
| 368 | + wdma_m32(dev, MTK_WDMA_GLO_CFG, |
| 369 | + MTK_WDMA_GLO_CFG_TX_DMA_EN | |
| 370 | + MTK_WDMA_GLO_CFG_RX_INFO1_PRERES | |
| 371 | + MTK_WDMA_GLO_CFG_RX_INFO2_PRERES, 0); |
| 372 | + |
| 373 | + if (dev->ver == MTK_WED_V1) { |
| 374 | + regmap_write(dev->hw->mirror, dev->hw->index * 4, 0); |
| 375 | + wdma_m32(dev, MTK_WDMA_GLO_CFG, |
| 376 | + MTK_WDMA_GLO_CFG_RX_INFO3_PRERES, 0); |
| 377 | + } else { |
| 378 | + wed_clr(dev, MTK_WED_WPDMA_GLO_CFG, |
| 379 | + MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC | |
| 380 | + MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC); |
| 381 | + } |
| 382 | +} |
| 383 | + |
| 384 | static void |
| 385 | mtk_wed_stop(struct mtk_wed_device *dev) |
| 386 | { |
| 387 | - regmap_write(dev->hw->mirror, dev->hw->index * 4, 0); |
| 388 | + mtk_wed_dma_disable(dev); |
| 389 | + |
| 390 | + if (dev->ver > MTK_WED_V1) |
| 391 | + mtk_wed_set_512_support(dev, false); |
| 392 | + |
| 393 | mtk_wed_set_ext_int(dev, false); |
| 394 | |
| 395 | wed_clr(dev, MTK_WED_CTRL, |
| 396 | @@ -245,26 +394,18 @@ mtk_wed_stop(struct mtk_wed_device *dev) |
| 397 | MTK_WED_CTRL_WPDMA_INT_AGENT_EN | |
| 398 | MTK_WED_CTRL_WED_TX_BM_EN | |
| 399 | MTK_WED_CTRL_WED_TX_FREE_AGENT_EN); |
| 400 | + |
| 401 | wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, 0); |
| 402 | wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, 0); |
| 403 | wdma_w32(dev, MTK_WDMA_INT_MASK, 0); |
| 404 | wdma_w32(dev, MTK_WDMA_INT_GRP2, 0); |
| 405 | wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0); |
| 406 | - |
| 407 | - wed_clr(dev, MTK_WED_GLO_CFG, |
| 408 | - MTK_WED_GLO_CFG_TX_DMA_EN | |
| 409 | - MTK_WED_GLO_CFG_RX_DMA_EN); |
| 410 | - wed_clr(dev, MTK_WED_WPDMA_GLO_CFG, |
| 411 | - MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN | |
| 412 | - MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN); |
| 413 | - wed_clr(dev, MTK_WED_WDMA_GLO_CFG, |
| 414 | - MTK_WED_WDMA_GLO_CFG_RX_DRV_EN); |
| 415 | } |
| 416 | |
| 417 | static void |
| 418 | mtk_wed_detach(struct mtk_wed_device *dev) |
| 419 | { |
| 420 | - struct device_node *wlan_node = dev->wlan.pci_dev->dev.of_node; |
| 421 | + struct device_node *wlan_node; |
| 422 | struct mtk_wed_hw *hw = dev->hw; |
| 423 | |
| 424 | mutex_lock(&hw_lock); |
| 425 | @@ -279,9 +420,12 @@ mtk_wed_detach(struct mtk_wed_device *dev) |
| 426 | mtk_wed_free_buffer(dev); |
| 427 | mtk_wed_free_tx_rings(dev); |
| 428 | |
| 429 | - if (of_dma_is_coherent(wlan_node)) |
| 430 | - regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP, |
| 431 | - BIT(hw->index), BIT(hw->index)); |
| 432 | + if (dev->wlan.bus_type == MTK_BUS_TYPE_PCIE) { |
| 433 | + wlan_node = dev->wlan.pci_dev->dev.of_node; |
| 434 | + if (of_dma_is_coherent(wlan_node)) |
| 435 | + regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP, |
| 436 | + BIT(hw->index), BIT(hw->index)); |
| 437 | + } |
| 438 | |
| 439 | if (!hw_list[!hw->index]->wed_dev && |
| 440 | hw->eth->dma_dev != hw->eth->dev) |
| 441 | @@ -294,15 +438,87 @@ mtk_wed_detach(struct mtk_wed_device *dev) |
| 442 | mutex_unlock(&hw_lock); |
| 443 | } |
| 444 | |
| 445 | +static void |
| 446 | +mtk_wed_bus_init(struct mtk_wed_device *dev) |
| 447 | +{ |
| 448 | +#define PCIE_BASE_ADDR0 0x11280000 |
| 449 | + |
| 450 | + if (dev->wlan.bus_type == MTK_BUS_TYPE_PCIE) { |
| 451 | + struct device_node *node; |
| 452 | + void __iomem * base_addr; |
| 453 | + u32 value = 0; |
| 454 | + |
| 455 | + node = of_parse_phandle(dev->hw->node, "mediatek,wed_pcie", 0); |
| 456 | + if (!node) { |
| 457 | + pr_err("%s: no wed_pcie node\n", __func__); |
| 458 | + return; |
| 459 | + } |
| 460 | + |
| 461 | + base_addr = of_iomap(node, 0); |
| 462 | + |
| 463 | + value = readl(base_addr); |
| 464 | + value |= BIT(0); |
| 465 | + writel(value, base_addr); |
| 466 | + |
| 467 | + wed_w32(dev, MTK_WED_PCIE_INT_CTRL, |
| 468 | + FIELD_PREP(MTK_WED_PCIE_INT_CTRL_POLL_EN, 2)); |
| 469 | + |
| 470 | + /* pcie interrupt control: pola/source selection */ |
| 471 | + wed_set(dev, MTK_WED_PCIE_INT_CTRL, |
| 472 | + MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA | |
| 473 | + FIELD_PREP(MTK_WED_PCIE_INT_CTRL_SRC_SEL, 1)); |
| 474 | + wed_r32(dev, MTK_WED_PCIE_INT_CTRL); |
| 475 | + |
| 476 | + value = wed_r32(dev, MTK_WED_PCIE_CFG_INTM); |
| 477 | + value = wed_r32(dev, MTK_WED_PCIE_CFG_BASE); |
| 478 | + wed_w32(dev, MTK_WED_PCIE_CFG_INTM, PCIE_BASE_ADDR0 | 0x180); |
| 479 | + wed_w32(dev, MTK_WED_PCIE_CFG_BASE, PCIE_BASE_ADDR0 | 0x184); |
| 480 | + |
| 481 | + value = wed_r32(dev, MTK_WED_PCIE_CFG_INTM); |
| 482 | + value = wed_r32(dev, MTK_WED_PCIE_CFG_BASE); |
| 483 | + |
| 484 | + /* pcie interrupt status trigger register */ |
| 485 | + wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(24)); |
| 486 | + wed_r32(dev, MTK_WED_PCIE_INT_TRIGGER); |
| 487 | + |
| 488 | + /* pola setting */ |
| 489 | + value = wed_r32(dev, MTK_WED_PCIE_INT_CTRL); |
| 490 | + wed_set(dev, MTK_WED_PCIE_INT_CTRL, |
| 491 | + MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA); |
| 492 | + } else if (dev->wlan.bus_type == MTK_BUS_TYPE_AXI) { |
| 493 | + wed_set(dev, MTK_WED_WPDMA_INT_CTRL, |
| 494 | + MTK_WED_WPDMA_INT_CTRL_SIG_SRC | |
| 495 | + FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_SRC_SEL, 0)); |
| 496 | + } |
| 497 | + return; |
| 498 | +} |
| 499 | + |
| 500 | +static void |
| 501 | +mtk_wed_set_wpdma(struct mtk_wed_device *dev) |
| 502 | +{ |
| 503 | + if (dev->ver > MTK_WED_V1) { |
| 504 | + wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_int); |
| 505 | + wed_w32(dev, MTK_WED_WPDMA_CFG_INT_MASK, dev->wlan.wpdma_mask); |
| 506 | + wed_w32(dev, MTK_WED_WPDMA_CFG_TX, dev->wlan.wpdma_tx); |
| 507 | + wed_w32(dev, MTK_WED_WPDMA_CFG_TX_FREE, dev->wlan.wpdma_txfree); |
| 508 | + } else { |
| 509 | + wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys); |
| 510 | + } |
| 511 | +} |
| 512 | + |
| 513 | static void |
| 514 | mtk_wed_hw_init_early(struct mtk_wed_device *dev) |
| 515 | { |
| 516 | u32 mask, set; |
| 517 | - u32 offset; |
| 518 | |
| 519 | mtk_wed_stop(dev); |
| 520 | mtk_wed_reset(dev, MTK_WED_RESET_WED); |
| 521 | |
| 522 | + if (dev->ver > MTK_WED_V1) |
| 523 | + mtk_wed_bus_init(dev); |
| 524 | + |
| 525 | + mtk_wed_set_wpdma(dev); |
| 526 | + |
| 527 | mask = MTK_WED_WDMA_GLO_CFG_BT_SIZE | |
| 528 | MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE | |
| 529 | MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE; |
| 530 | @@ -311,30 +527,54 @@ mtk_wed_hw_init_early(struct mtk_wed_device *dev) |
| 531 | MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY; |
| 532 | wed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set); |
| 533 | |
| 534 | - wdma_set(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_RX_INFO_PRERES); |
| 535 | + if (dev->ver == MTK_WED_V1) { |
| 536 | + u32 offset; |
| 537 | + offset = dev->hw->index ? 0x04000400 : 0; |
| 538 | + wed_w32(dev, MTK_WED_WDMA_OFFSET0, 0x2a042a20 + offset); |
| 539 | + wed_w32(dev, MTK_WED_WDMA_OFFSET1, 0x29002800 + offset); |
| 540 | |
| 541 | - offset = dev->hw->index ? 0x04000400 : 0; |
| 542 | - wed_w32(dev, MTK_WED_WDMA_OFFSET0, 0x2a042a20 + offset); |
| 543 | - wed_w32(dev, MTK_WED_WDMA_OFFSET1, 0x29002800 + offset); |
| 544 | + wed_w32(dev, MTK_WED_PCIE_CFG_BASE, MTK_PCIE_BASE(dev->hw->index)); |
| 545 | + } else { |
| 546 | + wed_w32(dev, MTK_WED_WDMA_CFG_BASE, dev->hw->wdma_phy); |
| 547 | + wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_ETH_DMAD_FMT); |
| 548 | + wed_w32(dev, MTK_WED_WDMA_OFFSET0, |
| 549 | + FIELD_PREP(MTK_WED_WDMA_OFST0_GLO_INTS, |
| 550 | + MTK_WDMA_INT_STATUS) | |
| 551 | + FIELD_PREP(MTK_WED_WDMA_OFST0_GLO_CFG, |
| 552 | + MTK_WDMA_GLO_CFG)); |
| 553 | + |
| 554 | + wed_w32(dev, MTK_WED_WDMA_OFFSET1, |
| 555 | + FIELD_PREP(MTK_WED_WDMA_OFST1_TX_CTRL, |
| 556 | + MTK_WDMA_RING_TX(0)) | |
| 557 | + FIELD_PREP(MTK_WED_WDMA_OFST1_RX_CTRL, |
| 558 | + MTK_WDMA_RING_RX(0))); |
| 559 | + } |
| 560 | |
| 561 | - wed_w32(dev, MTK_WED_PCIE_CFG_BASE, MTK_PCIE_BASE(dev->hw->index)); |
| 562 | - wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_phys); |
| 563 | } |
| 564 | |
| 565 | static void |
| 566 | mtk_wed_hw_init(struct mtk_wed_device *dev) |
| 567 | { |
| 568 | + int size = dev->buf_ring.size; |
| 569 | + int rev_size = MTK_WED_TX_RING_SIZE / 2; |
| 570 | + int thr = 1; |
| 571 | + |
| 572 | if (dev->init_done) |
| 573 | return; |
| 574 | |
| 575 | dev->init_done = true; |
| 576 | mtk_wed_set_ext_int(dev, false); |
| 577 | + |
| 578 | + if (dev->ver > MTK_WED_V1) { |
| 579 | + size = MTK_WED_WDMA_RING_SIZE * 2 + dev->buf_ring.size; |
| 580 | + rev_size = size; |
| 581 | + thr = 0; |
| 582 | + } |
| 583 | + |
| 584 | wed_w32(dev, MTK_WED_TX_BM_CTRL, |
| 585 | MTK_WED_TX_BM_CTRL_PAUSE | |
| 586 | - FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM, |
| 587 | - dev->buf_ring.size / 128) | |
| 588 | - FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM, |
| 589 | - MTK_WED_TX_RING_SIZE / 256)); |
| 590 | + FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM, size / 128) | |
| 591 | + FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM, rev_size / 128)); |
| 592 | |
| 593 | wed_w32(dev, MTK_WED_TX_BM_BASE, dev->buf_ring.desc_phys); |
| 594 | |
| 595 | @@ -347,28 +587,38 @@ mtk_wed_hw_init(struct mtk_wed_device *dev) |
| 596 | wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE); |
| 597 | |
| 598 | wed_w32(dev, MTK_WED_TX_BM_DYN_THR, |
| 599 | - FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO, 1) | |
| 600 | + FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO, thr) | |
| 601 | MTK_WED_TX_BM_DYN_THR_HI); |
| 602 | |
| 603 | + if (dev->ver > MTK_WED_V1) { |
| 604 | + wed_w32(dev, MTK_WED_TX_TKID_CTRL, |
| 605 | + MTK_WED_TX_TKID_CTRL_PAUSE | |
| 606 | + FIELD_PREP(MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM, |
| 607 | + dev->buf_ring.size / 128) | |
| 608 | + FIELD_PREP(MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM, |
| 609 | + dev->buf_ring.size / 128)); |
| 610 | + wed_w32(dev, MTK_WED_TX_TKID_DYN_THR, |
| 611 | + FIELD_PREP(MTK_WED_TX_TKID_DYN_THR_LO, 0) | |
| 612 | + MTK_WED_TX_TKID_DYN_THR_HI); |
| 613 | + } |
| 614 | mtk_wed_reset(dev, MTK_WED_RESET_TX_BM); |
| 615 | |
| 616 | - wed_set(dev, MTK_WED_CTRL, |
| 617 | - MTK_WED_CTRL_WED_TX_BM_EN | |
| 618 | - MTK_WED_CTRL_WED_TX_FREE_AGENT_EN); |
| 619 | - |
| 620 | wed_clr(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_PAUSE); |
| 621 | + if (dev->ver > MTK_WED_V1) |
| 622 | + wed_clr(dev, MTK_WED_TX_TKID_CTRL, MTK_WED_TX_TKID_CTRL_PAUSE); |
| 623 | } |
| 624 | |
| 625 | static void |
| 626 | -mtk_wed_ring_reset(struct mtk_wdma_desc *desc, int size) |
| 627 | +mtk_wed_ring_reset(struct mtk_wdma_desc *desc, int size, int scale) |
| 628 | { |
| 629 | int i; |
| 630 | |
| 631 | for (i = 0; i < size; i++) { |
| 632 | - desc[i].buf0 = 0; |
| 633 | - desc[i].ctrl = cpu_to_le32(MTK_WDMA_DESC_CTRL_DMA_DONE); |
| 634 | - desc[i].buf1 = 0; |
| 635 | - desc[i].info = 0; |
| 636 | + desc->buf0 = 0; |
| 637 | + desc->ctrl = cpu_to_le32(MTK_WDMA_DESC_CTRL_DMA_DONE); |
| 638 | + desc->buf1 = 0; |
| 639 | + desc->info = 0; |
| 640 | + desc += scale; |
| 641 | } |
| 642 | } |
| 643 | |
| 644 | @@ -424,7 +674,7 @@ mtk_wed_reset_dma(struct mtk_wed_device *dev) |
| 645 | if (!desc) |
| 646 | continue; |
| 647 | |
| 648 | - mtk_wed_ring_reset(desc, MTK_WED_TX_RING_SIZE); |
| 649 | + mtk_wed_ring_reset(desc, MTK_WED_TX_RING_SIZE, dev->ver); |
| 650 | } |
| 651 | |
| 652 | if (mtk_wed_poll_busy(dev)) |
| 653 | @@ -481,16 +731,16 @@ mtk_wed_reset_dma(struct mtk_wed_device *dev) |
| 654 | |
| 655 | static int |
| 656 | mtk_wed_ring_alloc(struct mtk_wed_device *dev, struct mtk_wed_ring *ring, |
| 657 | - int size) |
| 658 | + int size, int scale) |
| 659 | { |
| 660 | ring->desc = dma_alloc_coherent(dev->hw->dev, |
| 661 | - size * sizeof(*ring->desc), |
| 662 | + size * sizeof(*ring->desc) * scale, |
| 663 | &ring->desc_phys, GFP_KERNEL); |
| 664 | if (!ring->desc) |
| 665 | return -ENOMEM; |
| 666 | |
| 667 | ring->size = size; |
| 668 | - mtk_wed_ring_reset(ring->desc, size); |
| 669 | + mtk_wed_ring_reset(ring->desc, size, scale); |
| 670 | |
| 671 | return 0; |
| 672 | } |
| 673 | @@ -500,7 +750,7 @@ mtk_wed_wdma_ring_setup(struct mtk_wed_device *dev, int idx, int size) |
| 674 | { |
| 675 | struct mtk_wed_ring *wdma = &dev->tx_wdma[idx]; |
| 676 | |
| 677 | - if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE)) |
| 678 | + if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE, dev->ver)) |
| 679 | return -ENOMEM; |
| 680 | |
| 681 | wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE, |
| 682 | @@ -521,60 +771,36 @@ static void |
| 683 | mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask) |
| 684 | { |
| 685 | u32 wdma_mask; |
| 686 | - u32 val; |
| 687 | int i; |
| 688 | |
| 689 | for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++) |
| 690 | if (!dev->tx_wdma[i].desc) |
| 691 | mtk_wed_wdma_ring_setup(dev, i, 16); |
| 692 | |
| 693 | - wdma_mask = FIELD_PREP(MTK_WDMA_INT_MASK_RX_DONE, GENMASK(1, 0)); |
| 694 | |
| 695 | mtk_wed_hw_init(dev); |
| 696 | |
| 697 | - wed_set(dev, MTK_WED_CTRL, |
| 698 | - MTK_WED_CTRL_WDMA_INT_AGENT_EN | |
| 699 | - MTK_WED_CTRL_WPDMA_INT_AGENT_EN | |
| 700 | - MTK_WED_CTRL_WED_TX_BM_EN | |
| 701 | - MTK_WED_CTRL_WED_TX_FREE_AGENT_EN); |
| 702 | - |
| 703 | - wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, MTK_WED_PCIE_INT_TRIGGER_STATUS); |
| 704 | + mtk_wed_set_int(dev, irq_mask); |
| 705 | |
| 706 | - wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER, |
| 707 | - MTK_WED_WPDMA_INT_TRIGGER_RX_DONE | |
| 708 | - MTK_WED_WPDMA_INT_TRIGGER_TX_DONE); |
| 709 | - |
| 710 | - wed_set(dev, MTK_WED_WPDMA_INT_CTRL, |
| 711 | - MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV); |
| 712 | - |
| 713 | - wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, wdma_mask); |
| 714 | - wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask); |
| 715 | - |
| 716 | - wdma_w32(dev, MTK_WDMA_INT_MASK, wdma_mask); |
| 717 | - wdma_w32(dev, MTK_WDMA_INT_GRP2, wdma_mask); |
| 718 | |
| 719 | - wed_w32(dev, MTK_WED_WPDMA_INT_MASK, irq_mask); |
| 720 | - wed_w32(dev, MTK_WED_INT_MASK, irq_mask); |
| 721 | + mtk_wed_set_ext_int(dev, true); |
| 722 | |
| 723 | - wed_set(dev, MTK_WED_GLO_CFG, |
| 724 | - MTK_WED_GLO_CFG_TX_DMA_EN | |
| 725 | - MTK_WED_GLO_CFG_RX_DMA_EN); |
| 726 | - wed_set(dev, MTK_WED_WPDMA_GLO_CFG, |
| 727 | - MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN | |
| 728 | - MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN); |
| 729 | - wed_set(dev, MTK_WED_WDMA_GLO_CFG, |
| 730 | - MTK_WED_WDMA_GLO_CFG_RX_DRV_EN); |
| 731 | + if (dev->ver == MTK_WED_V1) { |
| 732 | + u32 val; |
| 733 | |
| 734 | - mtk_wed_set_ext_int(dev, true); |
| 735 | - val = dev->wlan.wpdma_phys | |
| 736 | - MTK_PCIE_MIRROR_MAP_EN | |
| 737 | - FIELD_PREP(MTK_PCIE_MIRROR_MAP_WED_ID, dev->hw->index); |
| 738 | + val = dev->wlan.wpdma_phys | |
| 739 | + MTK_PCIE_MIRROR_MAP_EN | |
| 740 | + FIELD_PREP(MTK_PCIE_MIRROR_MAP_WED_ID, dev->hw->index); |
| 741 | |
| 742 | - if (dev->hw->index) |
| 743 | - val |= BIT(1); |
| 744 | - val |= BIT(0); |
| 745 | - regmap_write(dev->hw->mirror, dev->hw->index * 4, val); |
| 746 | + if (dev->hw->index) |
| 747 | + val |= BIT(1); |
| 748 | + val |= BIT(0); |
| 749 | + regmap_write(dev->hw->mirror, dev->hw->index * 4, val); |
| 750 | + } else { |
| 751 | + mtk_wed_set_512_support(dev, true); |
| 752 | + } |
| 753 | |
| 754 | + mtk_wed_dma_enable(dev); |
| 755 | dev->running = true; |
| 756 | } |
| 757 | |
| 758 | @@ -588,15 +814,11 @@ mtk_wed_attach(struct mtk_wed_device *dev) |
| 759 | RCU_LOCKDEP_WARN(!rcu_read_lock_held(), |
| 760 | "mtk_wed_attach without holding the RCU read lock"); |
| 761 | |
| 762 | - if (pci_domain_nr(dev->wlan.pci_dev->bus) > 1 || |
| 763 | - !try_module_get(THIS_MODULE)) |
| 764 | - ret = -ENODEV; |
| 765 | + if (!try_module_get(THIS_MODULE)) |
| 766 | + return -ENODEV; |
| 767 | |
| 768 | rcu_read_unlock(); |
| 769 | |
| 770 | - if (ret) |
| 771 | - return ret; |
| 772 | - |
| 773 | mutex_lock(&hw_lock); |
| 774 | |
| 775 | hw = mtk_wed_assign(dev); |
| 776 | @@ -606,8 +828,6 @@ mtk_wed_attach(struct mtk_wed_device *dev) |
| 777 | goto out; |
| 778 | } |
| 779 | |
| 780 | - dev_info(&dev->wlan.pci_dev->dev, "attaching wed device %d\n", hw->index); |
| 781 | - |
| 782 | dev->hw = hw; |
| 783 | dev->dev = hw->dev; |
| 784 | dev->irq = hw->irq; |
| 785 | @@ -617,6 +837,9 @@ mtk_wed_attach(struct mtk_wed_device *dev) |
| 786 | of_dma_is_coherent(hw->eth->dev->of_node)) |
| 787 | mtk_eth_set_dma_device(hw->eth, hw->dev); |
| 788 | |
| 789 | + dev->ver = FIELD_GET(MTK_WED_REV_ID_MAJOR, |
| 790 | + wed_r32(dev, MTK_WED_REV_ID)); |
| 791 | + |
| 792 | ret = mtk_wed_buffer_alloc(dev); |
| 793 | if (ret) { |
| 794 | mtk_wed_detach(dev); |
| 795 | @@ -624,7 +847,10 @@ mtk_wed_attach(struct mtk_wed_device *dev) |
| 796 | } |
| 797 | |
| 798 | mtk_wed_hw_init_early(dev); |
| 799 | - regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP, BIT(hw->index), 0); |
| 800 | + |
| 801 | + if (dev->ver == MTK_WED_V1) |
| 802 | + regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP, |
| 803 | + BIT(hw->index), 0); |
| 804 | |
| 805 | out: |
| 806 | mutex_unlock(&hw_lock); |
| 807 | @@ -651,7 +877,7 @@ mtk_wed_tx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs) |
| 808 | |
| 809 | BUG_ON(idx > ARRAY_SIZE(dev->tx_ring)); |
| 810 | |
| 811 | - if (mtk_wed_ring_alloc(dev, ring, MTK_WED_TX_RING_SIZE)) |
| 812 | + if (mtk_wed_ring_alloc(dev, ring, MTK_WED_TX_RING_SIZE, 1)) |
| 813 | return -ENOMEM; |
| 814 | |
| 815 | if (mtk_wed_wdma_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE)) |
| 816 | @@ -678,21 +904,24 @@ static int |
| 817 | mtk_wed_txfree_ring_setup(struct mtk_wed_device *dev, void __iomem *regs) |
| 818 | { |
| 819 | struct mtk_wed_ring *ring = &dev->txfree_ring; |
| 820 | - int i; |
| 821 | + int i, idx = 1; |
| 822 | + |
| 823 | + if(dev->ver > MTK_WED_V1) |
| 824 | + idx = 0; |
| 825 | |
| 826 | /* |
| 827 | * For txfree event handling, the same DMA ring is shared between WED |
| 828 | * and WLAN. The WLAN driver accesses the ring index registers through |
| 829 | * WED |
| 830 | */ |
| 831 | - ring->reg_base = MTK_WED_RING_RX(1); |
| 832 | + ring->reg_base = MTK_WED_RING_RX(idx); |
| 833 | ring->wpdma = regs; |
| 834 | |
| 835 | for (i = 0; i < 12; i += 4) { |
| 836 | u32 val = readl(regs + i); |
| 837 | |
| 838 | - wed_w32(dev, MTK_WED_RING_RX(1) + i, val); |
| 839 | - wed_w32(dev, MTK_WED_WPDMA_RING_RX(1) + i, val); |
| 840 | + wed_w32(dev, MTK_WED_RING_RX(idx) + i, val); |
| 841 | + wed_w32(dev, MTK_WED_WPDMA_RING_RX(idx) + i, val); |
| 842 | } |
| 843 | |
| 844 | return 0; |
developer | 8a2ded5 | 2023-08-21 17:40:56 +0800 | [diff] [blame] | 845 | @@ -780,7 +1009,8 @@ out: |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 846 | } |
| 847 | |
| 848 | void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth, |
| 849 | - void __iomem *wdma, int index) |
| 850 | + void __iomem *wdma, u32 wdma_phy, int index) |
| 851 | + |
| 852 | { |
| 853 | static const struct mtk_wed_ops wed_ops = { |
| 854 | .attach = mtk_wed_attach, |
developer | 8a2ded5 | 2023-08-21 17:40:56 +0800 | [diff] [blame] | 855 | @@ -830,21 +1060,27 @@ void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth, |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 856 | hw->eth = eth; |
| 857 | hw->dev = &pdev->dev; |
| 858 | hw->wdma = wdma; |
| 859 | + hw->wdma_phy = wdma_phy; |
| 860 | hw->index = index; |
| 861 | hw->irq = irq; |
| 862 | - hw->mirror = syscon_regmap_lookup_by_phandle(eth_np, |
| 863 | - "mediatek,pcie-mirror"); |
| 864 | - hw->hifsys = syscon_regmap_lookup_by_phandle(eth_np, |
| 865 | - "mediatek,hifsys"); |
| 866 | - if (IS_ERR(hw->mirror) || IS_ERR(hw->hifsys)) { |
| 867 | - kfree(hw); |
| 868 | - goto unlock; |
| 869 | - } |
| 870 | |
| 871 | - if (!index) { |
| 872 | - regmap_write(hw->mirror, 0, 0); |
| 873 | - regmap_write(hw->mirror, 4, 0); |
| 874 | + if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) { |
| 875 | + hw->mirror = syscon_regmap_lookup_by_phandle(eth_np, |
| 876 | + "mediatek,pcie-mirror"); |
| 877 | + hw->hifsys = syscon_regmap_lookup_by_phandle(eth_np, |
| 878 | + "mediatek,hifsys"); |
| 879 | + |
| 880 | + if (IS_ERR(hw->mirror) || IS_ERR(hw->hifsys)) { |
| 881 | + kfree(hw); |
| 882 | + goto unlock; |
| 883 | + } |
| 884 | + |
| 885 | + if (!index) { |
| 886 | + regmap_write(hw->mirror, 0, 0); |
| 887 | + regmap_write(hw->mirror, 4, 0); |
| 888 | + } |
| 889 | } |
| 890 | + |
| 891 | mtk_wed_hw_add_debugfs(hw); |
| 892 | |
| 893 | hw_list[index] = hw; |
| 894 | diff --git a/drivers/net/ethernet/mediatek/mtk_wed.h b/drivers/net/ethernet/mediatek/mtk_wed.h |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 895 | index 981ec613f..9b17b7405 100644 |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 896 | --- a/drivers/net/ethernet/mediatek/mtk_wed.h |
| 897 | +++ b/drivers/net/ethernet/mediatek/mtk_wed.h |
| 898 | @@ -8,6 +8,19 @@ |
| 899 | #include <linux/debugfs.h> |
| 900 | #include <linux/regmap.h> |
| 901 | #include <linux/netdevice.h> |
| 902 | +#define MTK_PCIE_BASE(n) (0x1a143000 + (n) * 0x2000) |
| 903 | + |
| 904 | +#define MTK_WED_PKT_SIZE 1900 |
| 905 | +#define MTK_WED_BUF_SIZE 2048 |
| 906 | +#define MTK_WED_BUF_PER_PAGE (PAGE_SIZE / 2048) |
| 907 | + |
| 908 | +#define MTK_WED_TX_RING_SIZE 2048 |
| 909 | +#define MTK_WED_WDMA_RING_SIZE 512 |
| 910 | +#define MTK_WED_MAX_GROUP_SIZE 0x100 |
| 911 | +#define MTK_WED_VLD_GROUP_SIZE 0x40 |
| 912 | +#define MTK_WED_PER_GROUP_PKT 128 |
| 913 | + |
| 914 | +#define MTK_WED_FBUF_SIZE 128 |
| 915 | |
| 916 | struct mtk_eth; |
| 917 | |
| 918 | @@ -23,6 +36,7 @@ struct mtk_wed_hw { |
| 919 | struct mtk_wed_device *wed_dev; |
| 920 | u32 debugfs_reg; |
| 921 | u32 num_flows; |
| 922 | + u32 wdma_phy; |
| 923 | char dirname[5]; |
| 924 | int irq; |
| 925 | int index; |
| 926 | @@ -101,14 +115,14 @@ wpdma_txfree_w32(struct mtk_wed_device *dev, u32 reg, u32 val) |
| 927 | } |
| 928 | |
| 929 | void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth, |
| 930 | - void __iomem *wdma, int index); |
| 931 | + void __iomem *wdma, u32 wdma_phy, int index); |
| 932 | void mtk_wed_exit(void); |
| 933 | int mtk_wed_flow_add(int index); |
| 934 | void mtk_wed_flow_remove(int index); |
| 935 | #else |
| 936 | static inline void |
| 937 | mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth, |
| 938 | - void __iomem *wdma, int index) |
| 939 | + void __iomem *wdma, u32 wdma_phy, int index) |
| 940 | { |
| 941 | } |
| 942 | static inline void |
| 943 | diff --git a/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 944 | index a81d3fd1a..f420f187e 100644 |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 945 | --- a/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c |
| 946 | +++ b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c |
| 947 | @@ -116,6 +116,9 @@ wed_txinfo_show(struct seq_file *s, void *data) |
| 948 | DUMP_WDMA(WDMA_GLO_CFG), |
| 949 | DUMP_WDMA_RING(WDMA_RING_RX(0)), |
| 950 | DUMP_WDMA_RING(WDMA_RING_RX(1)), |
| 951 | + |
| 952 | + DUMP_STR("TX FREE"), |
| 953 | + DUMP_WED(WED_RX_MIB(0)), |
| 954 | }; |
| 955 | struct mtk_wed_hw *hw = s->private; |
| 956 | struct mtk_wed_device *dev = hw->wed_dev; |
| 957 | diff --git a/drivers/net/ethernet/mediatek/mtk_wed_regs.h b/drivers/net/ethernet/mediatek/mtk_wed_regs.h |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 958 | index 0a0465ea5..69f136ed4 100644 |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 959 | --- a/drivers/net/ethernet/mediatek/mtk_wed_regs.h |
| 960 | +++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h |
| 961 | @@ -4,9 +4,15 @@ |
| 962 | #ifndef __MTK_WED_REGS_H |
| 963 | #define __MTK_WED_REGS_H |
| 964 | |
| 965 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 966 | +#define MTK_WDMA_DESC_CTRL_LEN1 GENMASK(13, 0) |
| 967 | +#define MTK_WDMA_DESC_CTRL_LAST_SEG1 BIT(14) |
| 968 | +#define MTK_WDMA_DESC_CTRL_BURST BIT(15) |
| 969 | +#else |
| 970 | #define MTK_WDMA_DESC_CTRL_LEN1 GENMASK(14, 0) |
| 971 | #define MTK_WDMA_DESC_CTRL_LAST_SEG1 BIT(15) |
| 972 | #define MTK_WDMA_DESC_CTRL_BURST BIT(16) |
| 973 | +#endif |
| 974 | #define MTK_WDMA_DESC_CTRL_LEN0 GENMASK(29, 16) |
| 975 | #define MTK_WDMA_DESC_CTRL_LAST_SEG0 BIT(30) |
| 976 | #define MTK_WDMA_DESC_CTRL_DMA_DONE BIT(31) |
developer | f50c180 | 2022-07-05 20:35:53 +0800 | [diff] [blame] | 977 | @@ -18,6 +24,14 @@ struct mtk_wdma_desc { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 978 | __le32 info; |
| 979 | } __packed __aligned(4); |
| 980 | |
developer | f50c180 | 2022-07-05 20:35:53 +0800 | [diff] [blame] | 981 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 982 | +#define MTK_WED_REV_ID 0x004 |
| 983 | +#define MTK_WED_REV_ID_MAJOR GENMASK(31, 28) |
developer | f50c180 | 2022-07-05 20:35:53 +0800 | [diff] [blame] | 984 | +#else |
| 985 | +#define MTK_WED_REV_ID 0x000 |
| 986 | +#define MTK_WED_REV_ID_MAJOR GENMASK(7, 0) |
| 987 | +#endif |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 988 | + |
| 989 | #define MTK_WED_RESET 0x008 |
| 990 | #define MTK_WED_RESET_TX_BM BIT(0) |
| 991 | #define MTK_WED_RESET_TX_FREE_AGENT BIT(4) |
developer | 8a2ded5 | 2023-08-21 17:40:56 +0800 | [diff] [blame] | 992 | @@ -41,6 +55,7 @@ struct mtk_wdma_desc { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 993 | #define MTK_WED_CTRL_RESERVE_EN BIT(12) |
| 994 | #define MTK_WED_CTRL_RESERVE_BUSY BIT(13) |
| 995 | #define MTK_WED_CTRL_FINAL_DIDX_READ BIT(24) |
| 996 | +#define MTK_WED_CTRL_ETH_DMAD_FMT BIT(25) |
| 997 | #define MTK_WED_CTRL_MIB_READ_CLEAR BIT(28) |
| 998 | |
| 999 | #define MTK_WED_EXT_INT_STATUS 0x020 |
developer | 8a2ded5 | 2023-08-21 17:40:56 +0800 | [diff] [blame] | 1000 | @@ -49,6 +64,10 @@ struct mtk_wdma_desc { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1001 | #define MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID BIT(4) |
| 1002 | #define MTK_WED_EXT_INT_STATUS_TX_FBUF_LO_TH BIT(8) |
| 1003 | #define MTK_WED_EXT_INT_STATUS_TX_FBUF_HI_TH BIT(9) |
| 1004 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 1005 | +#define MTK_WED_EXT_INT_STATUS_TX_TKID_LO_TH BIT(10) |
| 1006 | +#define MTK_WED_EXT_INT_STATUS_TX_TKID_HI_TH BIT(11) |
| 1007 | +#endif |
| 1008 | #define MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH BIT(12) |
| 1009 | #define MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH BIT(13) |
| 1010 | #define MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR BIT(16) |
developer | 8a2ded5 | 2023-08-21 17:40:56 +0800 | [diff] [blame] | 1011 | @@ -57,16 +76,23 @@ struct mtk_wdma_desc { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1012 | #define MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN BIT(19) |
| 1013 | #define MTK_WED_EXT_INT_STATUS_RX_DRV_BM_DMAD_COHERENT BIT(20) |
| 1014 | #define MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR BIT(21) |
| 1015 | -#define MTK_WED_EXT_INT_STATUS_TX_DRV_W_RESP_ERR BIT(22) |
| 1016 | +#define MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR BIT(22) |
| 1017 | +#define MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR BIT(23) |
| 1018 | #define MTK_WED_EXT_INT_STATUS_RX_DRV_DMA_RECYCLE BIT(24) |
| 1019 | +#define MTK_WED_EXT_INT_STATUS_RX_DRV_GET_BM_DMAD_SKIP BIT(25) |
| 1020 | +#define MTK_WED_EXT_INT_STATUS_WPDMA_RX_D_DRV_ERR BIT(26) |
| 1021 | +#define MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY BIT(27) |
| 1022 | + |
| 1023 | #define MTK_WED_EXT_INT_STATUS_ERROR_MASK (MTK_WED_EXT_INT_STATUS_TF_LEN_ERR | \ |
| 1024 | MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD | \ |
| 1025 | MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID | \ |
| 1026 | + MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH | \ |
| 1027 | + MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH | \ |
| 1028 | MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR | \ |
| 1029 | MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR | \ |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1030 | MTK_WED_EXT_INT_STATUS_RX_DRV_INIT_WDMA_EN | \ |
| 1031 | - MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR | \ |
| 1032 | - MTK_WED_EXT_INT_STATUS_TX_DRV_W_RESP_ERR) |
| 1033 | + MTK_WED_EXT_INT_STATUS_TX_DMA_R_RESP_ERR | \ |
| 1034 | + MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR) |
| 1035 | |
| 1036 | #define MTK_WED_EXT_INT_MASK 0x028 |
| 1037 | |
developer | 8a2ded5 | 2023-08-21 17:40:56 +0800 | [diff] [blame] | 1038 | @@ -80,10 +106,6 @@ struct mtk_wdma_desc { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1039 | |
| 1040 | #define MTK_WED_TX_BM_BASE 0x084 |
| 1041 | |
| 1042 | -#define MTK_WED_TX_BM_TKID 0x088 |
| 1043 | -#define MTK_WED_TX_BM_TKID_START GENMASK(15, 0) |
| 1044 | -#define MTK_WED_TX_BM_TKID_END GENMASK(31, 16) |
| 1045 | - |
| 1046 | #define MTK_WED_TX_BM_BUF_LEN 0x08c |
| 1047 | |
| 1048 | #define MTK_WED_TX_BM_INTF 0x09c |
developer | 8a2ded5 | 2023-08-21 17:40:56 +0800 | [diff] [blame] | 1049 | @@ -93,9 +115,38 @@ struct mtk_wdma_desc { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1050 | #define MTK_WED_TX_BM_INTF_TKID_READ BIT(29) |
| 1051 | |
| 1052 | #define MTK_WED_TX_BM_DYN_THR 0x0a0 |
| 1053 | +#if defined(CONFIG_MEDIATEK_NETSYS_V2) |
| 1054 | +#define MTK_WED_TX_BM_DYN_THR_LO GENMASK(8, 0) |
| 1055 | +#define MTK_WED_TX_BM_DYN_THR_HI GENMASK(24, 16) |
| 1056 | + |
| 1057 | +#define MTK_WED_TX_BM_TKID 0x0c8 |
| 1058 | +#define MTK_WED_TX_BM_TKID_START GENMASK(15, 0) |
| 1059 | +#define MTK_WED_TX_BM_TKID_END GENMASK(31, 16) |
| 1060 | +#else |
| 1061 | #define MTK_WED_TX_BM_DYN_THR_LO GENMASK(6, 0) |
| 1062 | #define MTK_WED_TX_BM_DYN_THR_HI GENMASK(22, 16) |
| 1063 | |
| 1064 | +#define MTK_WED_TX_BM_TKID 0x088 |
| 1065 | +#define MTK_WED_TX_BM_TKID_START GENMASK(15, 0) |
| 1066 | +#define MTK_WED_TX_BM_TKID_END GENMASK(31, 16) |
| 1067 | +#endif |
| 1068 | + |
| 1069 | +#define MTK_WED_TX_TKID_CTRL 0x0c0 |
| 1070 | +#define MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM GENMASK(6, 0) |
| 1071 | +#define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM GENMASK(22, 16) |
| 1072 | +#define MTK_WED_TX_TKID_CTRL_PAUSE BIT(28) |
| 1073 | + |
| 1074 | +#define MTK_WED_TX_TKID_DYN_THR 0x0e0 |
| 1075 | +#define MTK_WED_TX_TKID_DYN_THR_LO GENMASK(6, 0) |
| 1076 | +#define MTK_WED_TX_TKID_DYN_THR_HI GENMASK(22, 16) |
| 1077 | + |
| 1078 | +#define MTK_WED_TXP_DW0 0x120 |
| 1079 | +#define MTK_WED_TXP_DW1 0x124 |
| 1080 | +#define MTK_WED_WPDMA_WRITE_TXP GENMASK(31, 16) |
| 1081 | +#define MTK_WED_TXDP_CTRL 0x130 |
| 1082 | +#define MTK_WED_TXDP_DW9_OVERWR BIT(9) |
| 1083 | +#define MTK_WED_RX_BM_TKID_MIB 0x1cc |
| 1084 | + |
| 1085 | #define MTK_WED_INT_STATUS 0x200 |
| 1086 | #define MTK_WED_INT_MASK 0x204 |
| 1087 | |
developer | 8a2ded5 | 2023-08-21 17:40:56 +0800 | [diff] [blame] | 1088 | @@ -125,6 +176,7 @@ struct mtk_wdma_desc { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1089 | #define MTK_WED_RESET_IDX_RX GENMASK(17, 16) |
| 1090 | |
| 1091 | #define MTK_WED_TX_MIB(_n) (0x2a0 + (_n) * 4) |
| 1092 | +#define MTK_WED_RX_MIB(_n) (0x2e0 + (_n) * 4) |
| 1093 | |
| 1094 | #define MTK_WED_RING_TX(_n) (0x300 + (_n) * 0x10) |
| 1095 | |
developer | 8a2ded5 | 2023-08-21 17:40:56 +0800 | [diff] [blame] | 1096 | @@ -139,6 +191,19 @@ struct mtk_wdma_desc { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1097 | #define MTK_WED_WPDMA_GLO_CFG_TX_DRV_BUSY BIT(1) |
| 1098 | #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN BIT(2) |
| 1099 | #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_BUSY BIT(3) |
| 1100 | +/* CONFIG_MEDIATEK_NETSYS_V2 */ |
| 1101 | +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC BIT(4) |
| 1102 | +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_PKT_PROC BIT(5) |
| 1103 | +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC BIT(6) |
| 1104 | +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_CRX_SYNC BIT(7) |
| 1105 | +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_VER GENMASK(18, 16) |
| 1106 | +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNSUPPORT_FMT BIT(19) |
| 1107 | +#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UEVENT_PKT_FMT_CHK BIT(20) |
| 1108 | +#define MTK_WED_WPDMA_GLO_CFG_RX_DDONE2_WR BIT(21) |
| 1109 | +#define MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP BIT(24) |
| 1110 | +#define MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV BIT(28) |
| 1111 | + |
| 1112 | +/* CONFIG_MEDIATEK_NETSYS_V1 */ |
| 1113 | #define MTK_WED_WPDMA_GLO_CFG_RX_BT_SIZE GENMASK(5, 4) |
| 1114 | #define MTK_WED_WPDMA_GLO_CFG_TX_WB_DDONE BIT(6) |
| 1115 | #define MTK_WED_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7) |
developer | 8a2ded5 | 2023-08-21 17:40:56 +0800 | [diff] [blame] | 1116 | @@ -152,24 +217,54 @@ struct mtk_wdma_desc { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1117 | #define MTK_WED_WPDMA_GLO_CFG_FIRST_TOKEN_ONLY BIT(26) |
| 1118 | #define MTK_WED_WPDMA_GLO_CFG_OMIT_RX_INFO BIT(27) |
| 1119 | #define MTK_WED_WPDMA_GLO_CFG_OMIT_TX_INFO BIT(28) |
| 1120 | + |
| 1121 | #define MTK_WED_WPDMA_GLO_CFG_BYTE_SWAP BIT(29) |
| 1122 | +#define MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK BIT(30) |
| 1123 | #define MTK_WED_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31) |
| 1124 | |
| 1125 | #define MTK_WED_WPDMA_RESET_IDX 0x50c |
| 1126 | #define MTK_WED_WPDMA_RESET_IDX_TX GENMASK(3, 0) |
| 1127 | #define MTK_WED_WPDMA_RESET_IDX_RX GENMASK(17, 16) |
| 1128 | |
| 1129 | +#define MTK_WED_WPDMA_CTRL 0x518 |
| 1130 | +#define MTK_WED_WPDMA_CTRL_SDL1_FIXED BIT(31) |
| 1131 | + |
| 1132 | #define MTK_WED_WPDMA_INT_CTRL 0x520 |
| 1133 | #define MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV BIT(21) |
| 1134 | +#define MTK_WED_WPDMA_INT_CTRL_SIG_SRC BIT(22) |
| 1135 | +#define MTK_WED_WPDMA_INT_CTRL_SRC_SEL GENMASK(17, 16) |
| 1136 | |
| 1137 | #define MTK_WED_WPDMA_INT_MASK 0x524 |
| 1138 | |
| 1139 | -#define MTK_WED_PCIE_CFG_BASE 0x560 |
| 1140 | +#define MTK_WED_WPDMA_INT_CTRL_TX 0x530 |
| 1141 | +#define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN BIT(0) |
| 1142 | +#define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_CLR BIT(1) |
| 1143 | +#define MTK_WED_WPDMA_INT_CTRL_TX0_DONE_TRIG GENMASK(6, 2) |
| 1144 | +#define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_EN BIT(8) |
| 1145 | +#define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_CLR BIT(9) |
| 1146 | +#define MTK_WED_WPDMA_INT_CTRL_TX1_DONE_TRIG GENMASK(14, 10) |
| 1147 | + |
| 1148 | +#define MTK_WED_WPDMA_INT_CTRL_RX 0x534 |
| 1149 | + |
| 1150 | +#define MTK_WED_WPDMA_INT_CTRL_TX_FREE 0x538 |
| 1151 | +#define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_EN BIT(0) |
| 1152 | +#define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_CLR BIT(1) |
| 1153 | +#define MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG GENMASK(6, 2) |
| 1154 | |
| 1155 | +#define MTK_WED_PCIE_CFG_BASE 0x560 |
| 1156 | +#define MTK_WED_PCIE_CFG_INTM 0x564 |
| 1157 | +#define MTK_WED_PCIE_CFG_MSIS 0x568 |
| 1158 | #define MTK_WED_PCIE_INT_TRIGGER 0x570 |
| 1159 | #define MTK_WED_PCIE_INT_TRIGGER_STATUS BIT(16) |
| 1160 | |
| 1161 | +#define MTK_WED_PCIE_INT_CTRL 0x57c |
| 1162 | +#define MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA BIT(20) |
| 1163 | +#define MTK_WED_PCIE_INT_CTRL_SRC_SEL GENMASK(17, 16) |
| 1164 | +#define MTK_WED_PCIE_INT_CTRL_POLL_EN GENMASK(13, 12) |
| 1165 | #define MTK_WED_WPDMA_CFG_BASE 0x580 |
| 1166 | +#define MTK_WED_WPDMA_CFG_INT_MASK 0x584 |
| 1167 | +#define MTK_WED_WPDMA_CFG_TX 0x588 |
| 1168 | +#define MTK_WED_WPDMA_CFG_TX_FREE 0x58c |
| 1169 | |
| 1170 | #define MTK_WED_WPDMA_TX_MIB(_n) (0x5a0 + (_n) * 4) |
| 1171 | #define MTK_WED_WPDMA_TX_COHERENT_MIB(_n) (0x5d0 + (_n) * 4) |
developer | 8a2ded5 | 2023-08-21 17:40:56 +0800 | [diff] [blame] | 1172 | @@ -203,14 +298,22 @@ struct mtk_wdma_desc { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1173 | #define MTK_WED_WDMA_RESET_IDX_RX GENMASK(17, 16) |
| 1174 | #define MTK_WED_WDMA_RESET_IDX_DRV GENMASK(25, 24) |
| 1175 | |
| 1176 | +#define MTK_WED_WDMA_INT_CLR 0xa24 |
| 1177 | +#define MTK_WED_WDMA_INT_CLR_RX_DONE GENMASK(17, 16) |
| 1178 | + |
| 1179 | #define MTK_WED_WDMA_INT_TRIGGER 0xa28 |
| 1180 | #define MTK_WED_WDMA_INT_TRIGGER_RX_DONE GENMASK(17, 16) |
| 1181 | |
| 1182 | #define MTK_WED_WDMA_INT_CTRL 0xa2c |
| 1183 | -#define MTK_WED_WDMA_INT_CTRL_POLL_SRC_SEL GENMASK(17, 16) |
| 1184 | +#define MTK_WED_WDMA_INT_POLL_SRC_SEL GENMASK(17, 16) |
| 1185 | |
| 1186 | +#define MTK_WED_WDMA_CFG_BASE 0xaa0 |
| 1187 | #define MTK_WED_WDMA_OFFSET0 0xaa4 |
| 1188 | #define MTK_WED_WDMA_OFFSET1 0xaa8 |
| 1189 | +#define MTK_WED_WDMA_OFST0_GLO_INTS GENMASK(15, 0) |
| 1190 | +#define MTK_WED_WDMA_OFST0_GLO_CFG GENMASK(31, 16) |
| 1191 | +#define MTK_WED_WDMA_OFST1_TX_CTRL GENMASK(15, 0) |
| 1192 | +#define MTK_WED_WDMA_OFST1_RX_CTRL GENMASK(31, 16) |
| 1193 | |
| 1194 | #define MTK_WED_WDMA_RX_MIB(_n) (0xae0 + (_n) * 4) |
| 1195 | #define MTK_WED_WDMA_RX_RECYCLE_MIB(_n) (0xae8 + (_n) * 4) |
developer | 8a2ded5 | 2023-08-21 17:40:56 +0800 | [diff] [blame] | 1196 | @@ -221,14 +324,21 @@ struct mtk_wdma_desc { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1197 | #define MTK_WED_RING_OFS_CPU_IDX 0x08 |
| 1198 | #define MTK_WED_RING_OFS_DMA_IDX 0x0c |
| 1199 | |
| 1200 | +#define MTK_WDMA_RING_TX(_n) (0x000 + (_n) * 0x10) |
| 1201 | #define MTK_WDMA_RING_RX(_n) (0x100 + (_n) * 0x10) |
| 1202 | |
| 1203 | #define MTK_WDMA_GLO_CFG 0x204 |
| 1204 | -#define MTK_WDMA_GLO_CFG_RX_INFO_PRERES GENMASK(28, 26) |
| 1205 | +#define MTK_WDMA_GLO_CFG_TX_DMA_EN BIT(0) |
| 1206 | +#define MTK_WDMA_GLO_CFG_RX_DMA_EN BIT(2) |
| 1207 | +#define MTK_WDMA_GLO_CFG_RX_INFO3_PRERES BIT(26) |
| 1208 | +#define MTK_WDMA_GLO_CFG_RX_INFO2_PRERES BIT(27) |
| 1209 | +#define MTK_WDMA_GLO_CFG_RX_INFO1_PRERES BIT(28) |
| 1210 | + |
| 1211 | |
| 1212 | #define MTK_WDMA_RESET_IDX 0x208 |
| 1213 | #define MTK_WDMA_RESET_IDX_TX GENMASK(3, 0) |
| 1214 | #define MTK_WDMA_RESET_IDX_RX GENMASK(17, 16) |
| 1215 | +#define MTK_WDMA_INT_STATUS 0x220 |
| 1216 | |
| 1217 | #define MTK_WDMA_INT_MASK 0x228 |
| 1218 | #define MTK_WDMA_INT_MASK_TX_DONE GENMASK(3, 0) |
| 1219 | diff --git a/include/linux/soc/mediatek/mtk_wed.h b/include/linux/soc/mediatek/mtk_wed.h |
developer | ee39bcf | 2023-06-16 08:03:30 +0800 | [diff] [blame] | 1220 | index 7e00cca06..24742604b 100644 |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1221 | --- a/include/linux/soc/mediatek/mtk_wed.h |
| 1222 | +++ b/include/linux/soc/mediatek/mtk_wed.h |
| 1223 | @@ -8,6 +8,19 @@ |
| 1224 | |
| 1225 | #define MTK_WED_TX_QUEUES 2 |
| 1226 | |
| 1227 | +enum { |
| 1228 | + MTK_NO_WED, |
| 1229 | + MTK_WED_V1, |
| 1230 | + MTK_WED_V2, |
| 1231 | + MTK_WED_VMAX |
| 1232 | +}; |
| 1233 | + |
| 1234 | +enum { |
| 1235 | + MTK_BUS_TYPE_PCIE, |
| 1236 | + MTK_BUS_TYPE_AXI, |
| 1237 | + MTK_BUS_TYPE_MAX |
| 1238 | +}; |
| 1239 | + |
| 1240 | struct mtk_wed_hw; |
| 1241 | struct mtk_wdma_desc; |
| 1242 | |
| 1243 | @@ -28,6 +41,7 @@ struct mtk_wed_device { |
| 1244 | bool init_done, running; |
| 1245 | int wdma_idx; |
| 1246 | int irq; |
| 1247 | + u8 ver; |
| 1248 | |
| 1249 | struct mtk_wed_ring tx_ring[MTK_WED_TX_QUEUES]; |
| 1250 | struct mtk_wed_ring txfree_ring; |
developer | 2cd6d28 | 2022-07-07 18:17:32 +0800 | [diff] [blame] | 1251 | @@ -43,8 +57,17 @@ struct mtk_wed_device { |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1252 | /* filled by driver: */ |
| 1253 | struct { |
| 1254 | struct pci_dev *pci_dev; |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1255 | + void __iomem *base; |
| 1256 | + u32 bus_type; |
developer | 2cd6d28 | 2022-07-07 18:17:32 +0800 | [diff] [blame] | 1257 | |
| 1258 | u32 wpdma_phys; |
| 1259 | + u32 wpdma_int; |
developer | 8cb3ac7 | 2022-07-04 10:55:14 +0800 | [diff] [blame] | 1260 | + u32 wpdma_mask; |
| 1261 | + u32 wpdma_tx; |
| 1262 | + u32 wpdma_txfree; |
| 1263 | + |
| 1264 | + u8 tx_tbit[MTK_WED_TX_QUEUES]; |
| 1265 | + u8 txfree_tbit; |
| 1266 | |
| 1267 | u16 token_start; |
| 1268 | unsigned int nbuf; |
| 1269 | -- |
| 1270 | 2.18.0 |
| 1271 | |