developer | f1422f6 | 2021-09-14 13:59:15 +0800 | [diff] [blame] | 1 | /dts-v1/; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 2 | #include "mt7986b.dtsi" |
| 3 | #include "mt7986b-pinctrl.dtsi" |
developer | f1422f6 | 2021-09-14 13:59:15 +0800 | [diff] [blame] | 4 | / { |
| 5 | model = "MediaTek MT7986b RFB"; |
| 6 | compatible = "mediatek,mt7986b-emmc-rfb"; |
developer | f1422f6 | 2021-09-14 13:59:15 +0800 | [diff] [blame] | 7 | chosen { |
| 8 | bootargs = "console=ttyS0,115200n1 loglevel=8 \ |
| 9 | earlycon=uart8250,mmio32,0x11002000 \ |
developer | 8262b0d | 2021-11-12 09:02:17 +0800 | [diff] [blame] | 10 | root=PARTLABEL=rootfs rootwait rootfstype=squashfs,f2fs"; |
developer | f1422f6 | 2021-09-14 13:59:15 +0800 | [diff] [blame] | 11 | }; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 12 | |
| 13 | memory { |
| 14 | reg = <0 0x40000000 0 0x10000000>; |
| 15 | }; |
| 16 | |
| 17 | reg_3p3v: regulator-3p3v { |
| 18 | compatible = "regulator-fixed"; |
| 19 | regulator-name = "fixed-3.3V"; |
| 20 | regulator-min-microvolt = <3300000>; |
| 21 | regulator-max-microvolt = <3300000>; |
| 22 | regulator-boot-on; |
| 23 | regulator-always-on; |
| 24 | }; |
developer | f1422f6 | 2021-09-14 13:59:15 +0800 | [diff] [blame] | 25 | }; |
| 26 | |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 27 | &uart0 { |
| 28 | status = "okay"; |
| 29 | }; |
| 30 | |
| 31 | /* Warning: pins shared with &snand */ |
| 32 | &uart1 { |
| 33 | pinctrl-names = "default"; |
| 34 | pinctrl-0 = <&uart1_pins>; |
developer | f1422f6 | 2021-09-14 13:59:15 +0800 | [diff] [blame] | 35 | status = "disabled"; |
| 36 | }; |
| 37 | |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 38 | /* Warning: pins shared with &spi1 */ |
| 39 | &uart2 { |
| 40 | pinctrl-names = "default"; |
| 41 | pinctrl-0 = <&uart2_pins>; |
developer | f1422f6 | 2021-09-14 13:59:15 +0800 | [diff] [blame] | 42 | status = "disabled"; |
| 43 | }; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 44 | |
| 45 | &i2c0 { |
| 46 | pinctrl-names = "default"; |
| 47 | pinctrl-0 = <&i2c_pins>; |
| 48 | status = "okay"; |
| 49 | }; |
| 50 | |
| 51 | &watchdog { |
| 52 | status = "okay"; |
| 53 | }; |
| 54 | |
| 55 | ð { |
| 56 | status = "okay"; |
| 57 | |
| 58 | gmac0: mac@0 { |
| 59 | compatible = "mediatek,eth-mac"; |
| 60 | reg = <0>; |
| 61 | phy-mode = "2500base-x"; |
| 62 | |
| 63 | fixed-link { |
| 64 | speed = <2500>; |
| 65 | full-duplex; |
| 66 | pause; |
| 67 | }; |
| 68 | }; |
| 69 | |
| 70 | gmac1: mac@1 { |
| 71 | compatible = "mediatek,eth-mac"; |
| 72 | reg = <1>; |
| 73 | phy-mode = "2500base-x"; |
| 74 | |
| 75 | fixed-link { |
| 76 | speed = <2500>; |
| 77 | full-duplex; |
| 78 | pause; |
| 79 | }; |
| 80 | }; |
| 81 | |
| 82 | mdio: mdio-bus { |
| 83 | #address-cells = <1>; |
| 84 | #size-cells = <0>; |
| 85 | |
| 86 | phy5: phy@5 { |
| 87 | compatible = "ethernet-phy-id67c9.de0a"; |
| 88 | reg = <5>; |
| 89 | reset-gpios = <&pio 6 1>; |
developer | 8c5a08b | 2022-05-06 09:10:38 +0800 | [diff] [blame] | 90 | reset-assert-us = <600>; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 91 | reset-deassert-us = <20000>; |
| 92 | phy-mode = "2500base-x"; |
| 93 | }; |
| 94 | |
| 95 | phy6: phy@6 { |
| 96 | compatible = "ethernet-phy-id67c9.de0a"; |
| 97 | reg = <6>; |
| 98 | phy-mode = "2500base-x"; |
| 99 | }; |
| 100 | |
| 101 | switch@0 { |
| 102 | compatible = "mediatek,mt7531"; |
| 103 | reg = <31>; |
| 104 | reset-gpios = <&pio 5 0>; |
| 105 | |
| 106 | ports { |
| 107 | #address-cells = <1>; |
| 108 | #size-cells = <0>; |
| 109 | |
| 110 | port@0 { |
| 111 | reg = <0>; |
| 112 | label = "lan0"; |
| 113 | }; |
| 114 | |
| 115 | port@1 { |
| 116 | reg = <1>; |
| 117 | label = "lan1"; |
| 118 | }; |
| 119 | |
| 120 | port@2 { |
| 121 | reg = <2>; |
| 122 | label = "lan2"; |
| 123 | }; |
| 124 | |
| 125 | port@3 { |
| 126 | reg = <3>; |
| 127 | label = "lan3"; |
| 128 | }; |
| 129 | |
| 130 | port@6 { |
| 131 | reg = <6>; |
| 132 | label = "cpu"; |
| 133 | ethernet = <&gmac0>; |
| 134 | phy-mode = "2500base-x"; |
| 135 | |
| 136 | fixed-link { |
| 137 | speed = <2500>; |
| 138 | full-duplex; |
| 139 | pause; |
| 140 | }; |
| 141 | }; |
| 142 | }; |
| 143 | }; |
| 144 | }; |
| 145 | }; |
| 146 | |
| 147 | &hnat { |
| 148 | mtketh-wan = "eth1"; |
| 149 | mtketh-lan = "lan"; |
| 150 | mtketh-max-gmac = <2>; |
| 151 | status = "okay"; |
| 152 | }; |
| 153 | |
| 154 | /* Warning: pins shared with &uart2 */ |
| 155 | &spi1 { |
| 156 | pinctrl-names = "default"; |
| 157 | pinctrl-0 = <&spic_pins>; |
| 158 | status = "okay"; |
| 159 | }; |
| 160 | |
| 161 | &mmc0 { |
| 162 | pinctrl-names = "default", "state_uhs"; |
| 163 | pinctrl-0 = <&mmc0_pins_default>; |
| 164 | pinctrl-1 = <&mmc0_pins_uhs>; |
| 165 | bus-width = <8>; |
developer | f77870c | 2021-12-14 14:39:02 +0800 | [diff] [blame] | 166 | max-frequency = <52000000>; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 167 | cap-mmc-highspeed; |
| 168 | vmmc-supply = <®_3p3v>; |
| 169 | vqmmc-supply = <®_3p3v>; |
| 170 | non-removable; |
developer | f77870c | 2021-12-14 14:39:02 +0800 | [diff] [blame] | 171 | no-sd; |
| 172 | no-sdio; |
developer | 565bacb | 2021-09-28 21:26:32 +0800 | [diff] [blame] | 173 | status = "okay"; |
| 174 | }; |
| 175 | |
| 176 | &wbsys { |
| 177 | status = "okay"; |
| 178 | }; |
| 179 | |
| 180 | &pio { |
| 181 | mmc0_pins_default: mmc0-pins-22-to-32-default { |
| 182 | mux { |
| 183 | function = "flash"; |
| 184 | groups = "emmc_45"; |
| 185 | }; |
| 186 | conf-cmd-dat { |
| 187 | pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", |
| 188 | "SPI0_CS", "SPI0_HOLD", "SPI0_WP", |
| 189 | "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; |
| 190 | input-enable; |
| 191 | drive-strength = <MTK_DRIVE_4mA>; |
| 192 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 193 | }; |
| 194 | conf-clk { |
| 195 | pins = "SPI1_CS"; |
| 196 | drive-strength = <MTK_DRIVE_6mA>; |
| 197 | mediatek,pull-down-adv = <2>; /* pull-down 50K */ |
| 198 | }; |
| 199 | conf-rst { |
| 200 | pins = "PWM1"; |
| 201 | drive-strength = <MTK_DRIVE_4mA>; |
| 202 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 203 | }; |
| 204 | }; |
| 205 | |
| 206 | mmc0_pins_uhs: mmc0-pins-22-to-32-uhs { |
| 207 | mux { |
| 208 | function = "flash"; |
| 209 | groups = "emmc_45"; |
| 210 | }; |
| 211 | conf-cmd-dat { |
| 212 | pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", |
| 213 | "SPI0_CS", "SPI0_HOLD", "SPI0_WP", |
| 214 | "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; |
| 215 | input-enable; |
| 216 | drive-strength = <MTK_DRIVE_4mA>; |
| 217 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 218 | }; |
| 219 | conf-clk { |
| 220 | pins = "SPI1_CS"; |
| 221 | drive-strength = <MTK_DRIVE_6mA>; |
| 222 | mediatek,pull-down-adv = <2>; /* pull-down 50K */ |
| 223 | }; |
| 224 | conf-rst { |
| 225 | pins = "PWM1"; |
| 226 | drive-strength = <MTK_DRIVE_4mA>; |
| 227 | mediatek,pull-up-adv = <1>; /* pull-up 10K */ |
| 228 | }; |
| 229 | }; |
| 230 | }; |