blob: 483c0981d3604dc9a5e828c49b8928a239150272 [file] [log] [blame]
developerf1422f62021-09-14 13:59:15 +08001/dts-v1/;
developer565bacb2021-09-28 21:26:32 +08002#include "mt7986b.dtsi"
3#include "mt7986b-pinctrl.dtsi"
developerf1422f62021-09-14 13:59:15 +08004/ {
5 model = "MediaTek MT7986b RFB";
6 compatible = "mediatek,mt7986b-emmc-rfb";
developerf1422f62021-09-14 13:59:15 +08007 chosen {
8 bootargs = "console=ttyS0,115200n1 loglevel=8 \
9 earlycon=uart8250,mmio32,0x11002000 \
developer8262b0d2021-11-12 09:02:17 +080010 root=PARTLABEL=rootfs rootwait rootfstype=squashfs,f2fs";
developerf1422f62021-09-14 13:59:15 +080011 };
developer565bacb2021-09-28 21:26:32 +080012
13 memory {
14 reg = <0 0x40000000 0 0x10000000>;
15 };
16
17 reg_3p3v: regulator-3p3v {
18 compatible = "regulator-fixed";
19 regulator-name = "fixed-3.3V";
20 regulator-min-microvolt = <3300000>;
21 regulator-max-microvolt = <3300000>;
22 regulator-boot-on;
23 regulator-always-on;
24 };
developerf1422f62021-09-14 13:59:15 +080025};
26
developer565bacb2021-09-28 21:26:32 +080027&uart0 {
28 status = "okay";
29};
30
31/* Warning: pins shared with &snand */
32&uart1 {
33 pinctrl-names = "default";
34 pinctrl-0 = <&uart1_pins>;
developerf1422f62021-09-14 13:59:15 +080035 status = "disabled";
36};
37
developer565bacb2021-09-28 21:26:32 +080038/* Warning: pins shared with &spi1 */
39&uart2 {
40 pinctrl-names = "default";
41 pinctrl-0 = <&uart2_pins>;
developerf1422f62021-09-14 13:59:15 +080042 status = "disabled";
43};
developer565bacb2021-09-28 21:26:32 +080044
45&i2c0 {
46 pinctrl-names = "default";
47 pinctrl-0 = <&i2c_pins>;
48 status = "okay";
49};
50
51&watchdog {
52 status = "okay";
53};
54
55&eth {
56 status = "okay";
57
58 gmac0: mac@0 {
59 compatible = "mediatek,eth-mac";
60 reg = <0>;
61 phy-mode = "2500base-x";
62
63 fixed-link {
64 speed = <2500>;
65 full-duplex;
66 pause;
67 };
68 };
69
70 gmac1: mac@1 {
71 compatible = "mediatek,eth-mac";
72 reg = <1>;
73 phy-mode = "2500base-x";
74
75 fixed-link {
76 speed = <2500>;
77 full-duplex;
78 pause;
79 };
80 };
81
82 mdio: mdio-bus {
83 #address-cells = <1>;
84 #size-cells = <0>;
85
86 phy5: phy@5 {
87 compatible = "ethernet-phy-id67c9.de0a";
88 reg = <5>;
89 reset-gpios = <&pio 6 1>;
90 reset-deassert-us = <20000>;
91 phy-mode = "2500base-x";
92 };
93
94 phy6: phy@6 {
95 compatible = "ethernet-phy-id67c9.de0a";
96 reg = <6>;
97 phy-mode = "2500base-x";
98 };
99
100 switch@0 {
101 compatible = "mediatek,mt7531";
102 reg = <31>;
103 reset-gpios = <&pio 5 0>;
104
105 ports {
106 #address-cells = <1>;
107 #size-cells = <0>;
108
109 port@0 {
110 reg = <0>;
111 label = "lan0";
112 };
113
114 port@1 {
115 reg = <1>;
116 label = "lan1";
117 };
118
119 port@2 {
120 reg = <2>;
121 label = "lan2";
122 };
123
124 port@3 {
125 reg = <3>;
126 label = "lan3";
127 };
128
129 port@6 {
130 reg = <6>;
131 label = "cpu";
132 ethernet = <&gmac0>;
133 phy-mode = "2500base-x";
134
135 fixed-link {
136 speed = <2500>;
137 full-duplex;
138 pause;
139 };
140 };
141 };
142 };
143 };
144};
145
146&hnat {
147 mtketh-wan = "eth1";
148 mtketh-lan = "lan";
149 mtketh-max-gmac = <2>;
150 status = "okay";
151};
152
153/* Warning: pins shared with &uart2 */
154&spi1 {
155 pinctrl-names = "default";
156 pinctrl-0 = <&spic_pins>;
157 status = "okay";
158};
159
160&mmc0 {
161 pinctrl-names = "default", "state_uhs";
162 pinctrl-0 = <&mmc0_pins_default>;
163 pinctrl-1 = <&mmc0_pins_uhs>;
164 bus-width = <8>;
developerf77870c2021-12-14 14:39:02 +0800165 max-frequency = <52000000>;
developer565bacb2021-09-28 21:26:32 +0800166 cap-mmc-highspeed;
167 vmmc-supply = <&reg_3p3v>;
168 vqmmc-supply = <&reg_3p3v>;
169 non-removable;
developerf77870c2021-12-14 14:39:02 +0800170 no-sd;
171 no-sdio;
developer565bacb2021-09-28 21:26:32 +0800172 status = "okay";
173};
174
175&wbsys {
176 status = "okay";
177};
178
179&pio {
180 mmc0_pins_default: mmc0-pins-22-to-32-default {
181 mux {
182 function = "flash";
183 groups = "emmc_45";
184 };
185 conf-cmd-dat {
186 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
187 "SPI0_CS", "SPI0_HOLD", "SPI0_WP",
188 "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
189 input-enable;
190 drive-strength = <MTK_DRIVE_4mA>;
191 mediatek,pull-up-adv = <1>; /* pull-up 10K */
192 };
193 conf-clk {
194 pins = "SPI1_CS";
195 drive-strength = <MTK_DRIVE_6mA>;
196 mediatek,pull-down-adv = <2>; /* pull-down 50K */
197 };
198 conf-rst {
199 pins = "PWM1";
200 drive-strength = <MTK_DRIVE_4mA>;
201 mediatek,pull-up-adv = <1>; /* pull-up 10K */
202 };
203 };
204
205 mmc0_pins_uhs: mmc0-pins-22-to-32-uhs {
206 mux {
207 function = "flash";
208 groups = "emmc_45";
209 };
210 conf-cmd-dat {
211 pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
212 "SPI0_CS", "SPI0_HOLD", "SPI0_WP",
213 "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
214 input-enable;
215 drive-strength = <MTK_DRIVE_4mA>;
216 mediatek,pull-up-adv = <1>; /* pull-up 10K */
217 };
218 conf-clk {
219 pins = "SPI1_CS";
220 drive-strength = <MTK_DRIVE_6mA>;
221 mediatek,pull-down-adv = <2>; /* pull-down 50K */
222 };
223 conf-rst {
224 pins = "PWM1";
225 drive-strength = <MTK_DRIVE_4mA>;
226 mediatek,pull-up-adv = <1>; /* pull-up 10K */
227 };
228 };
229};