[][kernel][mt7988][eth][phy: mediatek-2p5ge: Fix LED0/LED1 polarity]
[Description]
Fix LED0/LED1 polarity:
1. Don't use "default" pinctrl-name or pinctrl driver will get and select
it before phy driver sets correct LED polarity.
2. Now, LED0 is on when internal 2.5Gphy links up @ 10/100/1000/2500 Mbps.
LED1 is on when internal 2.5Gphy links up with FDX/HDX.
3. Setup LED after FW is loaded and triggered. So remove probe().
Without this patch, internal 2.5Gphy's LED may blink unexpectedly.
[Release-log]
N/A
Change-Id: I09bfc2d517d1773566bb1f171cf8595a408db6cc
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7500812
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-i2p5g-spim-nand.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-i2p5g-spim-nand.dts
index 3f88986..ebc7846 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-i2p5g-spim-nand.dts
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988a-dsa-i2p5g-spim-nand.dts
@@ -253,7 +253,7 @@
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@0 {
- pinctrl-names = "default";
+ pinctrl-names = "i2p5gbe-led";
pinctrl-0 = <&i2p5gbe_led0_pins>;
reg = <15>;
compatible = "ethernet-phy-ieee802.3-c45";
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-emmc.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-emmc.dts
index 0e58ac7..4f59883 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-emmc.dts
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-emmc.dts
@@ -239,7 +239,7 @@
clock-frequency = <10500000>;
phy0: ethernet-phy@0 {
- pinctrl-names = "default";
+ pinctrl-names = "i2p5gbe-led";
pinctrl-0 = <&i2p5gbe_led0_pins>;
reg = <15>;
compatible = "ethernet-phy-ieee802.3-c45";
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-sd.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-sd.dts
index d0b4ec3..f102b4a 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-sd.dts
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-sd.dts
@@ -230,7 +230,7 @@
clock-frequency = <10500000>;
phy0: ethernet-phy@0 {
- pinctrl-names = "default";
+ pinctrl-names = "i2p5gbe-led";
pinctrl-0 = <&i2p5gbe_led0_pins>;
reg = <15>;
compatible = "ethernet-phy-ieee802.3-c45";
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-snfi-nand.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-snfi-nand.dts
index 6cadcfc..b5f0cc4 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-snfi-nand.dts
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-snfi-nand.dts
@@ -265,7 +265,7 @@
clock-frequency = <10500000>;
phy0: ethernet-phy@0 {
- pinctrl-names = "default";
+ pinctrl-names = "i2p5gbe-led";
pinctrl-0 = <&i2p5gbe_led0_pins>;
reg = <15>;
compatible = "ethernet-phy-ieee802.3-c45";
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-spim-nand.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-spim-nand.dts
index 564debe..5e21726 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-spim-nand.dts
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-spim-nand.dts
@@ -405,7 +405,7 @@
clock-frequency = <10500000>;
phy0: ethernet-phy@0 {
- pinctrl-names = "default";
+ pinctrl-names = "i2p5gbe-led";
pinctrl-0 = <&i2p5gbe_led0_pins>;
reg = <15>;
compatible = "ethernet-phy-ieee802.3-c45";
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-spim-nor.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-spim-nor.dts
index 1c98664..a5d21f2 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-spim-nor.dts
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-10g-spim-nor.dts
@@ -257,7 +257,7 @@
clock-frequency = <10500000>;
phy0: ethernet-phy@0 {
- pinctrl-names = "default";
+ pinctrl-names = "i2p5gbe-led";
pinctrl-0 = <&i2p5gbe_led0_pins>;
reg = <15>;
compatible = "ethernet-phy-ieee802.3-c45";
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-e2p5g-spim-nand.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-e2p5g-spim-nand.dts
index e6a0115..84cc355 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-e2p5g-spim-nand.dts
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-dsa-e2p5g-spim-nand.dts
@@ -335,7 +335,7 @@
#size-cells = <0>;
phy0: ethernet-phy@0 {
- pinctrl-names = "default";
+ pinctrl-names = "i2p5gbe-led";
pinctrl-0 = <&i2p5gbe_led0_pins>;
reg = <15>;
compatible = "ethernet-phy-ieee802.3-c45";
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-gsw-10g-sfp-spim-nand.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-gsw-10g-sfp-spim-nand.dts
index 2404586..6c31fb8 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-gsw-10g-sfp-spim-nand.dts
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-gsw-10g-sfp-spim-nand.dts
@@ -350,7 +350,7 @@
#size-cells = <0>;
phy0: ethernet-phy@0 {
- pinctrl-names = "default";
+ pinctrl-names = "i2p5gbe-led";
pinctrl-0 = <&i2p5gbe_led0_pins>;
reg = <15>;
compatible = "ethernet-phy-ieee802.3-c45";
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-gsw-10g-spim-nand.dts b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-gsw-10g-spim-nand.dts
index 3446b6b..81ac5bc 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-gsw-10g-spim-nand.dts
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988c-gsw-10g-spim-nand.dts
@@ -381,7 +381,7 @@
clock-frequency = <10500000>;
phy0: ethernet-phy@0 {
- pinctrl-names = "default";
+ pinctrl-names = "i2p5gbe-led";
pinctrl-0 = <&i2p5gbe_led0_pins>;
reg = <15>;
compatible = "ethernet-phy-ieee802.3-c45";
diff --git a/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-2p5ge.c b/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-2p5ge.c
index 32ae8ea..2825a36 100644
--- a/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-2p5ge.c
+++ b/target/linux/mediatek/files-5.4/drivers/net/phy/mediatek-2p5ge.c
@@ -28,8 +28,17 @@
/* Registers on MDIO_MMD_VEND2 */
#define MTK_PHY_LED0_ON_CTRL (0x24)
+#define MTK_PHY_LED0_ON_LINK1000 BIT(0)
+#define MTK_PHY_LED0_ON_LINK100 BIT(1)
+#define MTK_PHY_LED0_ON_LINK10 BIT(2)
+#define MTK_PHY_LED0_ON_LINK2500 BIT(7)
#define MTK_PHY_LED0_POLARITY BIT(14)
+#define MTK_PHY_LED1_ON_CTRL (0x26)
+#define MTK_PHY_LED1_ON_FDX BIT(4)
+#define MTK_PHY_LED1_ON_HDX BIT(5)
+#define MTK_PHY_LED1_POLARITY BIT(14)
+
enum {
PHY_AUX_SPD_10 = 0,
PHY_AUX_SPD_100,
@@ -37,22 +46,6 @@
PHY_AUX_SPD_2500,
};
-static int mt798x_2p5ge_phy_probe(struct phy_device *phydev)
-{
- struct pinctrl *pinctrl;
-
- phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
- MTK_PHY_LED0_POLARITY);
-
- pinctrl = devm_pinctrl_get_select_default(&phydev->mdio.dev);
- if (IS_ERR(pinctrl)) {
- dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n");
- return PTR_ERR(pinctrl);
- }
-
- return 0;
-}
-
static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev)
{
int ret;
@@ -64,6 +57,8 @@
void __iomem *pmb_addr;
void __iomem *mcucsr_base;
u16 reg;
+ struct pinctrl *pinctrl;
+
np = of_find_compatible_node(NULL, NULL, "mediatek,2p5gphy-fw");
if (!np)
@@ -103,6 +98,20 @@
writew(reg | MD32_EN, mcucsr_base + MD32_EN_CFG);
dev_info(dev, "Firmware loading/trigger ok.\n");
+ /* Setup LED */
+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
+ MTK_PHY_LED0_POLARITY | MTK_PHY_LED0_ON_LINK10 |
+ MTK_PHY_LED0_ON_LINK100 | MTK_PHY_LED0_ON_LINK1000 |
+ MTK_PHY_LED0_ON_LINK2500);
+ phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
+ MTK_PHY_LED1_ON_FDX | MTK_PHY_LED1_ON_HDX);
+
+ pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led");
+ if (IS_ERR(pinctrl)) {
+ dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n");
+ return PTR_ERR(pinctrl);
+ }
+
return 0;
}
@@ -221,7 +230,6 @@
{
PHY_ID_MATCH_EXACT(0x00339c11),
.name = "MediaTek MT798x 2.5GbE PHY",
- .probe = mt798x_2p5ge_phy_probe,
.config_init = mt798x_2p5ge_phy_config_init,
.config_aneg = mt798x_2p5ge_phy_config_aneg,
.get_features = mt798x_2p5ge_phy_get_features,