[][openwrt][mt7988][eth][Add HW version check for MT7988]
[Description]
Add hardware version check for MT7988.
If the hardware that we're using is MT7988 v2,
it can support dummy page feature, which is
going to be enabled by default.
If without this patch, MT7988 cannot enable dummy page.
[Release-log]
N/A
Change-Id: Ic34d16ccd117adf6f0be1444721d23e9a1b7fb25
Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/7420053
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi
index c9da613..28cb8eb 100644
--- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi
+++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7988.dtsi
@@ -127,6 +127,11 @@
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
};
+ hwver: hwver {
+ compatible = "mediatek,hwver", "syscon";
+ reg = <0 0x8000000 0 0x1000>;
+ };
+
thermal-zones {
cpu_thermal: cpu-thermal {
polling-delay-passive = <1000>;
@@ -841,6 +846,7 @@
mediatek,xfi_pll = <&xfi_pll>;
mediatek,infracfg = <&topmisc>;
mediatek,toprgu = <&watchdog>;
+ mediatek,hwver = <&hwver>;
#reset-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 05a5595..55307ff 100755
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -500,6 +500,34 @@
mtk_w32(eth, mcr, MTK_MAC_MCR(mac->id));
}
+static int mtk_get_hwver(struct mtk_eth *eth)
+{
+ struct device_node *np;
+ struct regmap *hwver;
+ u32 info = 0;
+
+ eth->hwver = MTK_HWID_V1;
+
+ np = of_parse_phandle(eth->dev->of_node, "mediatek,hwver", 0);
+ if (!np)
+ return -EINVAL;
+
+ hwver = syscon_node_to_regmap(np);
+ if (IS_ERR(hwver))
+ return PTR_ERR(hwver);
+
+ regmap_read(hwver, 0x8, &info);
+
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3))
+ eth->hwver = FIELD_GET(HWVER_BIT_NETSYS_3, info);
+ else
+ eth->hwver = FIELD_GET(HWVER_BIT_NETSYS_1_2, info);
+
+ of_node_put(np);
+
+ return 0;
+}
+
static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
phy_interface_t interface)
{
@@ -3744,6 +3772,12 @@
MTK_FE_INT_RFIFO_OV | MTK_FE_INT_RFIFO_UF, MTK_FE_INT_ENABLE);
if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V3)) {
+ /* PSE dummy page mechanism */
+ if (eth->soc->caps != MT7988_CAPS || eth->hwver != MTK_HWID_V1)
+ mtk_w32(eth, PSE_DUMMY_WORK_GDM(1) |
+ PSE_DUMMY_WORK_GDM(2) | PSE_DUMMY_WORK_GDM(3) |
+ DUMMY_PAGE_THR, PSE_DUMY_REQ);
+
/* PSE should not drop port1, port8 and port9 packets */
mtk_w32(eth, 0x00000302, PSE_NO_DROP_CFG);
@@ -4568,6 +4602,8 @@
eth->phy_scratch_ring = res->start + MTK_ETH_SRAM_OFFSET;
}
+ mtk_get_hwver(eth);
+
if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
eth->ip_align = NET_IP_ALIGN;
diff --git a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index 03c18f0..2082ec6 100755
--- a/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/target/linux/mediatek/files-5.4/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -761,6 +761,10 @@
#define GPIO_BIAS_CTRL 0xed0
#define GPIO_DRV_SEL10 0xf00
+/* SoC hardware version register */
+#define HWVER_BIT_NETSYS_1_2 BIT(0)
+#define HWVER_BIT_NETSYS_3 BIT(8)
+
/* ethernet subsystem chip id register */
#define ETHSYS_CHIPID0_3 0x0
#define ETHSYS_CHIPID4_7 0x4
@@ -1230,6 +1234,12 @@
MTK_GDM_TYPE_MAX
};
+enum mtk_hw_id {
+ MTK_HWID_V1 = 0,
+ MTK_HWID_V2,
+ MTK_HWID_MAX
+};
+
static inline const char *gdm_type(int type)
{
switch (type) {
@@ -1758,6 +1768,7 @@
struct net_device *netdev[MTK_MAX_DEVS];
struct mtk_mac *mac[MTK_MAX_DEVS];
int irq[MTK_MAX_IRQ_NUM];
+ u8 hwver;
u32 msg_enable;
unsigned long sysclk;
struct regmap *ethsys;