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git01.mediatek.com / filogic / uboot / f872d4767f756ca34cc9bce93932f20619528708 / drivers / clk
  1. f872d47 drivers: clk: sifive: fu740-prci: replace 'pciaux' with 'pcieaux' by Green Wan · Mon Jun 28 19:13:08 2021 +0800
  2. 08b3fd6 Merge tag 'xilinx-for-v2021.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next by Tom Rini · Thu Jul 01 08:57:23 2021 -0400
  3. 159b60e Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-sh into next by Tom Rini · Mon Jun 28 18:32:07 2021 -0400
  4. d3e8b73 Merge tag 'v2021.07-rc5' into next by Tom Rini · Mon Jun 28 16:22:13 2021 -0400
  5. 86d59f3 clk: renesas: Add R8A779A0 clock tables by Hai Pham · Tue Aug 11 10:46:34 2020 +0700
  6. 0fbb8a7 clk: renesas: Handle R8A779A0 V3U clock types in Gen3 clock code by Marek Vasut · Tue Apr 27 19:52:53 2021 +0200
  7. 39df053 clk: zynq: Add clock wizard driver by Zhengxun · Fri Jun 11 15:10:48 2021 +0000
  8. ce92768 Merge tag 'u-boot-rockchip-20210618' of https://source.denx.de/u-boot/custodians/u-boot-rockchip into next by Tom Rini · Sat Jun 19 08:20:12 2021 -0400
  9. b9c3214 clk: cosmetic change in uclass by Patrick Delaunay · Tue Apr 27 10:57:54 2021 +0200
  10. 5be90bb rockchip: rk3568: add clock driver by Elaine Zhang · Wed Jun 02 11:39:24 2021 +0800
  11. 152919d clk: k210: Move k210 clock out of its own subdirectory by Sean Anderson · Fri Jun 11 00:16:14 2021 -0400
  12. 16d64cd clk: k210: Remove bypass driver by Sean Anderson · Fri Jun 11 00:16:13 2021 -0400
  13. 1a37182 clk: k210: Don't set PLL rates if we are already at the correct rate by Sean Anderson · Fri Jun 11 00:16:12 2021 -0400
  14. 3a29bc6 clk: k210: Re-add support for setting rate by Sean Anderson · Fri Jun 11 00:16:11 2021 -0400
  15. ecf9284 clk: k210: Implement soc_clk_dump by Sean Anderson · Fri Jun 11 00:16:10 2021 -0400
  16. edbe849 clk: k210: Move pll into the rest of the driver by Sean Anderson · Fri Jun 11 00:16:09 2021 -0400
  17. 2957313 clk: k210: Rewrite to remove CCF by Sean Anderson · Fri Jun 11 00:16:08 2021 -0400
  18. 08d531c clk: Allow force setting clock defaults before relocation by Sean Anderson · Fri Jun 11 00:16:07 2021 -0400
  19. 82ceb0d clk: add support for TI K3 SoC clocks by Tero Kristo · Fri Jun 11 11:45:14 2021 +0300
  20. 81744b7 clk: add support for TI K3 SoC PLL by Tero Kristo · Fri Jun 11 11:45:13 2021 +0300
  21. 9ab78c1 clk: fix set_rate to clean up cached rates for the hierarchy by Tero Kristo · Fri Jun 11 11:45:12 2021 +0300
  22. d41b2b3 clk: fix assigned-clocks to pass with deferring provider by Tero Kristo · Fri Jun 11 11:45:11 2021 +0300
  23. 1770884 clk: sci-clk: fix return value of set_rate by Tero Kristo · Fri Jun 11 11:45:10 2021 +0300
  24. f04dfff clk: do not attempt to fetch clock pointer with null device by Tero Kristo · Fri Jun 11 11:45:08 2021 +0300
  25. de4ef9b clk: fixed_rate: add API for directly registering fixed rate clocks by Tero Kristo · Fri Jun 11 11:45:06 2021 +0300
  26. d08f867 clk: imx: clk-imxrt1050: introduce IMXRT1050_CLK_USBOH3 by Giulio Benetti · Thu May 20 16:10:14 2021 +0200
  27. 71d1ee4 clk: imx: clk-imxrt1050: introduce LCDIF_PIX and rename LCDIF to LCDIF_APB by Giulio Benetti · Thu May 13 12:19:33 2021 +0200
  28. ecefa5f drivers: clk: add fu740 support by Green Wan · Thu May 27 06:52:08 2021 -0700
  29. 4bebdd3 treewide: Convert macro and uses of __section(foo) to __section("foo") by Marek Behún · Thu May 20 13:23:52 2021 +0200
  30. 8f56786 clk: renesas: Deduplicate gen3_clk_get_rate64() PLL handling by Marek Vasut · Tue Apr 27 19:36:39 2021 +0200
  31. 9480346 clk: renesas: Add register pointers into struct cpg_mssr_info by Hai Pham · Thu Nov 05 22:30:37 2020 +0700
  32. 016a4c2 clk: renesas: Introduce enum clk_reg_layout by Hai Pham · Thu Nov 05 21:32:38 2020 +0700
  33. 5460ee0 clk: renesas: Pass struct cpg_mssr_info to renesas_clk_endisable() by Hai Pham · Fri May 22 10:39:04 2020 +0700
  34. 814217e clk: renesas: Make reset controller modemr register offset configurable by Marek Vasut · Sun Apr 25 21:53:05 2021 +0200
  35. 215de2b clk: renesas: Add support for RPCD2 clock by Hai Pham · Tue Aug 11 10:25:28 2020 +0700
  36. 1a61896 clk: renesas: Fix Realtime Module Stop Control Register offsets by Hai Pham · Tue May 19 17:42:05 2020 +0700
  37. f2279df clk: renesas: Fix incorrect return RPC clk_get_rate by Hai Pham · Sat Dec 05 09:35:40 2020 +0700
  38. f5fec9d clk: renesas: Reinstate RPC clock on R-Car D3/E3 by Marek Vasut · Sun Apr 25 21:26:22 2021 +0200
  39. 0e8dcb7 clk: renesas: Synchronize R-Car Gen3 tables with Linux 5.12 by Marek Vasut · Sun Apr 25 21:10:40 2021 +0200
  40. aac4de2 clk: renesas: Synchronize R-Car Gen2 tables with Linux 5.12 by Marek Vasut · Sun Apr 25 21:09:10 2021 +0200
  41. 8538d53 clk: renesas: Synchronize RZ/G2 tables with Linux 5.12 by Marek Vasut · Sun Apr 25 21:08:18 2021 +0200
  42. 8aa82e1 clk: Add support for the k210 clock driver pre-relocation by Sean Anderson · Thu Apr 08 22:13:08 2021 -0400
  43. 95d2724 clk: k210: Move the clint clock to under aclk by Sean Anderson · Thu Apr 08 22:13:07 2021 -0400
  44. afab998 clk: k210: Remove k210_register_pll by Sean Anderson · Thu Apr 08 22:13:06 2021 -0400
  45. 16e5c17 clk: k210: Fix PLL enable always getting taken by Sean Anderson · Thu Apr 08 22:13:05 2021 -0400
  46. e649ff3 clk: k210: Fix PLLs not being enabled by Sean Anderson · Thu Apr 08 22:13:04 2021 -0400
  47. d7ac373 clk: Warn on failure to assign rate by Sean Anderson · Thu Apr 08 22:13:03 2021 -0400
  48. eff80eb clk: ti: am3-dpll: use custom API for memory access by Dario Binacchi · Sat May 01 17:05:25 2021 +0200
  49. 3693460 clk: ti: gate: use custom API for memory access by Dario Binacchi · Sat May 01 17:05:24 2021 +0200
  50. ac7c705 clk: ti: change clk_ti_latch() signature by Dario Binacchi · Sat May 01 17:05:23 2021 +0200
  51. 6dfe426 clk: ti: add custom API for memory access by Dario Binacchi · Sat May 01 17:05:22 2021 +0200
  52. a738b53 Merge tag 'xilinx-for-v2021.07-rc2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze by Tom Rini · Thu Apr 29 11:31:06 2021 -0400
  53. 5af8b6a clk: renesas: Synchronize Gen2 MSTP teardown tables by Marek Vasut · Sat Jun 06 15:26:14 2020 +0200
  54. 22f9fc7 clk: renesas: Only ever access documented bits in clock driver teardown by Marek Vasut · Sat Apr 25 14:57:45 2020 +0200
  55. 8ce9043 clk: Fix typo in Zynq Kconfig symbol description by Michal Simek · Wed Apr 07 14:36:14 2021 +0200
  56. e275751 clk: meson-g12a: add PCIe gates by Neil Armstrong · Thu Feb 25 18:46:12 2021 +0100
  57. d73b8a5 clk: sunxi: h6: Add XHCI clocks by Samuel Holland · Sun Feb 07 23:57:20 2021 -0600
  58. 5861030 clk: sunxi: Add a dummy clock driver for the RTC by Samuel Holland · Sun Feb 07 23:57:19 2021 -0600
  59. 3ff5d69 clk: mpfs_clk: Enable DM_FLAG_PRE_RELOC flag by Bin Meng · Wed Mar 31 15:24:49 2021 +0800
  60. 46e5f61 clk: Return -ENOSYS when system call is not available by Simon Glass · Thu Mar 25 10:26:09 2021 +1300
  61. 29ff16a clk: Update drivers to use -EINVAL by Simon Glass · Thu Mar 25 10:26:08 2021 +1300
  62. 86676e0 Merge tag 'xilinx-for-v2021.07' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next by Tom Rini · Wed Mar 31 09:47:30 2021 -0400
  63. 97ab47d clk: zynqmp: Fix clk dump values by T Karthik Reddy · Wed Feb 24 23:44:46 2021 -0700
  64. 0000e0d dm: Rename device_get_by_driver_info_idx() by Simon Glass · Mon Mar 15 17:25:28 2021 +1300
  65. 9bb88fb clk: sandbox: Create a special fixed-rate driver by Simon Glass · Mon Mar 15 17:25:24 2021 +1300
  66. b95c7b9 clk: fixed-rate: Export driver parts for OF_PLATDATA_INST by Simon Glass · Mon Mar 15 17:25:23 2021 +1300
  67. 96d5736 clk: sandbox: Move priv/plat data to a header file by Simon Glass · Mon Mar 15 17:25:22 2021 +1300
  68. 55a7814 clk: stm32mp1: gets root clocks from fdt by Etienne Carriere · Wed Feb 24 11:19:42 2021 +0100
  69. df070ce Merge tag 'xilinx-for-v2021.04-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze by Tom Rini · Tue Feb 23 10:45:55 2021 -0500
  70. 277300f clk: versal: Add support to enable clocks by T Karthik Reddy · Wed Feb 03 03:10:47 2021 -0700
  71. 2aa360e clk: zynqmp: Add support to enable clocks by T Karthik Reddy · Wed Feb 03 03:10:45 2021 -0700
  72. 4171095 clk: zynq: Add dummy clock enable function by Michal Simek · Tue Feb 09 15:28:15 2021 +0100
  73. 9fcb0d7 clk: ti: improve debug messages for clkctrl driver by Dario Binacchi · Sat Feb 13 12:02:30 2021 +0100
  74. b1db71b Merge branch '2021-02-02-drop-asm_global_data-when-unused' by Tom Rini · Mon Feb 15 08:19:40 2021 -0500
  75. 9589167 clk: at91: compat: partially revert "dm: Remove uses of device_bind_offset()" by Eugen Hristev · Tue Feb 02 10:47:58 2021 +0200
  76. 5c0ea51 clk: stm32mp1: add support of I2C6_K by Patrick Delaunay · Fri Jan 22 15:34:25 2021 +0100
  77. 3ba929a common: Drop asm/global_data.h from common header by Simon Glass · Fri Oct 30 21:38:53 2020 -0600
  78. 6646c57 clk: x86: Correct the driver name by Simon Glass · Thu Jan 21 13:57:12 2021 -0700
  79. f73f581 clk: Add debugging for return values by Simon Glass · Thu Jan 21 13:57:11 2021 -0700
  80. d719a4d Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi by Tom Rini · Mon Jan 25 19:46:02 2021 -0500
  81. e52dc3e clk: sunxi: Add support for H616 clocks by Jernej Skrabec · Mon Jan 11 21:11:52 2021 +0100
  82. 7bf38bc Merge tag 'mips-pull-2021-01-24' of https://gitlab.denx.de/u-boot/custodians/u-boot-mips by Tom Rini · Mon Jan 25 14:38:40 2021 -0500
  83. f4d0d2b clk: add clock driver for MediaTek MT7620 SoC by developer · Thu Nov 12 16:36:10 2020 +0800
  84. b1a8bb0 clk: imx: Add ECSPI to iMX8MN by Marek Vasut · Tue Jan 19 00:58:31 2021 +0100
  85. ce5ecc1 clk: aspeed: Add AST2600 clock support by Ryan Chen · Mon Dec 14 13:54:23 2020 +0800
  86. 4b1c515 clk: mediatek: Add MT8183 clock driver by Fabien Parent · Sat Oct 17 12:52:15 2020 +0200
  87. 0c4ae80 clk: Add Microchip PolarFire SoC clock driver by Padmarao Begari · Fri Jan 15 08:20:38 2021 +0530
  88. f686e4d dm: fix build errors generated by last merges by Dario Binacchi · Fri Jan 15 09:10:26 2021 +0100
  89. 0f075f8 Merge tag 'u-boot-stm32-20210113' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm by Tom Rini · Wed Jan 13 15:00:53 2021 -0500
  90. 0542b01 Merge tag 'u-boot-amlogic-20210112' of https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic by Tom Rini · Tue Jan 12 15:46:52 2021 -0500
  91. 88c7eb7 clk: clk_stm32h7: migrate trace to dev and log macro by Patrick Delaunay · Fri Nov 06 19:01:47 2020 +0100
  92. a57b8cd clk: clk_stm32f: migrate trace to dev and log macro by Patrick Delaunay · Fri Nov 06 19:01:46 2020 +0100
  93. 30cd91e clk: stm32mp1: migrate trace to dev and log macro by Patrick Delaunay · Fri Nov 06 19:01:45 2020 +0100
  94. d4352b8 clk: move clk-ti-sci driver to 'ti' directory by Dario Binacchi · Wed Dec 30 00:16:20 2020 +0100
  95. 4707e38 clk: ti: omap4: add clock manager driver by Dario Binacchi · Wed Dec 30 00:16:18 2020 +0100
  96. 59ea184 clk: ti: add support for clkctrl clocks by Dario Binacchi · Wed Dec 30 00:06:39 2020 +0100
  97. b96e897 clk: ti: add gate clock driver by Dario Binacchi · Wed Dec 30 00:06:36 2020 +0100
  98. d284157 clk: ti: add divider clock driver by Dario Binacchi · Wed Dec 30 00:06:35 2020 +0100
  99. 6e6eb8b clk: ti: am33xx: add DPLL clock drivers by Dario Binacchi · Wed Dec 30 00:06:34 2020 +0100
  100. da3b020 clk: ti: add mux clock driver by Dario Binacchi · Wed Dec 30 00:06:32 2020 +0100