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git01.mediatek.com / filogic / uboot / f19e0e57252a9dd2c4b7fa994b6ea1b25c8c6776 / arch / riscv / include
  1. f4b4d75 riscv: provide missing base extension functions by Heinrich Schuchardt · Thu Mar 17 07:36:14 2022 +0100
  2. 295e1ce cmd: sbi: add Performance Monitoring Unit Extension by Heinrich Schuchardt · Wed Mar 16 21:21:18 2022 +0100
  3. fc55736 event: Convert arch_cpu_init_dm() to use events by Simon Glass · Fri Mar 04 08:43:05 2022 -0700
  4. 47b4c02 doc: replace @return by Return: by Heinrich Schuchardt · Wed Jan 19 18:05:50 2022 +0100
  5. 2f5b807 riscv: add #define in asm/io.h for some device drivers by Wei Fu · Sun Oct 24 00:31:12 2021 +0800
  6. 69c681e riscv: function to retrieve SBI implementation version by Heinrich Schuchardt · Mon Oct 25 15:09:34 2021 +0200
  7. 579f12b riscv: Avoid io read/write cause wrong result by Nick Hu · Mon Oct 18 11:50:05 2021 +0800
  8. cc382ff sysreset: provide SBI based sysreset driver by Heinrich Schuchardt · Sun Sep 12 21:11:46 2021 +0200
  9. 2d1c651 riscv: add missing SBI extension definitions by Heinrich Schuchardt · Sun Sep 12 21:11:44 2021 +0200
  10. b28d6b9 riscv: lib: modify the indent by Zong Li · Wed Sep 01 15:01:43 2021 +0800
  11. ec34849 board: sifive: use ccache driver instead of helper function by Zong Li · Wed Sep 01 15:01:42 2021 +0800
  12. dab3e8e board: sifive: Add an interface to get PCB revision by Zong Li · Wed Jun 30 23:23:48 2021 +0800
  13. 7f33743 riscv: cpu: fu740: Add support for cpu fu740 by Green Wan · Thu May 27 06:52:07 2021 -0700
  14. 614b1d8 riscv: Split SiFive CLINT support between SPL and U-Boot proper by Bin Meng · Tue May 11 20:04:12 2021 +0800
  15. d62063d lmb: move CONFIG_LMB in Kconfig by Patrick Delaunay · Wed Mar 10 10:16:25 2021 +0100
  16. 23caf66 riscv: assembler versions of memcpy, memmove, memset by Heinrich Schuchardt · Sat Mar 27 12:37:04 2021 +0100
  17. 440b77f riscv: Change phys_addr_t and phys_size_t to 64-bit by Bin Meng · Sun Jan 31 20:36:04 2021 +0800
  18. a235d43 riscv: Add DMA 64-bit address support by Padmarao Begari · Fri Jan 15 08:20:35 2021 +0530
  19. b75b15b dm: treewide: Rename ..._platdata variables to just ..._plat by Simon Glass · Thu Dec 03 16:55:23 2020 -0700
  20. ff184fe riscv: Use a valid bit to ignore already-pending IPIs by Sean Anderson · Mon Sep 21 07:51:37 2020 -0400
  21. 87e6ce5 riscv: Rework Andes PLMT as a UCLASS_TIMER driver by Sean Anderson · Mon Sep 28 10:52:24 2020 -0400
  22. 6e7eb46 riscv: define function set_gd() by Heinrich Schuchardt · Thu Sep 10 07:47:39 2020 +0200
  23. 95492ae cmd: provide command sbi by Heinrich Schuchardt · Thu Aug 20 19:43:39 2020 +0200
  24. 2b2d9c4 riscv: sifive/fu540: spl: Rename soc_spl_init() by Bin Meng · Sun Aug 02 23:09:03 2020 -0700
  25. 63dcfcb riscv: Call spl_board_init_f() in the generic SPL board_init_f() by Bin Meng · Sun Aug 02 23:09:01 2020 -0700
  26. e1ff6eb sifive: reset: add DM based reset driver for SiFive SoC's by Sagar Shrikant Kadam · Wed Jul 29 02:36:13 2020 -0700
  27. 90fa4e9 Merge branch 'next' by Tom Rini · Mon Jul 06 15:46:38 2020 -0400
  28. 8a52128 riscv: sifive: fu540: enable all cache ways from U-Boot proper by Pragnesh Patel · Fri May 29 12:14:51 2020 +0530
  29. 7f4b666 riscv: Add option to support RISC-V privileged spec 1.9 by Sean Anderson · Wed Jun 24 06:41:19 2020 -0400
  30. b1d0cb3 riscv: Clean up IPI initialization code by Sean Anderson · Wed Jun 24 06:41:18 2020 -0400
  31. 5aa0074 riscv: Add headers for asm/global_data.h by Sean Anderson · Wed Jun 24 06:41:16 2020 -0400
  32. 0961ae8 bdinfo: riscv: Use generic bd_info by Simon Glass · Sun May 10 14:16:26 2020 -0600
  33. b391ead riscv: sbi: Remove sbi_spec_version by Bin Meng · Wed May 27 02:04:52 2020 -0700
  34. e00653c riscv: sifive: fu540: add SPL configuration by Pragnesh Patel · Fri May 29 11:33:35 2020 +0530
  35. 25269c0 riscv: cpu: fu540: Add support for cpu fu540 by Pragnesh Patel · Fri May 29 11:33:34 2020 +0530
  36. a7edd07 riscv: Move all SMP related SBI calls to SBI_v01 by Atish Patra · Tue Apr 21 14:51:57 2020 -0700
  37. 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · Sun May 10 11:40:13 2020 -0600
  38. 111b804 riscv: Provide a mechanism to fix DT for reserved memory by Atish Patra · Tue Apr 21 11:15:01 2020 -0700
  39. b161f90 riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL by Bin Meng · Thu Apr 16 08:09:30 2020 -0700
  40. f7e6d33 riscv: Implement new SBI v0.2 extensions by Bin Meng · Mon Mar 09 19:35:31 2020 -0700
  41. 887d809 riscv: Introduce a new config for SBI v0.1 by Bin Meng · Mon Mar 09 19:35:30 2020 -0700
  42. c20421b riscv: Add SBI v0.2 extension definitions by Bin Meng · Mon Mar 09 19:35:29 2020 -0700
  43. ee3bcd0 riscv: Add basic support for SBI v0.2 by Bin Meng · Mon Mar 09 19:35:28 2020 -0700
  44. 9da11d1 riscv: Mark existing SBI as v0.1 SBI by Bin Meng · Mon Mar 09 19:35:27 2020 -0700
  45. ad76cd4 riscv: Fix sbi_remote_sfence_vma{,_asid} by Bin Meng · Fri Mar 06 00:44:16 2020 -0800
  46. 6373a17 dma-mapping: move dma_map_(un)single() to <linux/dma-mapping.h> by Masahiro Yamada · Fri Feb 14 16:40:19 2020 +0900
  47. 05a5dba dma-mapping: fix the prototype of dma_unmap_single() by Masahiro Yamada · Fri Feb 14 16:40:18 2020 +0900
  48. 7167d67 dma-mapping: fix the prototype of dma_map_single() by Masahiro Yamada · Fri Feb 14 16:40:17 2020 +0900
  49. 4a81a21 asm: dma-mapping.h: Fix dma mapping functions by Vignesh Raghavendra · Thu Jan 16 14:23:45 2020 +0530
  50. c308e01 riscv: add option to wait for ack from secondary harts in smp functions by Lukas Auer · Sun Dec 08 23:28:51 2019 +0100
  51. 211be3b gpio: sifive: add support for DM based gpio driver for FU540-SoC by Sagar Shrikant Kadam · Tue Oct 01 10:00:46 2019 -0700
  52. 396f0bd riscv: add SPL support by Lukas Auer · Wed Aug 21 21:14:45 2019 +0200
  53. 6134659 riscv: add run mode configuration for SPL by Lukas Auer · Wed Aug 21 21:14:43 2019 +0200
  54. f942636 riscv: Access CSRs using CSR numbers by Bin Meng · Wed Jul 10 23:43:13 2019 -0700
  55. a27264c riscv: Sync csr.h with Linux kernel v5.2 by Bin Meng · Wed Jul 10 23:43:12 2019 -0700
  56. 9cce6f7 env: Drop environment.h header file where not needed by Simon Glass · Thu Aug 01 09:47:12 2019 -0600
  57. e5e6c36 riscv: Introduce CONFIG_XIP to support booting from flash by Rick Chen · Tue Apr 30 13:49:33 2019 +0800
  58. 7376677 riscv: Add a SYSCON driver for Andestech's PLMT by Rick Chen · Tue Apr 02 15:56:40 2019 +0800
  59. 6df4ed0 riscv: Add a SYSCON driver for Andestech's PLIC by Rick Chen · Tue Apr 02 15:56:39 2019 +0800
  60. a359665 riscv: add support for multi-hart systems by Lukas Auer · Sun Mar 17 19:28:37 2019 +0100
  61. 9c03845 riscv: import the supervisor binary interface header file by Lukas Auer · Sun Mar 17 19:28:33 2019 +0100
  62. 83d573d riscv: add infrastructure for calling functions on other harts by Lukas Auer · Sun Mar 17 19:28:32 2019 +0100
  63. 818d49a riscv: Enable CONFIG_SYS_BOOT_RAMDISK_HIGH for using initrd by Anup Patel · Mon Feb 25 08:15:33 2019 +0000
  64. 6f07f45 riscv: Add place-holder asm/arch/clk.h for driver compilation by Anup Patel · Mon Feb 25 08:14:24 2019 +0000
  65. 928452a riscv: Add asm/dma-mapping.h for DMA mappings by Anup Patel · Mon Feb 25 08:14:17 2019 +0000
  66. 89681a7 riscv: Save boot hart id to the global data by Bin Meng · Wed Dec 12 06:12:45 2018 -0800
  67. 9e9e6fe riscv: Add indirect stringification to csr_xxx ops by Bin Meng · Wed Dec 12 06:12:39 2018 -0800
  68. 731e2d4 riscv: Add exception codes for xcause register by Bin Meng · Wed Dec 12 06:12:37 2018 -0800
  69. ea5086b riscv: Add CSR numbers by Bin Meng · Wed Dec 12 06:12:36 2018 -0800
  70. b6ee5e1 riscv: Add a SYSCON driver for SiFive's Core Local Interruptor by Bin Meng · Wed Dec 12 06:12:30 2018 -0800
  71. 89b3934 riscv: Add kconfig option to run U-Boot in S-mode by Anup Patel · Mon Dec 03 10:57:40 2018 +0530
  72. 842d580 riscv: cache: Implement i/dcache [status, enable, disable] by Rick Chen · Wed Nov 07 09:34:06 2018 +0800
  73. 09db5fc riscv: do not reimplement generic io functions by Lukas Auer · Thu Nov 22 11:26:19 2018 +0100
  74. 78da26d riscv: make use of the barrier functions from Linux by Lukas Auer · Thu Nov 22 11:26:18 2018 +0100
  75. e429a1e riscv: fix use of incorrectly sized variables by Lukas Auer · Thu Nov 22 11:26:17 2018 +0100
  76. 401885a Use _AC and UL macros from linux/const.h by Baruch Siach · Sun Nov 11 12:31:01 2018 +0200
  77. 748dae2 riscv: Remove CSR read/write defines in encoding.h by Bin Meng · Wed Sep 26 06:55:15 2018 -0700
  78. 055700e riscv: Add a helper routine to print CPU information by Bin Meng · Wed Sep 26 06:55:14 2018 -0700
  79. ebd336f riscv: Remove mach type by Bin Meng · Wed Sep 26 06:55:09 2018 -0700
  80. d9eec24 riscv: Remove setup.h by Bin Meng · Wed Sep 26 06:55:07 2018 -0700
  81. 1359226 arch: types.h: factor out fixed width typedefs to int-ll64.h by Masahiro Yamada · Mon Aug 06 20:47:39 2018 +0900
  82. b66af37 riscv: cpu: nx25: Rename as ax25 by Rick Chen · Tue May 29 09:54:40 2018 +0800
  83. 9dbb973 SPDX: Convert single license tags to Linux Kernel style by Rick Chen · Tue May 29 14:10:06 2018 +0800
  84. 7ea64b0 riscv: Add board_quiesce_devices stub by Alexander Graf · Mon Apr 23 07:59:46 2018 +0200
  85. 3bb8f01 riscv: Add setjmp/longjmp code by Alexander Graf · Mon Apr 23 07:59:43 2018 +0200
  86. 435e382 riscv: Define PLATFORM__CLEAR_BIT for generic_clear_bit() by Bryan O'Donoghue · Mon Apr 30 15:56:04 2018 +0100
  87. 1c12981 riscv: Define PLATFORM__SET_BIT for generic_set_bit() by Bryan O'Donoghue · Mon Apr 30 15:56:03 2018 +0100
  88. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  89. 53b47b8 riscv: bootm: Remove ATAGS by Rick Chen · Tue Mar 13 14:59:41 2018 +0800
  90. 69ae630 riscv: checkpatch: Fix alignment should match open parenthesis by Rick Chen · Mon Feb 12 11:17:47 2018 +0800
  91. b34b4b9 riscv: checkpatch: Fix use of volatile by Rick Chen · Mon Feb 12 11:10:04 2018 +0800
  92. 5febadd riscv: checkpatch: Fix Macro argument reuse by Rick Chen · Mon Feb 12 11:07:58 2018 +0800
  93. 76c0a24 riscv: nx25: include: Add header files to support RISC-V by Rick Chen · Tue Dec 26 13:55:51 2017 +0800