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git01.mediatek.com / filogic / uboot / e957bd7e0eedd78794aed9851a82d7fd1901dc23 / cpu / mpc8xxx / ddr / ctrl_regs.c
  1. 24aa71a ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist by Kumar Gala · 15 years ago
  2. 68ef4bd fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT by Kumar Gala · 15 years ago
  3. 4be87b2 fsl-ddr: add the DDR3 SPD infrastructure by Dave Liu · 16 years ago
  4. 82aa953 fsl-ddr: Fix two bugs in the ddr infrastructure by Dave Liu · 16 years ago
  5. 2aad0ae fsl-ddr: make the self refresh idle threshold configurable by Dave Liu · 16 years ago
  6. 4758d53 fsl-ddr: clean up the ddr code for DDR3 controller by Dave Liu · 16 years ago
  7. 5c1bb51 fsl-ddr: update the bit mask for DDR3 controller by Dave Liu · 16 years ago
  8. d90e040 Add debug information for DDR controller registers by Haiying Wang · 16 years ago
  9. 272b596 Make DDR interleaving mode work correctly by Haiying Wang · 16 years ago
  10. 35ad58d Fix compiler warning in mpc8xxx ddr code by Kumar Gala · 16 years ago
  11. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · 16 years ago