Log - e6b5f1b9eb0b2571b91f05563f83ad8e1387ad03 - filogic/uboot

4be87b2 fsl-ddr: add the DDR3 SPD infrastructure by Dave Liu · Sat Mar 14 12:48:30 2009 +0800
82aa953 fsl-ddr: Fix two bugs in the ddr infrastructure by Dave Liu · Sat Mar 14 12:48:19 2009 +0800
45eea1d fsl-ddr: Allow system to boot if we have more than 4G of memory by Kumar Gala · Tue Feb 10 23:53:40 2009 -0600
c0f3b3c fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controller by Kumar Gala · Fri Feb 06 09:56:34 2009 -0600
a06d74c fsl-ddr: use the 1T timing as default configuration by Dave Liu · Fri Nov 21 16:31:43 2008 +0800
2aad0ae fsl-ddr: make the self refresh idle threshold configurable by Dave Liu · Fri Nov 21 16:31:35 2008 +0800
4758d53 fsl-ddr: clean up the ddr code for DDR3 controller by Dave Liu · Fri Nov 21 16:31:29 2008 +0800
5c1bb51 fsl-ddr: update the bit mask for DDR3 controller by Dave Liu · Fri Nov 21 16:31:22 2008 +0800
b135d93 fsl ddr skip interleaving if not supported. by Ed Swarthout · Wed Oct 29 09:21:44 2008 -0500
d90e040 Add debug information for DDR controller registers by Haiying Wang · Fri Oct 03 12:37:26 2008 -0400
b834f92 Check DDR interleaving mode by Haiying Wang · Fri Oct 03 12:37:10 2008 -0400
fa44036 Pass dimm parameters to populate populate controller options by Haiying Wang · Fri Oct 03 12:36:55 2008 -0400
272b596 Make DDR interleaving mode work correctly by Haiying Wang · Fri Oct 03 12:36:39 2008 -0400
0383694 rename CFG_ macros to CONFIG_SYS by Jean-Christophe PLAGNIOL-VILLARD · Thu Oct 16 15:01:15 2008 +0200
9dbbd7b Coding style cleanup, update CHANGELOG by Wolfgang Denk · Sat Sep 13 02:23:05 2008 +0200
35ad58d Fix compiler warning in mpc8xxx ddr code by Kumar Gala · Fri Sep 05 14:40:29 2008 -0500
fcf2884 FSL DDR: Add DDR2 DIMM paramter support by Kumar Gala · Tue Aug 26 15:01:32 2008 -0500
711d11b FSL DDR: Add DDR1 DIMM paramter support by Kumar Gala · Tue Aug 26 15:01:30 2008 -0500
124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · Tue Aug 26 15:01:29 2008 -0500