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git01.mediatek.com / filogic / uboot / e67eac0b9ff62f9aff7dedb07bf3983749e0510a / drivers / ddr
  1. e3cef9f driver/ddr/fsl: Fix timing_cfg_2 by York Sun · 8 years ago
  2. 8d56db9 Various, unrelated tree-wide typo fixes. by Robert P. J. Day · 8 years ago
  3. 4be68d0 driver/ddr/fsl: Check condition for erratum A-009803 by Shengzhou Liu · 9 years ago
  4. 2a77a12 drivers/ddr/fsl: Disabling data init if ECC is not enabled by York Sun · 9 years ago
  5. 3abd16b drivers/ddr/fsl: Fix timing_cfg_2 register by York Sun · 9 years ago
  6. 3b33dd2 drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntl by Shengzhou Liu · 9 years ago
  7. c4a11bc Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriq by Tom Rini · 9 years ago
  8. 31fdba2 arm: mvebu: a38x: Weed out floating point use by Marek Vasut · 9 years ago
  9. c72d12e driver/ddr/fsl: Add workaround for erratum A-010165 by Shengzhou Liu · 9 years ago
  10. 9c3cdc2 driver/ddr/fsl: Add workaround for erratum A-009801 by Shengzhou Liu · 9 years ago
  11. b2dee26 drivers/ddr/fsl: update workaround for erratum A-008511 by Shengzhou Liu · 9 years ago
  12. edfdb99 Fix spelling of "occurred". by Vagrant Cascadian · 9 years ago
  13. 66acabc ddr: altera: Repair DQ window centering code by Marek Vasut · 9 years ago
  14. a4b9fa1 ddr: altera: Staticize global variables by Marek Vasut · 9 years ago
  15. 4df2d7b ddr: altera: Make DLEVEL behavior inclusive by Marek Vasut · 9 years ago
  16. f4d3862 ddr: altera: Zero DM IN delay in scc_mgr_zero_group() by Marek Vasut · 9 years ago
  17. 2bf2ee5 ddr: altera: Remove unnecessary ODT mode config by Marek Vasut · 9 years ago
  18. acee8fd ddr: altera: Remove unnecessary update of the SCC by Marek Vasut · 9 years ago
  19. 12361a2 ddr: altera: Fix DRAM end value in protection rule by Marek Vasut · 9 years ago
  20. 45ce296 ddr: altera: Fix scc_mgr_set() argument order by Marek Vasut · 9 years ago
  21. 6946989 ddr: altera: Tweak DQS tracking enable handling by Marek Vasut · 9 years ago
  22. 2654bc9 ddr: altera: Replace ad-hoc constant with macro by Marek Vasut · 9 years ago
  23. 0137e60 Fix typo choosen in comments and printf logs by Alexander Merkle · 9 years ago
  24. 5b2c16a arm: mvebu: Fix ddr3_init() cpu config by Dirk Eibach · 9 years ago
  25. b03e1b1 driver/ddr/fsl: Add workaround for erratum A-009803 by Shengzhou Liu · 9 years ago
  26. 5219944 driver/ddr/fsl: Add address parity support for DDR4 UDIMM/discrete by Shengzhou Liu · 9 years ago
  27. 7557405 Use correct spelling of "U-Boot" by Bin Meng · 9 years ago
  28. e80d11f drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32. by Purna Chandra Mandal · 9 years ago
  29. 7ae7a0e drivers/ddr/fsl: fsl_ddr_sdram_size remove unused controllers by Ed Swarthout · 9 years ago
  30. bdda96c driver/ddr/fsl: Add workaround for A009663 by Shengzhou Liu · 9 years ago
  31. fa2e2fb fsl/ddr: Add workaround for ERRATUM_A009942 by Shengzhou Liu · 9 years ago
  32. e237880 Add more SPDX-License-Identifier tags by Tom Rini · 9 years ago
  33. 42aa46d ddr: altera: Init the rule ID in debug code by Marek Vasut · 9 years ago
  34. d911168 mvebu: axp: Rename MV_DDR_32BIT to CONFIG_DDR_32BIT by Phil Sutter · 9 years ago
  35. 33aa8de axp: Fix debugging support in DDR3 write leveling by Phil Sutter · 9 years ago
  36. ff7ad17 arm: mvebu: Make ECC support configurable on Armada XP by Stefan Roese · 9 years ago
  37. 3c6b6fc arm: mvebu: ddr: Fix compilation warning by Stefan Roese · 9 years ago
  38. fae8805 move erratum a008336 and a008514 to soc specific file by Yao Yuan · 9 years ago
  39. 5a46e43 fsl/ddr: updated ddr errata-A008378 for arm and power SoCs by Shengzhou Liu · 9 years ago
  40. 77594b3 driver/ddr/fsl: Update timing config for heavy load by York Sun · 9 years ago
  41. 780ae3d driver/ddr/fsl: Update workaround for A008511 for vref range by York Sun · 9 years ago
  42. d192126 driver/ddr/fsl: Update MR5 RTT park by York Sun · 9 years ago
  43. d4d97ef driver/ddr/fsl: Update DDR4 MR6 for Vref range by York Sun · 9 years ago
  44. 5cb12f6 driver/ddr/fsl: Update DDR4 RTT values by York Sun · 9 years ago
  45. 68c19d7 drivers/ddr/fsl: Fix typo in BIST test for DDR4 by York Sun · 9 years ago
  46. d957a67 drivers/ddr/fsl: Enable detection of one DDR controller operation for LSCH3 by York Sun · 9 years ago
  47. 77f7ded armv8: ls2085a: Add support of LS2085A SoC by Prabhakar Kushwaha · 9 years ago
  48. 122bcfd armv8: LS2080A: Rename LS2085A to reflect LS2080A by Prabhakar Kushwaha · 9 years ago
  49. dea4e33 arm: mvebu: Fix SAR1_CPU_CORE_MASK by Dirk Eibach · 9 years ago
  50. 0277a6b arm: mvebu: a38x: Remove unsupported topologies by Kevin Smith · 9 years ago
  51. 0cab3ec Various Makefiles: Add SPDX-License-Identifier tags by Tom Rini · 9 years ago
  52. 6dc192d drivers/ddr/fsl_ddr: Make SR_IE configurable by Joakim Tjernlund · 9 years ago
  53. 69bab55 bitops: introduce BIT() definition by Heiko Schocher · 9 years ago
  54. eb447cb ddr: altera: Repair uninited variable by Marek Vasut · 9 years ago
  55. af67cf3 ddr: altera: Replace float multiplication with integer one by Marek Vasut · 9 years ago
  56. f3345e6 arm: mvebu: Add complete SDRAM ECC scrubbing by Stefan Roese · 9 years ago
  57. e4a0f27 arm: mvebu: sdram: Enable ECC support on Armada XP by Stefan Roese · 9 years ago
  58. c85b9b3 ddr: altera: sequencer: Clean checkpatch issues by Marek Vasut · 9 years ago
  59. 8af9ca0 ddr: altera: sequencer: Clean data types by Marek Vasut · 9 years ago
  60. 5867376 ddr: altera: sequencer: Pluck out misc macros from code by Marek Vasut · 9 years ago
  61. 324d3f7 ddr: altera: sequencer: Zap SEQ_T(INIT|RESET)_CNTR._VAL by Marek Vasut · 9 years ago
  62. 32d813e ddr: altera: sequencer: Zap VFIFO_SIZE by Marek Vasut · 9 years ago
  63. f00a6ea ddr: altera: sequencer: Wrap misc remaining macros by Marek Vasut · 9 years ago
  64. 7e8f8a7 ddr: altera: sequencer: Pluck out IO_* macros from code by Marek Vasut · 9 years ago
  65. 3bf9204 ddr: altera: sequencer: Wrap IO_* macros by Marek Vasut · 9 years ago
  66. 2dfc76b ddr: altera: sequencer: Pluck out RW_MGR_* macros from code by Marek Vasut · 9 years ago
  67. 39b620e ddr: altera: sequencer: Wrap RW_MGR_* macros by Marek Vasut · 9 years ago
  68. 3384e74 ddr: altera: sequencer: Wrap ac_rom_init and inst_rom_init by Marek Vasut · 9 years ago
  69. 42ed1f2 ddr: altera: sequencer: Zap bogus redefinition of RW_MGR_MEM_NUMBER_OF_RANKS by Marek Vasut · 9 years ago
  70. eb98b38 ddr: altera: sequencer: Zap unused params and macros by Marek Vasut · 9 years ago
  71. 662a8a6 ddr: altera: sequencer: Move qts-generated files to board dir by Marek Vasut · 9 years ago
  72. 6772cd9 ddr: altera: sdram: Make sdram_start and sdram_end into u32 by Marek Vasut · 9 years ago
  73. 9114407 ddr: altera: sdram: Minor cleanup in sdram_get_rule() by Marek Vasut · 9 years ago
  74. 7fce5bc ddr: altera: sdram: Minor cleanup in sdram_set_rule() by Marek Vasut · 9 years ago
  75. b0d848c ddr: altera: sdram: Add missing kerneldoc by Marek Vasut · 9 years ago
  76. 116d88f ddr: altera: sdram: Clean up sdram_write_verify() by Marek Vasut · 9 years ago
  77. 1796a09 ddr: altera: sdram: Clean up sdram_calculate_size() part 2 by Marek Vasut · 9 years ago
  78. 6d6fbba ddr: altera: sdram: Clean up sdram_calculate_size() part 1 by Marek Vasut · 9 years ago
  79. 32ada57 ddr: altera: sdram: Introduce socfpga_sdram_get_config() by Marek Vasut · 9 years ago
  80. 1b1cc10 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 8 by Marek Vasut · 9 years ago
  81. 5a4e8ed ddr: altera: sdram: Clean up sdram_mmr_init_full() part 7 by Marek Vasut · 9 years ago
  82. b81f11c ddr: altera: sdram: Clean up sdram_mmr_init_full() part 6 by Marek Vasut · 9 years ago
  83. 1e271e4 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 5 by Marek Vasut · 9 years ago
  84. 71c1a00 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 4 by Marek Vasut · 9 years ago
  85. 3a07911 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 3 by Marek Vasut · 9 years ago
  86. 7697ff7 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 2 by Marek Vasut · 9 years ago
  87. 4fccfa4 ddr: altera: sdram: Clean up sdram_mmr_init_full() part 1 by Marek Vasut · 9 years ago
  88. 4f3adbf ddr: altera: sdram: Introduce socfpga_sdram_config() structure by Marek Vasut · 9 years ago
  89. 92e8e6f ddr: altera: sdram: Clean up set_sdr_mp_threshold() by Marek Vasut · 9 years ago
  90. 44f09cc ddr: altera: sdram: Clean up set_sdr_mp_pacing() by Marek Vasut · 9 years ago
  91. b933b19 ddr: altera: sdram: Clean up set_sdr_mp_weight() by Marek Vasut · 9 years ago
  92. f904a86 ddr: altera: sdram: Clean up set_sdr_fifo_cfg() by Marek Vasut · 9 years ago
  93. 9d64f19 ddr: altera: sdram: Clean up set_sdr_static_cfg() by Marek Vasut · 9 years ago
  94. 820b0d9 ddr: altera: sdram: Clean up set_sdr_addr_rw() by Marek Vasut · 9 years ago
  95. 6e9af9b ddr: altera: sdram: Clean up set_sdr_dram_timing*() by Marek Vasut · 9 years ago
  96. 82a2764 ddr: altera: sdram: Clean up set_sdr_ctrlcfg() by Marek Vasut · 9 years ago
  97. 724c50f ddr: altera: sdram: Clean up compute_errata_rows() part 2 by Marek Vasut · 9 years ago
  98. 186880e ddr: altera: sdram: Clean up compute_errata_rows() part 1 by Marek Vasut · 9 years ago
  99. 2fda506 ddr: altera: sdram: Switch to generic_hweight32() by Marek Vasut · 9 years ago
  100. 98d279a ddr: altera: Clean up of delay_for_n_mem_clocks() part 5 by Marek Vasut · 9 years ago