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git01.mediatek.com / filogic / uboot / e464d6ebc703beeedf04ebbd68f77005d9359067 / arch / riscv / cpu / ax25
  1. 49cb706 riscv: cache: use CCTL to flush d-cache by Rick Chen · Wed Aug 28 18:46:11 2019 +0800
  2. 05a684e riscv: cache: Flush L2 cache before jump to linux by Rick Chen · Wed Aug 28 18:46:09 2019 +0800
  3. 19117d2 riscv: ax25: add imply v5l2 cache controller by Rick Chen · Thu Aug 29 10:30:13 2019 +0800
  4. 6134659 riscv: add run mode configuration for SPL by Lukas Auer · Wed Aug 21 21:14:43 2019 +0200
  5. 43ec7e0 CONFIG_SPL_SYS_[DI]CACHE_OFF: add by Trevor Woerner · Fri May 03 09:41:00 2019 -0400
  6. f71410a riscv: ax25: Andes specific cache shall only support in M-mode by Rick Chen · Tue Apr 02 15:56:42 2019 +0800
  7. 14a1075 riscv: ax25: Add platform-specific Kconfig options by Rick Chen · Tue Apr 02 15:56:41 2019 +0800
  8. 6280e32 riscv: move the AX25-specific implementation of flush_dcache_all by Lukas Auer · Fri Jan 04 01:37:29 2019 +0100
  9. 4b284ad riscv: ax25: Hide the ax25-specific Kconfig option by Bin Meng · Wed Dec 12 06:12:28 2018 -0800
  10. 842d580 riscv: cache: Implement i/dcache [status, enable, disable] by Rick Chen · Wed Nov 07 09:34:06 2018 +0800
  11. de8d80e riscv: Move do_reset() to a common place by Bin Meng · Wed Sep 26 06:55:22 2018 -0700
  12. bcb3843 riscv: Make start.S available for all targets by Bin Meng · Wed Sep 26 06:55:17 2018 -0700
  13. a28e0f5 riscv: Move the linker script to the CPU root directory by Bin Meng · Wed Sep 26 06:55:11 2018 -0700
  14. b28f7b3 riscv: Include bss subsections in linker script by Alexander Graf · Mon Aug 20 14:25:49 2018 +0200
  15. 94a10f2 efi_loader: Rename sections to allow for implicit data by Alexander Graf · Tue Jun 12 07:48:37 2018 +0200
  16. b66af37 riscv: cpu: nx25: Rename as ax25 by Rick Chen · Tue May 29 09:54:40 2018 +0800