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git01.mediatek.com / filogic / uboot / d4932bdfddaef580c2334c44926244cd5720b70b / drivers / clk
  1. 1285f8e clk: scmi: define LOG_CATEGORY by Patrick Delaunay · Thu Oct 28 19:13:13 2021 +0200
  2. b0e3cf9 clk: ast2600: Add RSACLK control for ACRY by Chia-Wei Wang · Wed Oct 27 14:17:29 2021 +0800
  3. d59cd6f clk: ast2600: Add YCLK control for HACE by Joel Stanley · Wed Oct 27 14:17:26 2021 +0800
  4. 72a5762 stm32mp15: replace CONFIG_TFABOOT when it is possible by Patrick Delaunay · Mon Oct 11 09:52:50 2021 +0200
  5. 9a77a96 clk: sunxi: Extend DM_RESET selection to SPL by Samuel Holland · Sat Sep 11 14:45:31 2021 -0500
  6. d0dcb75 clk: sifive: Fix -Wint-to-pointer-cast warning by Bin Meng · Sun Sep 12 11:15:09 2021 +0800
  7. d3196cb clk: fixed_rate: add dummy disable() function by Samuel Holland · Tue Oct 12 19:40:29 2021 -0500
  8. 7b9b926 clk: rockchip: rk3568: update clks by Elaine Zhang · Tue Oct 12 16:43:00 2021 +0800
  9. b959910 rockchip: px30: add support for setting cpll clock by Chris Morgan · Thu Aug 05 11:48:47 2021 -0500
  10. 97e96f2 Merge https://source.denx.de/u-boot/custodians/u-boot-sunxi by Tom Rini · Tue Oct 12 08:58:58 2021 -0400
  11. d441175 clk: ti: add am33xx/am43xx spread spectrum clock support by Dario Binacchi · Sun Sep 26 11:58:58 2021 +0200
  12. f7d4954 clk: sunxi: Add drivers for A31 and H6 PRCM CCUs by Samuel Holland · Sun Sep 12 09:47:25 2021 -0500
  13. fa7a7fa clk: sunxi: Add support for I2C gates/resets by Samuel Holland · Sun Sep 12 09:47:24 2021 -0500
  14. 12e3faa clk: sunxi: Move header out of arch directory by Samuel Holland · Sun Sep 12 11:48:43 2021 -0500
  15. e72139e clk: k210: Try harder to get the best config by Sean Anderson · Sat Sep 11 13:20:03 2021 -0400
  16. 89c3584 k210: clk: Refactor out_of_spec tests by Sean Anderson · Sat Sep 11 13:20:01 2021 -0400
  17. b0126e9 clk: k210: Fix checking if ulongs are less than 0 by Sean Anderson · Sat Sep 11 13:20:00 2021 -0400
  18. 2154876 Merge tag 'xilinx-for-v2022.01-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next by Tom Rini · Thu Sep 30 11:29:41 2021 -0400
  19. 62fb2b4 WS cleanup: remove SPACE(s) followed by TAB by Wolfgang Denk · Mon Sep 27 17:42:39 2021 +0200
  20. 3fd6633 WS cleanup: remove trailing empty lines by Wolfgang Denk · Mon Sep 27 17:42:36 2021 +0200
  21. b5ef0ba clk: versal: Enable only GATE type clocks by T Karthik Reddy · Tue Sep 28 11:30:27 2021 +0530
  22. f04c4ab Merge tag 'dm-pull-next-27sep21' of https://source.denx.de/u-boot/custodians/u-boot-dm into next by Tom Rini · Mon Sep 27 11:09:23 2021 -0400
  23. 961578e Merge tag 'v2021.10-rc5' into next by Tom Rini · Mon Sep 27 09:45:36 2021 -0400
  24. 1257efc clk: Rename clk_get_by_driver_info() by Simon Glass · Sat Aug 07 07:24:09 2021 -0600
  25. 6d70ba0 treewide: Try to avoid the preprocessor with OF_REAL by Simon Glass · Sat Aug 07 07:24:06 2021 -0600
  26. 9288265 treewide: Use OF_REAL instead of !OF_PLATDATA by Simon Glass · Sat Aug 07 07:24:04 2021 -0600
  27. 3580f6d treewide: Simply conditions with the new OF_REAL by Simon Glass · Sat Aug 07 07:24:03 2021 -0600
  28. 8b5bbad clk: at91: clk-master: split master clock in pres and divider by Claudiu Beznea · Fri Jul 16 08:43:48 2021 +0300
  29. db4c2dc clk: ti: k3: Update driver to account for divider flags by Suman Anna · Tue Sep 07 17:16:58 2021 -0500
  30. 6bc722e clk: ti: k3-pll: Change DIV_CTRL programming to read-modify-write by Dave Gerlach · Tue Sep 07 17:16:57 2021 -0500
  31. b58bfe0 mmc: Rename MMC_SUPPORT to MMC by Simon Glass · Sun Aug 08 12:20:09 2021 -0600
  32. 5e317de drivers: clk: Add memory clock driver for Intel N5X device by Siew Chin Lim · Tue Aug 10 11:26:32 2021 +0800
  33. 1557df8 drivers: clk: Add clock driver for Intel N5X device by Siew Chin Lim · Tue Aug 10 11:26:30 2021 +0800
  34. db7b2f4 clk: clk_versaclock: Add support for versaclock driver by Adam Ford · Fri Jun 04 12:26:06 2021 -0500
  35. d69d174 clk: stm32mp1: add support of BSEC clock by Patrick Delaunay · Fri Jul 16 10:10:55 2021 +0200
  36. 8f20e73 rockchip: px30: Support configure SFC by Jon Lin · Thu Aug 05 16:27:53 2021 +0800
  37. dcd705e clk: stm32mp1: add support of missing SPI clocks by Patrick Delaunay · Fri Jul 09 14:24:34 2021 +0200
  38. 97790fb clk: zynqmp: Add support for enabling clock on lpd_lsbus by Michal Simek · Thu Jul 01 19:01:42 2021 +0200
  39. f5e1d9e Merge tag 'u-boot-imx-20210717' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx by Tom Rini · Sat Jul 17 10:52:21 2021 -0400
  40. 0a06b64 Merge branch '2021-07-15-assorted-fixes' by Tom Rini · Fri Jul 16 09:15:59 2021 -0400
  41. c7d146d clk: stm32mp1: add support of SYSCFG clock by Patrick Delaunay · Tue Jun 29 12:04:22 2021 +0200
  42. 862555d clk: Detect failure to set defaults by Simon Glass · Thu May 13 19:39:31 2021 -0600
  43. 04f1971 clk: uniphier: Add PCIe clock entry by Kunihiko Hayashi · Tue Jul 06 19:01:06 2021 +0900
  44. 339beba clk: imx8mm: Add SPI clocks by Frieder Schrempf · Mon Jun 07 14:36:43 2021 +0200
  45. 4481168 clk: armada-37xx: Set DM_FLAG_PRE_RELOC by Marek Behún · Tue May 25 19:42:39 2021 +0200
  46. 4aab306 Merge tag 'dm-pull-6jul21' of https://source.denx.de/u-boot/custodians/u-boot-dm by Tom Rini · Wed Jul 07 13:34:42 2021 -0400
  47. 8131335 dm: define LOG_CATEGORY for all uclass by Patrick Delaunay · Tue Apr 27 11:02:19 2021 +0200
  48. f872d47 drivers: clk: sifive: fu740-prci: replace 'pciaux' with 'pcieaux' by Green Wan · Mon Jun 28 19:13:08 2021 +0800
  49. 08b3fd6 Merge tag 'xilinx-for-v2021.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next by Tom Rini · Thu Jul 01 08:57:23 2021 -0400
  50. 159b60e Merge branch 'next' of https://source.denx.de/u-boot/custodians/u-boot-sh into next by Tom Rini · Mon Jun 28 18:32:07 2021 -0400
  51. d3e8b73 Merge tag 'v2021.07-rc5' into next by Tom Rini · Mon Jun 28 16:22:13 2021 -0400
  52. 86d59f3 clk: renesas: Add R8A779A0 clock tables by Hai Pham · Tue Aug 11 10:46:34 2020 +0700
  53. 0fbb8a7 clk: renesas: Handle R8A779A0 V3U clock types in Gen3 clock code by Marek Vasut · Tue Apr 27 19:52:53 2021 +0200
  54. 39df053 clk: zynq: Add clock wizard driver by Zhengxun · Fri Jun 11 15:10:48 2021 +0000
  55. ce92768 Merge tag 'u-boot-rockchip-20210618' of https://source.denx.de/u-boot/custodians/u-boot-rockchip into next by Tom Rini · Sat Jun 19 08:20:12 2021 -0400
  56. b9c3214 clk: cosmetic change in uclass by Patrick Delaunay · Tue Apr 27 10:57:54 2021 +0200
  57. 5be90bb rockchip: rk3568: add clock driver by Elaine Zhang · Wed Jun 02 11:39:24 2021 +0800
  58. 152919d clk: k210: Move k210 clock out of its own subdirectory by Sean Anderson · Fri Jun 11 00:16:14 2021 -0400
  59. 16d64cd clk: k210: Remove bypass driver by Sean Anderson · Fri Jun 11 00:16:13 2021 -0400
  60. 1a37182 clk: k210: Don't set PLL rates if we are already at the correct rate by Sean Anderson · Fri Jun 11 00:16:12 2021 -0400
  61. 3a29bc6 clk: k210: Re-add support for setting rate by Sean Anderson · Fri Jun 11 00:16:11 2021 -0400
  62. ecf9284 clk: k210: Implement soc_clk_dump by Sean Anderson · Fri Jun 11 00:16:10 2021 -0400
  63. edbe849 clk: k210: Move pll into the rest of the driver by Sean Anderson · Fri Jun 11 00:16:09 2021 -0400
  64. 2957313 clk: k210: Rewrite to remove CCF by Sean Anderson · Fri Jun 11 00:16:08 2021 -0400
  65. 08d531c clk: Allow force setting clock defaults before relocation by Sean Anderson · Fri Jun 11 00:16:07 2021 -0400
  66. 82ceb0d clk: add support for TI K3 SoC clocks by Tero Kristo · Fri Jun 11 11:45:14 2021 +0300
  67. 81744b7 clk: add support for TI K3 SoC PLL by Tero Kristo · Fri Jun 11 11:45:13 2021 +0300
  68. 9ab78c1 clk: fix set_rate to clean up cached rates for the hierarchy by Tero Kristo · Fri Jun 11 11:45:12 2021 +0300
  69. d41b2b3 clk: fix assigned-clocks to pass with deferring provider by Tero Kristo · Fri Jun 11 11:45:11 2021 +0300
  70. 1770884 clk: sci-clk: fix return value of set_rate by Tero Kristo · Fri Jun 11 11:45:10 2021 +0300
  71. f04dfff clk: do not attempt to fetch clock pointer with null device by Tero Kristo · Fri Jun 11 11:45:08 2021 +0300
  72. de4ef9b clk: fixed_rate: add API for directly registering fixed rate clocks by Tero Kristo · Fri Jun 11 11:45:06 2021 +0300
  73. d08f867 clk: imx: clk-imxrt1050: introduce IMXRT1050_CLK_USBOH3 by Giulio Benetti · Thu May 20 16:10:14 2021 +0200
  74. 71d1ee4 clk: imx: clk-imxrt1050: introduce LCDIF_PIX and rename LCDIF to LCDIF_APB by Giulio Benetti · Thu May 13 12:19:33 2021 +0200
  75. ecefa5f drivers: clk: add fu740 support by Green Wan · Thu May 27 06:52:08 2021 -0700
  76. 4bebdd3 treewide: Convert macro and uses of __section(foo) to __section("foo") by Marek Behún · Thu May 20 13:23:52 2021 +0200
  77. 8f56786 clk: renesas: Deduplicate gen3_clk_get_rate64() PLL handling by Marek Vasut · Tue Apr 27 19:36:39 2021 +0200
  78. 9480346 clk: renesas: Add register pointers into struct cpg_mssr_info by Hai Pham · Thu Nov 05 22:30:37 2020 +0700
  79. 016a4c2 clk: renesas: Introduce enum clk_reg_layout by Hai Pham · Thu Nov 05 21:32:38 2020 +0700
  80. 5460ee0 clk: renesas: Pass struct cpg_mssr_info to renesas_clk_endisable() by Hai Pham · Fri May 22 10:39:04 2020 +0700
  81. 814217e clk: renesas: Make reset controller modemr register offset configurable by Marek Vasut · Sun Apr 25 21:53:05 2021 +0200
  82. 215de2b clk: renesas: Add support for RPCD2 clock by Hai Pham · Tue Aug 11 10:25:28 2020 +0700
  83. 1a61896 clk: renesas: Fix Realtime Module Stop Control Register offsets by Hai Pham · Tue May 19 17:42:05 2020 +0700
  84. f2279df clk: renesas: Fix incorrect return RPC clk_get_rate by Hai Pham · Sat Dec 05 09:35:40 2020 +0700
  85. f5fec9d clk: renesas: Reinstate RPC clock on R-Car D3/E3 by Marek Vasut · Sun Apr 25 21:26:22 2021 +0200
  86. 0e8dcb7 clk: renesas: Synchronize R-Car Gen3 tables with Linux 5.12 by Marek Vasut · Sun Apr 25 21:10:40 2021 +0200
  87. aac4de2 clk: renesas: Synchronize R-Car Gen2 tables with Linux 5.12 by Marek Vasut · Sun Apr 25 21:09:10 2021 +0200
  88. 8538d53 clk: renesas: Synchronize RZ/G2 tables with Linux 5.12 by Marek Vasut · Sun Apr 25 21:08:18 2021 +0200
  89. 8aa82e1 clk: Add support for the k210 clock driver pre-relocation by Sean Anderson · Thu Apr 08 22:13:08 2021 -0400
  90. 95d2724 clk: k210: Move the clint clock to under aclk by Sean Anderson · Thu Apr 08 22:13:07 2021 -0400
  91. afab998 clk: k210: Remove k210_register_pll by Sean Anderson · Thu Apr 08 22:13:06 2021 -0400
  92. 16e5c17 clk: k210: Fix PLL enable always getting taken by Sean Anderson · Thu Apr 08 22:13:05 2021 -0400
  93. e649ff3 clk: k210: Fix PLLs not being enabled by Sean Anderson · Thu Apr 08 22:13:04 2021 -0400
  94. d7ac373 clk: Warn on failure to assign rate by Sean Anderson · Thu Apr 08 22:13:03 2021 -0400
  95. eff80eb clk: ti: am3-dpll: use custom API for memory access by Dario Binacchi · Sat May 01 17:05:25 2021 +0200
  96. 3693460 clk: ti: gate: use custom API for memory access by Dario Binacchi · Sat May 01 17:05:24 2021 +0200
  97. ac7c705 clk: ti: change clk_ti_latch() signature by Dario Binacchi · Sat May 01 17:05:23 2021 +0200
  98. 6dfe426 clk: ti: add custom API for memory access by Dario Binacchi · Sat May 01 17:05:22 2021 +0200
  99. a738b53 Merge tag 'xilinx-for-v2021.07-rc2' of https://source.denx.de/u-boot/custodians/u-boot-microblaze by Tom Rini · Thu Apr 29 11:31:06 2021 -0400
  100. 5af8b6a clk: renesas: Synchronize Gen2 MSTP teardown tables by Marek Vasut · Sat Jun 06 15:26:14 2020 +0200