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git01.mediatek.com / filogic / uboot / d1eb93bad135f615cc3750f351b613e458c37c67 / arch / riscv / cpu / jh7110
  1. 51a9aac common: return type board_get_usable_ram_top by Heinrich Schuchardt · Sat Aug 12 20:16:58 2023 +0200
  2. ac4bf43 riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE by Shengyu Qu · Wed Aug 09 21:11:33 2023 +0800
  3. 62b89a1 riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation by Shengyu Qu · Wed Aug 09 21:11:32 2023 +0800
  4. 8fe34ac riscv: starfive: Add SYS_CACHE_SHIFT_6 to enable SYS_CACHELINE_SIZE by Minda Chen · Mon Aug 07 16:53:37 2023 +0800
  5. b5f0372 riscv: Rename SiFive CLINT to RISC-V ALINT by Bin Meng · Wed Jun 21 23:11:46 2023 +0800
  6. f69a512 ram: starfive: Read memory size information from EEPROM by Yanhong Wang · Thu Jun 15 17:36:51 2023 +0800
  7. 5203a63 riscv: cpu: jh7110: Add Kconfig for StarFive JH7110 SoC by Yanhong Wang · Wed Mar 29 11:42:18 2023 +0800
  8. e28ec34 riscv: cpu: jh7110: Add support for jh7110 SoC by Yanhong Wang · Wed Mar 29 11:42:08 2023 +0800