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git01.mediatek.com / filogic / uboot / d1a2587961966abbf282dfad28f391c85c8fa111 / doc / device-tree-bindings / clock / st,stm32mp1.txt
  1. 885bdc2 stm32mp1: clk: configure pll1 with OPP by Patrick Delaunay · Mon May 25 12:19:44 2020 +0200
  2. c22caac ARM: dts: stm32m1: add reg for pll nodes by Patrick Delaunay · Tue Jan 28 10:11:03 2020 +0100
  3. caba145 dt-bindings: clock: stm32mp1: support disabled fixed clock by Patrick Delaunay · Tue Jul 30 19:16:19 2019 +0200
  4. 09e1f60 stm32mp1: update RCC binding after kernel realignment by Patrick Delaunay · Thu Apr 18 17:32:41 2019 +0200
  5. 9a6ce2a clk: stm32mp1: correctly handle Clock Spreading Generator by Patrick Delaunay · Wed Jan 30 13:07:06 2019 +0100
  6. 80cb568 stm32mp1: clk: support digital bypass by Patrick Delaunay · Mon Jul 16 10:41:46 2018 +0200
  7. f11398e clk: stm32mp1: add clock tree initialization by Patrick Delaunay · Mon Mar 12 10:46:16 2018 +0100