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git01.mediatek.com / filogic / uboot / c7d983a6658d807081ca64eea6fbefaa16c11578 / cpu / mpc8xxx / ddr
  1. c7d983a fsl-ddr: Fix power-down timing settings by Dave Liu · Wed Dec 16 10:24:36 2009 -0600
  2. 0f9318f fsl-ddr: Fix the chip-select interleaving issue by Dave Liu · Thu Nov 12 07:26:37 2009 +0800
  3. 63fa48d mpc8xxx: improve LAW error messages when setting up DDR by Paul Gortmaker · Wed Oct 07 16:34:28 2009 -0400
  4. 14f2eb1 ppc/8xxx: Misc DDR related fixes by Kumar Gala · Thu Sep 10 14:54:55 2009 -0500
  5. 24aa71a ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist by Kumar Gala · Tue Sep 01 22:01:54 2009 -0500
  6. f4018f9 85xx, 86xx: Add common board_add_ram_info() by Peter Tyser · Fri Jul 17 10:14:48 2009 -0500
  7. efb8ce3 fsl_ddr: Fix DDR3 calculation of rank density with 8GB or more by Timur Tabi · Wed Jul 01 16:51:59 2009 -0500
  8. 68ef4bd fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT by Kumar Gala · Thu Jun 11 23:42:35 2009 -0500
  9. 4be87b2 fsl-ddr: add the DDR3 SPD infrastructure by Dave Liu · Sat Mar 14 12:48:30 2009 +0800
  10. 82aa953 fsl-ddr: Fix two bugs in the ddr infrastructure by Dave Liu · Sat Mar 14 12:48:19 2009 +0800
  11. 45eea1d fsl-ddr: Allow system to boot if we have more than 4G of memory by Kumar Gala · Tue Feb 10 23:53:40 2009 -0600
  12. c0f3b3c fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controller by Kumar Gala · Fri Feb 06 09:56:34 2009 -0600
  13. a06d74c fsl-ddr: use the 1T timing as default configuration by Dave Liu · Fri Nov 21 16:31:43 2008 +0800
  14. 2aad0ae fsl-ddr: make the self refresh idle threshold configurable by Dave Liu · Fri Nov 21 16:31:35 2008 +0800
  15. 4758d53 fsl-ddr: clean up the ddr code for DDR3 controller by Dave Liu · Fri Nov 21 16:31:29 2008 +0800
  16. 5c1bb51 fsl-ddr: update the bit mask for DDR3 controller by Dave Liu · Fri Nov 21 16:31:22 2008 +0800
  17. b135d93 fsl ddr skip interleaving if not supported. by Ed Swarthout · Wed Oct 29 09:21:44 2008 -0500
  18. d90e040 Add debug information for DDR controller registers by Haiying Wang · Fri Oct 03 12:37:26 2008 -0400
  19. b834f92 Check DDR interleaving mode by Haiying Wang · Fri Oct 03 12:37:10 2008 -0400
  20. fa44036 Pass dimm parameters to populate populate controller options by Haiying Wang · Fri Oct 03 12:36:55 2008 -0400
  21. 272b596 Make DDR interleaving mode work correctly by Haiying Wang · Fri Oct 03 12:36:39 2008 -0400
  22. 0383694 rename CFG_ macros to CONFIG_SYS by Jean-Christophe PLAGNIOL-VILLARD · Thu Oct 16 15:01:15 2008 +0200
  23. 9dbbd7b Coding style cleanup, update CHANGELOG by Wolfgang Denk · Sat Sep 13 02:23:05 2008 +0200
  24. 35ad58d Fix compiler warning in mpc8xxx ddr code by Kumar Gala · Fri Sep 05 14:40:29 2008 -0500
  25. fcf2884 FSL DDR: Add DDR2 DIMM paramter support by Kumar Gala · Tue Aug 26 15:01:32 2008 -0500
  26. 711d11b FSL DDR: Add DDR1 DIMM paramter support by Kumar Gala · Tue Aug 26 15:01:30 2008 -0500
  27. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · Tue Aug 26 15:01:29 2008 -0500