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git01.mediatek.com / filogic / uboot / b9ad45db58fc8520a46cbd8e0e602519110bef7d / arch / riscv / cpu
  1. b9ad45d riscv: update fix_rela_dyn by Marcus Comstedt · Sun Aug 11 14:45:29 2019 +0200
  2. 2a2a925 riscv: support SPL stack and global data relocation by Lukas Auer · Wed Aug 21 21:14:46 2019 +0200
  3. 396f0bd riscv: add SPL support by Lukas Auer · Wed Aug 21 21:14:45 2019 +0200
  4. 6134659 riscv: add run mode configuration for SPL by Lukas Auer · Wed Aug 21 21:14:43 2019 +0200
  5. f942636 riscv: Access CSRs using CSR numbers by Bin Meng · Wed Jul 10 23:43:13 2019 -0700
  6. 43ec7e0 CONFIG_SPL_SYS_[DI]CACHE_OFF: add by Trevor Woerner · Fri May 03 09:41:00 2019 -0400
  7. 3043b90 riscv: prior_stage_fdt_address should only be used when OF_PRIOR_STAGE is enabled by Rick Chen · Tue Apr 30 13:49:35 2019 +0800
  8. e5e6c36 riscv: Introduce CONFIG_XIP to support booting from flash by Rick Chen · Tue Apr 30 13:49:33 2019 +0800
  9. f71410a riscv: ax25: Andes specific cache shall only support in M-mode by Rick Chen · Tue Apr 02 15:56:42 2019 +0800
  10. 14a1075 riscv: ax25: Add platform-specific Kconfig options by Rick Chen · Tue Apr 02 15:56:41 2019 +0800
  11. cddde09 riscv: hang if relocation of secondary harts fails by Lukas Auer · Sun Mar 17 19:28:40 2019 +0100
  12. 9ebf294 riscv: do not rely on hart ID passed by previous boot stage by Lukas Auer · Sun Mar 17 19:28:39 2019 +0100
  13. a359665 riscv: add support for multi-hart systems by Lukas Auer · Sun Mar 17 19:28:37 2019 +0100
  14. 8de4b3e riscv: save hart ID in register tp instead of s0 by Lukas Auer · Sun Mar 17 19:28:36 2019 +0100
  15. 01558e2 riscv: delay initialization of caches and debug UART by Lukas Auer · Sun Mar 17 19:28:35 2019 +0100
  16. 0bbe9cf riscv: generic: Ensure that U-Boot runs within 4GB for 64bit systems by Anup Patel · Mon Feb 25 08:14:30 2019 +0000
  17. 1240cd6 riscv: Rename cpu/qemu to cpu/generic by Anup Patel · Mon Feb 25 08:14:10 2019 +0000
  18. 6280e32 riscv: move the AX25-specific implementation of flush_dcache_all by Lukas Auer · Fri Jan 04 01:37:29 2019 +0100
  19. 89681a7 riscv: Save boot hart id to the global data by Bin Meng · Wed Dec 12 06:12:45 2018 -0800
  20. 1f46f6d riscv: Return to previous privilege level after trap handling by Bin Meng · Wed Dec 12 06:12:43 2018 -0800
  21. ea95452 riscv: Fix context restore before returning from trap handler by Bin Meng · Wed Dec 12 06:12:42 2018 -0800
  22. 2e128a7 riscv: Move trap handler codes to mtrap.S by Bin Meng · Wed Dec 12 06:12:41 2018 -0800
  23. a7544ed riscv: Do some basic architecture level cpu initialization by Bin Meng · Wed Dec 12 06:12:40 2018 -0800
  24. edfe9a9 riscv: Update supports_extension() to use desc from cpu driver by Bin Meng · Wed Dec 12 06:12:38 2018 -0800
  25. 2caa1ee riscv: Remove non-DM version of print_cpuinfo() by Bin Meng · Wed Dec 12 06:12:35 2018 -0800
  26. 7a3bbfb riscv: Probe cpus during boot by Bin Meng · Wed Dec 12 06:12:34 2018 -0800
  27. 8fa4478 riscv: qemu: Add platform-specific Kconfig options by Bin Meng · Wed Dec 12 06:12:32 2018 -0800
  28. 4b284ad riscv: ax25: Hide the ax25-specific Kconfig option by Bin Meng · Wed Dec 12 06:12:28 2018 -0800
  29. 66c6935 riscv: qemu: Create a simple-bus driver for the soc node by Bin Meng · Wed Dec 12 06:12:25 2018 -0800
  30. 2a21815 riscv: ax25-ae350: Pass dtb address to u-boot with a1 register by Rick Chen · Mon Dec 03 17:48:20 2018 +0800
  31. 89b3934 riscv: Add kconfig option to run U-Boot in S-mode by Anup Patel · Mon Dec 03 10:57:40 2018 +0530
  32. 842d580 riscv: cache: Implement i/dcache [status, enable, disable] by Rick Chen · Wed Nov 07 09:34:06 2018 +0800
  33. 39a652b riscv: save hart ID and device tree passed by prior boot stage by Lukas Auer · Thu Nov 22 11:26:29 2018 +0100
  34. 8598e6b riscv: do not blindly modify the mstatus CSR by Lukas Auer · Thu Nov 22 11:26:28 2018 +0100
  35. 230ab8a riscv: remove unused labels in start.S by Lukas Auer · Thu Nov 22 11:26:27 2018 +0100
  36. ccd035a Drop CONFIG_INIT_CRITICAL by Bin Meng · Thu Nov 22 11:26:26 2018 +0100
  37. af51285 riscv: align mtvec on a 4-byte boundary by Lukas Auer · Thu Nov 22 11:26:25 2018 +0100
  38. 7cf4368 riscv: fix inconsistent use of spaces and tabs in start.S by Lukas Auer · Thu Nov 22 11:26:24 2018 +0100
  39. de8d80e riscv: Move do_reset() to a common place by Bin Meng · Wed Sep 26 06:55:22 2018 -0700
  40. 8a8694d riscv: Add QEMU virt board support by Bin Meng · Wed Sep 26 06:55:21 2018 -0700
  41. bcb3843 riscv: Make start.S available for all targets by Bin Meng · Wed Sep 26 06:55:17 2018 -0700
  42. 055700e riscv: Add a helper routine to print CPU information by Bin Meng · Wed Sep 26 06:55:14 2018 -0700
  43. c7feb19 riscv: Fix coding style issues in the linker script by Bin Meng · Wed Sep 26 06:55:12 2018 -0700
  44. a28e0f5 riscv: Move the linker script to the CPU root directory by Bin Meng · Wed Sep 26 06:55:11 2018 -0700
  45. b28f7b3 riscv: Include bss subsections in linker script by Alexander Graf · Mon Aug 20 14:25:49 2018 +0200
  46. 94a10f2 efi_loader: Rename sections to allow for implicit data by Alexander Graf · Tue Jun 12 07:48:37 2018 +0200
  47. b66af37 riscv: cpu: nx25: Rename as ax25 by Rick Chen · Tue May 29 09:54:40 2018 +0800
  48. 9677a37 efi_loader: Enable RISC-V support by Rick Chen · Mon May 28 19:06:37 2018 +0800
  49. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  50. 40a6fe7 riscv: ae250: Support DT provided by the board at runtime by Rick Chen · Thu Mar 29 10:08:33 2018 +0800
  51. e76b804 riscv: cpu: Add nx25 to support RISC-V by Rick Chen · Tue Dec 26 13:55:48 2017 +0800