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git01.mediatek.com / filogic / uboot / 943b13aa5de35b591d11c5b92616eabb2f07ad2d / arch / riscv
  1. 369d87a Add support for stack-protector by Joel Peshkin · Sun Apr 11 11:21:58 2021 +0200
  2. c88bdaa riscv: dts: mpfs-icicle-kit: Drop 'clock-frequency' in the uart nodes by Bin Meng · Wed Mar 31 15:24:50 2021 +0800
  3. 23caf66 riscv: assembler versions of memcpy, memmove, memset by Heinrich Schuchardt · Sat Mar 27 12:37:04 2021 +0100
  4. 76eb648 riscv: simplify longjmp by Heinrich Schuchardt · Tue Mar 23 19:11:26 2021 +0100
  5. e9ead4a riscv: sifive: Rename fu540 board to unleashed by Bin Meng · Wed Mar 17 11:10:58 2021 +0800
  6. 1c30c0e riscv: Add watchdog bindings for the k210 by Sean Anderson · Wed Mar 10 21:02:21 2021 -0500
  7. 2f00216 cpu: Rename SPL_CPU_SUPPORT to SPL_CPU by Simon Glass · Mon Mar 15 18:11:18 2021 +1300
  8. 0937c19 riscv: k210: Enable QSPI for spi3 by Sean Anderson · Thu Feb 04 23:11:19 2021 -0500
  9. b1db71b Merge branch '2021-02-02-drop-asm_global_data-when-unused' by Tom Rini · Mon Feb 15 08:19:40 2021 -0500
  10. 440b77f riscv: Change phys_addr_t and phys_size_t to 64-bit by Bin Meng · Sun Jan 31 20:36:04 2021 +0800
  11. 489b25a riscv: Adjust board_get_usable_ram_top() for 32-bit by Bin Meng · Sun Jan 31 20:35:57 2021 +0800
  12. 3ba929a common: Drop asm/global_data.h from common header by Simon Glass · Fri Oct 30 21:38:53 2020 -0600
  13. 5854c3d riscv: dts: Add device tree for Microchip Icicle Kit by Padmarao Begari · Fri Jan 15 08:20:39 2021 +0530
  14. a235d43 riscv: Add DMA 64-bit address support by Padmarao Begari · Fri Jan 15 08:20:35 2021 +0530
  15. bb721de Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into next by Tom Rini · Tue Jan 05 22:34:43 2021 -0500
  16. e6256ce Merge tag 'v2021.01-rc5' into next by Tom Rini · Tue Jan 05 16:20:26 2021 -0500
  17. 65130cd dm: Rename DM_GET_DRIVER() to DM_DRIVER_GET() by Simon Glass · Mon Dec 28 20:34:56 2020 -0700
  18. 2ddd3e0 riscv: Add device tree bindings for SPI by Sean Anderson · Fri Oct 16 18:57:54 2020 -0400
  19. fd9571a spi: dw: Add SoC-specific compatible strings by Sean Anderson · Fri Oct 16 18:57:50 2020 -0400
  20. dd5d79b riscv: Complete efi header for RV32/64 by Leo Yu-Chi Liang · Mon Nov 16 17:07:41 2020 +0800
  21. b68402d riscv: Fix efi header size for RV32 by Leo Yu-Chi Liang · Thu Nov 12 10:09:52 2020 +0800
  22. fa36696 riscv: Fix efi header for RV32 by Atish Patra · Tue Oct 13 12:23:31 2020 -0700
  23. b881ba8 riscv: reset after crash by Heinrich Schuchardt · Wed Dec 02 14:36:26 2020 +0100
  24. 4b96c88 riscv: fix the wrong swap value register by Brad Kim · Fri Nov 13 20:47:51 2020 +0900
  25. b75b15b dm: treewide: Rename ..._platdata variables to just ..._plat by Simon Glass · Thu Dec 03 16:55:23 2020 -0700
  26. 4f1b444 riscv: sifive/fu540: kconfig: Enable support for Opencores I2C controller by Pragnesh Patel · Sat Nov 14 14:42:35 2020 +0530
  27. 2dc5984 riscv: fu540: dts: Correct reg size of clint node by Pragnesh Patel · Tue Oct 20 11:03:02 2020 +0530
  28. 52a1db7 riscv: Move timer portions of SiFive CLINT to drivers/timer by Sean Anderson · Sun Oct 25 21:46:58 2020 -0400
  29. 5a23865 timer: Add _TIMER suffix to Andes PLMT Kconfig by Sean Anderson · Sun Oct 25 21:46:57 2020 -0400
  30. 5abf1f3 riscv: Move Andes PLMT driver to drivers/timer by Sean Anderson · Sun Oct 25 21:46:56 2020 -0400
  31. d1b3321 riscv: k210: Reduce DMA block size by Sean Anderson · Mon Oct 12 14:18:15 2020 -0400
  32. 584a5ee riscv: Only enable OF_BOARD_FIXUP for S-Mode by Sean Anderson · Sat Sep 05 09:22:11 2020 -0400
  33. 947fc2d timer: Return count from timer_ops.get_count by Sean Anderson · Wed Oct 07 14:37:44 2020 -0400
  34. 36d38fd riscv: add DT binding for BOOT button on Maix board by Heinrich Schuchardt · Mon Sep 14 11:02:05 2020 -0400
  35. 6870556 riscv: Add pinmux and gpio bindings for Kendryte K210 by Sean Anderson · Mon Sep 14 11:02:04 2020 -0400
  36. 38ae92e Merge branch 'next' by Tom Rini · Mon Oct 05 13:05:46 2020 -0400
  37. 5bdad9f riscv: Add some comments to start.S by Sean Anderson · Mon Sep 21 07:51:41 2020 -0400
  38. 2c4c7d1 riscv: Ensure gp is NULL or points to valid data by Sean Anderson · Mon Sep 21 07:51:40 2020 -0400
  39. 934b24a riscv: Consolidate fences into AMOs for available_harts_lock by Sean Anderson · Mon Sep 21 07:51:39 2020 -0400
  40. dd1cd70 riscv: Clear pending IPIs on initialization by Sean Anderson · Mon Sep 21 07:51:38 2020 -0400
  41. ff184fe riscv: Use a valid bit to ignore already-pending IPIs by Sean Anderson · Mon Sep 21 07:51:37 2020 -0400
  42. cfb0809 riscv: Match memory barriers between send_ipi_many and handle_ipi by Sean Anderson · Mon Sep 21 07:51:36 2020 -0400
  43. e8de08b Revert "riscv: Clear pending interrupts before enabling IPIs" by Sean Anderson · Mon Sep 21 07:51:35 2020 -0400
  44. 3d999194 riscv: Update SiFive device tree for new CLINT driver by Sean Anderson · Mon Sep 28 10:52:29 2020 -0400
  45. c6d0ef8 riscv: Update Kendryte device tree for new CLINT driver by Sean Anderson · Mon Sep 28 10:52:28 2020 -0400
  46. 272ab20 riscv: Rework Sifive CLINT as UCLASS_TIMER driver by Sean Anderson · Mon Sep 28 10:52:26 2020 -0400
  47. 28bfc32 riscv: Clean up initialization in Andes PLIC by Sean Anderson · Mon Sep 28 10:52:25 2020 -0400
  48. 87e6ce5 riscv: Rework Andes PLMT as a UCLASS_TIMER driver by Sean Anderson · Mon Sep 28 10:52:24 2020 -0400
  49. 9baaaef riscv: Rework riscv timer driver to only support S-mode by Sean Anderson · Mon Sep 28 10:52:21 2020 -0400
  50. fbef54d riscv: restore global data pointer in trap handler by Heinrich Schuchardt · Sat Sep 26 07:50:36 2020 +0200
  51. 646f8c6 fdtdec: optionally add property no-map to created reserved memory node by Etienne Carriere · Thu Sep 10 10:49:59 2020 +0200
  52. 6e7eb46 riscv: define function set_gd() by Heinrich Schuchardt · Thu Sep 10 07:47:39 2020 +0200
  53. 95492ae cmd: provide command sbi by Heinrich Schuchardt · Thu Aug 20 19:43:39 2020 +0200
  54. c78eef7 riscv: fix building with CONFIG_SPL_SMP=n by Heinrich Schuchardt · Sat Aug 15 09:49:26 2020 +0200
  55. 54bcf26 riscv: fu540: Use correct API to get L2 cache controller base address by Bin Meng · Tue Aug 18 01:09:20 2020 -0700
  56. 77efe24 riscv: additional crash information by Heinrich Schuchardt · Sat Aug 01 15:15:39 2020 +0000
  57. 03de50e riscv: sifive: fu540: redundant initialization by Heinrich Schuchardt · Mon Aug 03 23:09:49 2020 +0200
  58. d2014d1 riscv: remove redundant logical constraint. by Heinrich Schuchardt · Mon Aug 03 23:33:42 2020 +0200
  59. 6b15551 riscv: sifive/fu540: kconfig: Move FU540 driver related options to the SoC level by Bin Meng · Sun Aug 02 23:09:04 2020 -0700
  60. 2b2d9c4 riscv: sifive/fu540: spl: Rename soc_spl_init() by Bin Meng · Sun Aug 02 23:09:03 2020 -0700
  61. 63dcfcb riscv: Call spl_board_init_f() in the generic SPL board_init_f() by Bin Meng · Sun Aug 02 23:09:01 2020 -0700
  62. e1ff6eb sifive: reset: add DM based reset driver for SiFive SoC's by Sagar Shrikant Kadam · Wed Jul 29 02:36:13 2020 -0700
  63. b0357f4 fu540: dtsi: add reset producer and consumer entries by Sagar Shrikant Kadam · Wed Jul 29 02:36:12 2020 -0700
  64. a9e7ec5 riscv: dts: hifive-unleashed-a00: Make memory node available to SPL by Bin Meng · Sun Jul 19 23:06:34 2020 -0700
  65. 4e3ba2a riscv: Fix linking error when building u-boot-spl with no SMP support by Leo Yu-Chi Liang · Mon Jun 29 16:27:28 2020 +0800
  66. 3af8678 Revert "riscv: Allow use of reset drivers" by Bin Meng · Sun Jul 19 20:06:45 2020 -0700
  67. e70ef90 env: Enable SPI flash env for SiFive FU540 by Jagan Teki · Wed Jul 15 15:39:00 2020 +0530
  68. 05fb96d sifive: fu540: Add Booting from SPI by Jagan Teki · Wed Jul 15 15:38:59 2020 +0530
  69. 257875d riscv: Make SiFive HiFive Unleashed board boot again by Bin Meng · Sun Jul 19 23:17:07 2020 -0700
  70. 90fa4e9 Merge branch 'next' by Tom Rini · Mon Jul 06 15:46:38 2020 -0400
  71. 8cfbea0 riscv: use log functions in fdt_fixup by Heinrich Schuchardt · Tue Jun 30 11:30:59 2020 +0200
  72. 8a52128 riscv: sifive: fu540: enable all cache ways from U-Boot proper by Pragnesh Patel · Fri May 29 12:14:51 2020 +0530
  73. 491734f riscv: Use optimized version of fdtdec_get_addr_size_no_parent by Atish Patra · Wed Jun 24 14:56:15 2020 -0700
  74. f0947db riscv: Do not return error if reserved node already exists by Atish Patra · Wed Jun 24 14:56:14 2020 -0700
  75. c71f100 riscv: Do not build reset.c if SYSRESET is on by Bin Meng · Mon Jun 22 22:29:44 2020 -0700
  76. 2bdcd05 riscv: Enable CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATE by Bin Meng · Thu Jun 25 18:16:08 2020 -0700
  77. 7a36bd8 riscv: Expand the DT size before copy reserved memory node by Bin Meng · Thu Jun 25 18:16:07 2020 -0700
  78. 77073f4 riscv: Avoid the reserved memory fixup if src and dst point to the same place by Bin Meng · Thu Jun 25 18:16:06 2020 -0700
  79. 3961e14 riscv: fu540: dts: Correct reg size of otp and dmc nodes by Bin Meng · Mon Jun 08 20:28:26 2020 -0700
  80. e3870c8 riscv: fu540: dts: Remove the unnecessary space in the cpu2_intc node by Bin Meng · Mon Jun 08 20:28:25 2020 -0700
  81. d2b7f84 riscv: dts: hifive-unleashed-a00: add cpu aliases by Sagar Shrikant Kadam · Sun Jun 28 07:45:00 2020 -0700
  82. edc32ab riscv: Add Sipeed Maix support by Sean Anderson · Wed Jun 24 06:41:25 2020 -0400
  83. d11b582 riscv: Add device tree for K210 and Sipeed Maix BitM by Sean Anderson · Wed Jun 24 06:41:23 2020 -0400
  84. 35e14fb riscv: Allow use of reset drivers by Sean Anderson · Wed Jun 24 06:41:20 2020 -0400
  85. 7f4b666 riscv: Add option to support RISC-V privileged spec 1.9 by Sean Anderson · Wed Jun 24 06:41:19 2020 -0400
  86. b1d0cb3 riscv: Clean up IPI initialization code by Sean Anderson · Wed Jun 24 06:41:18 2020 -0400
  87. 84df2e1 riscv: Clear pending interrupts before enabling IPIs by Sean Anderson · Wed Jun 24 06:41:17 2020 -0400
  88. 5aa0074 riscv: Add headers for asm/global_data.h by Sean Anderson · Wed Jun 24 06:41:16 2020 -0400
  89. 0961ae8 bdinfo: riscv: Use generic bd_info by Simon Glass · Sun May 10 14:16:26 2020 -0600
  90. e622c74 riscv: sbi: Move sbi_probe_extension() out of CONFIG_SBI_V01 by Bin Meng · Wed May 27 02:04:53 2020 -0700
  91. b391ead riscv: sbi: Remove sbi_spec_version by Bin Meng · Wed May 27 02:04:52 2020 -0700
  92. e00653c riscv: sifive: fu540: add SPL configuration by Pragnesh Patel · Fri May 29 11:33:35 2020 +0530
  93. 25269c0 riscv: cpu: fu540: Add support for cpu fu540 by Pragnesh Patel · Fri May 29 11:33:34 2020 +0530
  94. 01ec498 riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux by Pragnesh Patel · Fri May 29 11:33:33 2020 +0530
  95. bb337f9 riscv: sifive: dts: fu540: set ethernet clock rate by Pragnesh Patel · Fri May 29 11:33:32 2020 +0530
  96. 45ffc91 riscv: sifive: dts: fu540: add U-Boot dmc node by Pragnesh Patel · Fri May 29 11:33:28 2020 +0530
  97. 8f4a403 sifive: dts: fu540: Add DDR controller and phy register settings by Pragnesh Patel · Fri May 29 11:33:27 2020 +0530
  98. b65f19f riscv: sifive: dts: fu540: Add board -u-boot.dtsi files by Pragnesh Patel · Fri May 29 11:33:25 2020 +0530
  99. 45b4ad9d riscv: Add _image_binary_end for SPL by Pragnesh Patel · Fri May 29 11:33:23 2020 +0530
  100. 2a449a3 riscv: sifive: fu540: Use OTP DM driver for serial environment variable by Pragnesh Patel · Fri May 29 11:33:22 2020 +0530