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git01.mediatek.com / filogic / uboot / 7d5d59154d16849e27718ad16d1dcceeb71ef765 / drivers / clk / renesas / renesas-cpg-mssr.h
  1. 86d59f3 clk: renesas: Add R8A779A0 clock tables by Hai Pham · Tue Aug 11 10:46:34 2020 +0700
  2. 9480346 clk: renesas: Add register pointers into struct cpg_mssr_info by Hai Pham · Thu Nov 05 22:30:37 2020 +0700
  3. 016a4c2 clk: renesas: Introduce enum clk_reg_layout by Hai Pham · Thu Nov 05 21:32:38 2020 +0700
  4. 5460ee0 clk: renesas: Pass struct cpg_mssr_info to renesas_clk_endisable() by Hai Pham · Fri May 22 10:39:04 2020 +0700
  5. 814217e clk: renesas: Make reset controller modemr register offset configurable by Marek Vasut · Sun Apr 25 21:53:05 2021 +0200
  6. 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · Sun May 10 11:40:13 2020 -0600
  7. 7841483 clk: renesas: Synchronize Gen3 tables with Linux 5.0 by Marek Vasut · Mon Mar 04 21:38:10 2019 +0100
  8. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  9. f63b295 clk: renesas: Add Gen2 clock core by Marek Vasut · Mon Jan 08 16:38:51 2018 +0100
  10. 32ae81e clk: renesas: Add DIV6P1 clock type by Marek Vasut · Thu Jan 18 00:05:28 2018 +0100
  11. e11008b clk: renesas: Split out code shared between Gen2 and Gen3 by Marek Vasut · Mon Jan 15 16:44:39 2018 +0100
  12. 2eb56a1 clk: renesas: Split SMSTPCR and RMSTPCR tables by Marek Vasut · Mon Jan 15 00:58:35 2018 +0100
  13. 7ef12c2 clk: renesas: Pull Gen3 specific bits into separate header by Marek Vasut · Mon Jan 08 17:09:45 2018 +0100
  14. 28f9004 clk: renesas: Make PLL configurations per-SoC by Marek Vasut · Tue Jan 16 19:23:17 2018 +0100
  15. b923419 clk: renesas: Make clk_ids per-driver by Marek Vasut · Mon Jan 08 16:05:28 2018 +0100
  16. 4eb4e6e clk: renesas: Split RCar Gen3 driver by Marek Vasut · Mon Jan 08 14:01:40 2018 +0100