Log - 7b170665da09036053f910f6d6b6a8ee0b9506d3 - filogic/uboot

e440ed4 configs: ae350: Enable v5l2 cache for AE350 platforms in SPL by Yu Chien Peter Lin · Mon Feb 06 16:10:50 2023 +0800
816979a riscv: Remove redundant Kconfig "RISCV_NDS_CACHE" by Leo Yu-Chi Liang · Mon Feb 06 16:10:44 2023 +0800
739cd6f riscv: Rename Andes PLIC to PLICSW by Yu Chien Peter Lin · Tue Oct 25 23:03:50 2022 +0800
2f00216 cpu: Rename SPL_CPU_SUPPORT to SPL_CPU by Simon Glass · Mon Mar 15 18:11:18 2021 +1300
5a23865 timer: Add _TIMER suffix to Andes PLMT Kconfig by Sean Anderson · Sun Oct 25 21:46:57 2020 -0400
9baaaef riscv: Rework riscv timer driver to only support S-mode by Sean Anderson · Mon Sep 28 10:52:21 2020 -0400
276292a riscv: ax25: add SPL support by Rick Chen · Thu Nov 14 13:52:21 2019 +0800
19117d2 riscv: ax25: add imply v5l2 cache controller by Rick Chen · Thu Aug 29 10:30:13 2019 +0800
6134659 riscv: add run mode configuration for SPL by Lukas Auer · Wed Aug 21 21:14:43 2019 +0200
f71410a riscv: ax25: Andes specific cache shall only support in M-mode by Rick Chen · Tue Apr 02 15:56:42 2019 +0800
14a1075 riscv: ax25: Add platform-specific Kconfig options by Rick Chen · Tue Apr 02 15:56:41 2019 +0800
4b284ad riscv: ax25: Hide the ax25-specific Kconfig option by Bin Meng · Wed Dec 12 06:12:28 2018 -0800
842d580 riscv: cache: Implement i/dcache [status, enable, disable] by Rick Chen · Wed Nov 07 09:34:06 2018 +0800