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git01.mediatek.com / filogic / uboot / 72c5827f8f73526e8aead84d52aba9d65318f98e / drivers / clk / renesas
  1. 68f1ac0 clk: renesas: Add R8A779G0 V4H clock tables by Hai Pham · Tue Feb 28 22:37:02 2023 +0100
  2. 99d4039 clk: renesas: Add R8A779F0 S4 clock tables by Hai Pham · Tue Feb 28 22:34:39 2023 +0100
  3. ba2c7d2 clk: renesas: Update R-Car Gen3 driver Gen4 support by Marek Vasut · Tue Feb 28 22:34:38 2023 +0100
  4. f5e6084 Merge branch 'master' into next by Tom Rini · Mon Mar 27 15:19:57 2023 -0400
  5. ef5c0b1 clk: renesas: Pack reset identifier before look up by Marek Vasut · Sat Mar 18 12:30:53 2023 +0100
  6. ea8505e clk: renesas: rcar-gen3: Replace SSCG caching with MDSEL/PE caching by Marek Vasut · Tue Feb 28 07:25:11 2023 +0100
  7. 3e55ce3 clk: renesas: Always select DM_RESET to prevent inobvious failure of rst_gen3 subdriver by Marek Vasut · Tue Feb 28 22:16:02 2023 +0100
  8. 06d8f97 clk: renesas: rcar-gen3: Factor out CPG library by Hai Pham · Thu Jan 26 21:06:07 2023 +0100
  9. 6811b57 clk: renesas: Add R8A77970 SD0H/SD0 clocks for SDHI by Hai Pham · Thu Jan 26 21:06:06 2023 +0100
  10. 4dae076 clk: renesas: Switch to new SD clock handling by Hai Pham · Sun Jan 29 02:50:22 2023 +0100
  11. 85e691e clk: renesas: Handle E3/D3 RPCSRC clock by Hai Pham · Thu Jan 26 21:06:04 2023 +0100
  12. e83700a clk: renesas: Introduce and use rcar_clk_get_rate64_div_table function by Hai Pham · Thu Jan 26 21:06:03 2023 +0100
  13. b2970fd clk: renesas: Convert Gen2/Gen3 clock tables to clk-provider struct clk_div_table by Marek Vasut · Thu Jan 26 21:06:02 2023 +0100
  14. 1bd2521 clk: renesas: Drop core param from gen3_clk_get_rate64_pll_mul_reg by Marek Vasut · Thu Jan 26 21:02:05 2023 +0100
  15. a80b061 clk: renesas: Use pre-defined offset for RPC clocks by Hai Pham · Thu Jan 26 21:02:04 2023 +0100
  16. f6b3202 clk: renesas: Add and enable CPG reset driver by Marek Vasut · Thu Jan 26 21:02:03 2023 +0100
  17. f144d50 clk: renesas: r8a7796: Add R8A77961 CPG/MSSR support by Hai Pham · Thu Jan 26 21:02:02 2023 +0100
  18. cef5c2f clk: renesas: Rename CLK_R8A7796 to CLK_R8A77960 by Hai Pham · Thu Jan 26 21:02:01 2023 +0100
  19. ffdcb5d clk: renesas: Synchronize R8A774E1 RZ/G2H clock tables with Linux 6.1.7 by Marek Vasut · Sun Jan 29 02:37:50 2023 +0100
  20. d4b102a clk: renesas: Synchronize R8A774C0 RZ/G2E clock tables with Linux 6.1.7 by Marek Vasut · Thu Jan 26 21:01:59 2023 +0100
  21. 43b3fdb clk: renesas: Synchronize R8A774B1 RZ/G2N clock tables with Linux 6.1.7 by Marek Vasut · Thu Jan 26 21:01:58 2023 +0100
  22. 7883e0d clk: renesas: Synchronize R8A774A1 RZ/G2M clock tables with Linux 6.1.7 by Marek Vasut · Thu Jan 26 21:01:57 2023 +0100
  23. 569acef clk: renesas: Synchronize R8A779A0 V3U clock tables with Linux 6.1.7 by Marek Vasut · Thu Jan 26 21:01:56 2023 +0100
  24. d1ff7e0 clk: renesas: Synchronize R8A77995 D3 clock tables with Linux 6.1.7 by Marek Vasut · Thu Jan 26 21:01:55 2023 +0100
  25. fdc9314 clk: renesas: Synchronize R8A77990 E3 clock tables with Linux 6.1.7 by Marek Vasut · Thu Jan 26 21:01:54 2023 +0100
  26. c3bb162 clk: renesas: Synchronize R8A77980 V3H clock tables with Linux 6.1.7 by Marek Vasut · Thu Jan 26 21:01:53 2023 +0100
  27. d5b2e95 clk: renesas: Synchronize R8A77965 M3-N clock tables with Linux 6.1.7 by Marek Vasut · Thu Jan 26 21:01:52 2023 +0100
  28. fd44059 clk: renesas: Synchronize R8A77960 M3-W and R8A77961 M3-W+ clock tables with Linux 6.1.7 by Marek Vasut · Thu Jan 26 21:01:51 2023 +0100
  29. ade5532 clk: renesas: Synchronize R8A7795 H3 clock tables with Linux 6.1.7 by Marek Vasut · Thu Jan 26 21:01:50 2023 +0100
  30. 0985e0e clk: renesas: Add dummy SDnH clock by Hai Pham · Thu Jan 26 21:01:49 2023 +0100
  31. a1b654b treewide: invaild -> invalid by Sean Anderson · Wed Dec 01 14:26:53 2021 -0500
  32. 86d59f3 clk: renesas: Add R8A779A0 clock tables by Hai Pham · Tue Aug 11 10:46:34 2020 +0700
  33. 0fbb8a7 clk: renesas: Handle R8A779A0 V3U clock types in Gen3 clock code by Marek Vasut · Tue Apr 27 19:52:53 2021 +0200
  34. 8f56786 clk: renesas: Deduplicate gen3_clk_get_rate64() PLL handling by Marek Vasut · Tue Apr 27 19:36:39 2021 +0200
  35. 9480346 clk: renesas: Add register pointers into struct cpg_mssr_info by Hai Pham · Thu Nov 05 22:30:37 2020 +0700
  36. 016a4c2 clk: renesas: Introduce enum clk_reg_layout by Hai Pham · Thu Nov 05 21:32:38 2020 +0700
  37. 5460ee0 clk: renesas: Pass struct cpg_mssr_info to renesas_clk_endisable() by Hai Pham · Fri May 22 10:39:04 2020 +0700
  38. 814217e clk: renesas: Make reset controller modemr register offset configurable by Marek Vasut · Sun Apr 25 21:53:05 2021 +0200
  39. 215de2b clk: renesas: Add support for RPCD2 clock by Hai Pham · Tue Aug 11 10:25:28 2020 +0700
  40. 1a61896 clk: renesas: Fix Realtime Module Stop Control Register offsets by Hai Pham · Tue May 19 17:42:05 2020 +0700
  41. f2279df clk: renesas: Fix incorrect return RPC clk_get_rate by Hai Pham · Sat Dec 05 09:35:40 2020 +0700
  42. f5fec9d clk: renesas: Reinstate RPC clock on R-Car D3/E3 by Marek Vasut · Sun Apr 25 21:26:22 2021 +0200
  43. 0e8dcb7 clk: renesas: Synchronize R-Car Gen3 tables with Linux 5.12 by Marek Vasut · Sun Apr 25 21:10:40 2021 +0200
  44. aac4de2 clk: renesas: Synchronize R-Car Gen2 tables with Linux 5.12 by Marek Vasut · Sun Apr 25 21:09:10 2021 +0200
  45. 8538d53 clk: renesas: Synchronize RZ/G2 tables with Linux 5.12 by Marek Vasut · Sun Apr 25 21:08:18 2021 +0200
  46. 5af8b6a clk: renesas: Synchronize Gen2 MSTP teardown tables by Marek Vasut · Sat Jun 06 15:26:14 2020 +0200
  47. 22f9fc7 clk: renesas: Only ever access documented bits in clock driver teardown by Marek Vasut · Sat Apr 25 14:57:45 2020 +0200
  48. 3ba929a common: Drop asm/global_data.h from common header by Simon Glass · Fri Oct 30 21:38:53 2020 -0600
  49. 8a2b47f dm: treewide: Rename auto_alloc_size members to be shorter by Simon Glass · Thu Dec 03 16:55:17 2020 -0700
  50. 3434a5f clk: renesas: Import R8A774C0 clock tables from Linux 5.9 by Lad Prabhakar · Fri Oct 16 08:37:14 2020 +0100
  51. eb6474c clk: renesas: Add R8A774E1 clock tables by Biju Das · Wed Oct 14 18:17:36 2020 +0100
  52. 69159a2 clk: renesas: Add R8A774B1 clock tables by Biju Das · Wed Oct 14 18:17:35 2020 +0100
  53. 161bf54 clk: renesas: r8a774a1-cpg-mssr: Add R8A774A1 RPC clock by Biju Das · Tue Sep 29 11:09:44 2020 +0100
  54. 48de37a Merge tag 'dm-pull-20jul20-take2a' of https://gitlab.denx.de/u-boot/custodians/u-boot-dm by Tom Rini · Mon Jul 27 11:15:37 2020 -0400
  55. 1096ae1 treewide: convert (void *)devfdt_get_addr() to dev_read_addr_ptr() by Masahiro Yamada · Fri Jul 17 14:36:46 2020 +0900
  56. 06c4f9b clk: renesas: Add R8A774A1 clock tables by Adam Ford · Tue Jun 30 09:30:08 2020 -0500
  57. 5a9ecb2 Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm" by Tom Rini · Fri Jul 24 08:42:06 2020 -0400
  58. a3332a1 treewide: convert (void *)devfdt_get_addr() to dev_read_addr_ptr() by Masahiro Yamada · Fri Jul 17 14:36:46 2020 +0900
  59. 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · Sun May 10 11:40:13 2020 -0600
  60. 0f2af88 common: Drop log.h from common header by Simon Glass · Sun May 10 11:40:05 2020 -0600
  61. ab11876 clk: renesas: Switch to fdtdec_get_addr_size_auto_noparent() on Gen2 by Marek Vasut · Sat Mar 21 16:45:29 2020 +0100
  62. d52c6cb clk: renesas: Add R8A77980 V3H clock tables by Marek Vasut · Mon Jul 29 19:59:44 2019 +0200
  63. 7841483 clk: renesas: Synchronize Gen3 tables with Linux 5.0 by Marek Vasut · Mon Mar 04 21:38:10 2019 +0100
  64. 3bee488 clk: renesas: Synchronize Gen2 tables with Linux 5.0 by Marek Vasut · Mon Mar 04 21:23:25 2019 +0100
  65. 98c2058 clk: renesas: Add R8A77965 clock tables by Marek Vasut · Mon Mar 04 13:36:13 2019 +0100
  66. 0f6aa07 clk: renesas: Add support for setting MMCIF clock divider on Gen2 by Marek Vasut · Mon Mar 18 06:04:02 2019 +0100
  67. 31872db clk: renesas: Fix swapped div and mul in debug output on Gen2 by Marek Vasut · Mon Mar 18 05:38:08 2019 +0100
  68. 272daa7 clk: renesas: Fix SDH clock divider decoding on Gen2 by Marek Vasut · Mon Mar 18 05:11:42 2019 +0100
  69. d0bb61b clk: rmobile: Drop def_bool per SoC by Marek Vasut · Mon Feb 18 13:22:47 2019 +0100
  70. c26bf89 clk: renesas: Allow reconfiguring SDHI clock on Gen3 by Marek Vasut · Tue Oct 30 17:54:20 2018 +0100
  71. 2447b74 clk: rmobile: Add R8A77995 RPC clock by Marek Vasut · Thu Jun 14 05:26:31 2018 +0200
  72. 69be062 clk: rmobile: Add R8A77990 RPC clock by Marek Vasut · Wed Jun 13 21:25:24 2018 +0200
  73. 2467224 Merge branch 'master' of git://git.denx.de/u-boot-sh by Tom Rini · Fri Jun 01 21:10:18 2018 -0400
  74. a6b456d clk: renesas: Add R8A77990 E3 clock tables by Marek Vasut · Thu Apr 26 10:19:03 2018 +0200
  75. 69459b2 clk: renesas: Add PE clock handling by Marek Vasut · Thu May 31 19:47:42 2018 +0200
  76. 52389f0 clk: renesas: Add PLL1 and PLL3 dividers by Marek Vasut · Thu May 31 19:25:41 2018 +0200
  77. 7571ac4 clk: renesas: Pass clock rate around as 64bit number internally by Marek Vasut · Thu May 31 19:06:02 2018 +0200
  78. 31de3d8 clk: renesas: Fix swapped arguments in debug message by Marek Vasut · Thu May 31 18:56:35 2018 +0200
  79. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  80. 031f404 clk: renesas: Drop USB extal from the R8A7792 clock driver by Marek Vasut · Wed May 02 10:48:15 2018 +0200
  81. dada109 clk: renesas: Minor clean up of the R8A7794 clock driver by Marek Vasut · Sat Apr 21 16:35:49 2018 +0200
  82. f5ff753 clk: renesas: Minor clean up of the R8A7792 clock driver by Marek Vasut · Sat Apr 21 16:36:54 2018 +0200
  83. f40c4cf clk: renesas: Minor clean up of the R8A7790 clock driver by Marek Vasut · Thu Apr 12 15:23:46 2018 +0200
  84. 284e94c clk: renesas: Add R8A77965 M3N entries by Marek Vasut · Mon Feb 26 10:35:15 2018 +0100
  85. 414dbbe clk: rmobile: Assure SD-IF clock are configured correctly by Marek Vasut · Thu Jan 11 16:28:31 2018 +0100
  86. 357f199 Merge branch 'rmobile-mx' of git://git.denx.de/u-boot-sh by Tom Rini · Sat Jan 27 14:50:52 2018 -0500
  87. 3fd0b09 clk: renesas: Import R8A7794 E2 clock tables by Marek Vasut · Wed Jan 17 23:39:57 2018 +0100
  88. 5f854a3 clk: renesas: Import R8A7792 V2H clock tables by Marek Vasut · Wed Jan 17 23:39:10 2018 +0100
  89. efa4fb1 clk: renesas: Import R8A7791/R8A7793 M2 clock tables by Marek Vasut · Mon Jan 08 16:38:51 2018 +0100
  90. b8379d6 clk: renesas: Import R8A7790 H2 clock tables by Marek Vasut · Wed Jan 17 23:14:25 2018 +0100
  91. f63b295 clk: renesas: Add Gen2 clock core by Marek Vasut · Mon Jan 08 16:38:51 2018 +0100
  92. 32ae81e clk: renesas: Add DIV6P1 clock type by Marek Vasut · Thu Jan 18 00:05:28 2018 +0100
  93. e11008b clk: renesas: Split out code shared between Gen2 and Gen3 by Marek Vasut · Mon Jan 15 16:44:39 2018 +0100
  94. 1a10f19 clk: renesas: Make clock tables Kconfig configurable by Marek Vasut · Mon Jan 08 16:32:38 2018 +0100
  95. 2eb56a1 clk: renesas: Split SMSTPCR and RMSTPCR tables by Marek Vasut · Mon Jan 15 00:58:35 2018 +0100
  96. 7ef12c2 clk: renesas: Pull Gen3 specific bits into separate header by Marek Vasut · Mon Jan 08 17:09:45 2018 +0100
  97. 28f9004 clk: renesas: Make PLL configurations per-SoC by Marek Vasut · Tue Jan 16 19:23:17 2018 +0100
  98. b923419 clk: renesas: Make clk_ids per-driver by Marek Vasut · Mon Jan 08 16:05:28 2018 +0100
  99. 4eb4e6e clk: renesas: Split RCar Gen3 driver by Marek Vasut · Mon Jan 08 14:01:40 2018 +0100
  100. 918de03 wait_bit: use wait_for_bit_le32 and remove wait_for_bit by Álvaro Fernández Rojas · Tue Jan 23 17:14:55 2018 +0100