Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 68ef4bdd0cc36155541e3b0466d16ca86f54e9c7 / cpu / mpc8xxx / ddr / ctrl_regs.c
  1. 68ef4bd fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT by Kumar Gala · 15 years ago
  2. 4be87b2 fsl-ddr: add the DDR3 SPD infrastructure by Dave Liu · 16 years ago
  3. 82aa953 fsl-ddr: Fix two bugs in the ddr infrastructure by Dave Liu · 16 years ago
  4. 2aad0ae fsl-ddr: make the self refresh idle threshold configurable by Dave Liu · 16 years ago
  5. 4758d53 fsl-ddr: clean up the ddr code for DDR3 controller by Dave Liu · 16 years ago
  6. 5c1bb51 fsl-ddr: update the bit mask for DDR3 controller by Dave Liu · 16 years ago
  7. d90e040 Add debug information for DDR controller registers by Haiying Wang · 16 years ago
  8. 272b596 Make DDR interleaving mode work correctly by Haiying Wang · 16 years ago
  9. 35ad58d Fix compiler warning in mpc8xxx ddr code by Kumar Gala · 16 years ago
  10. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · 16 years ago