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git01.mediatek.com / filogic / uboot / 625b26821d085123b57855e778057456aa098db7 / cpu / mpc8xxx / ddr / ctrl_regs.c
  1. 625b268 fsl-ddr: setup ODT_RD_CFG & ODT_WR_CFG when we interleave by Dave Liu · Wed Dec 16 10:24:39 2009 -0600
  2. 2d0f125 fsl-ddr: add override for the Rtt_Wr by Dave Liu · Wed Dec 16 10:24:38 2009 -0600
  3. 64ee7df fsl-ddr: add the override for write leveling by Dave Liu · Wed Dec 16 10:24:37 2009 -0600
  4. c7d983a fsl-ddr: Fix power-down timing settings by Dave Liu · Wed Dec 16 10:24:36 2009 -0600
  5. 14f2eb1 ppc/8xxx: Misc DDR related fixes by Kumar Gala · Thu Sep 10 14:54:55 2009 -0500
  6. 24aa71a ppc/8xxx: Remove ddr_pd_cntl register since it doesn't exist by Kumar Gala · Tue Sep 01 22:01:54 2009 -0500
  7. 68ef4bd fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BIT by Kumar Gala · Thu Jun 11 23:42:35 2009 -0500
  8. 4be87b2 fsl-ddr: add the DDR3 SPD infrastructure by Dave Liu · Sat Mar 14 12:48:30 2009 +0800
  9. 82aa953 fsl-ddr: Fix two bugs in the ddr infrastructure by Dave Liu · Sat Mar 14 12:48:19 2009 +0800
  10. 2aad0ae fsl-ddr: make the self refresh idle threshold configurable by Dave Liu · Fri Nov 21 16:31:35 2008 +0800
  11. 4758d53 fsl-ddr: clean up the ddr code for DDR3 controller by Dave Liu · Fri Nov 21 16:31:29 2008 +0800
  12. 5c1bb51 fsl-ddr: update the bit mask for DDR3 controller by Dave Liu · Fri Nov 21 16:31:22 2008 +0800
  13. d90e040 Add debug information for DDR controller registers by Haiying Wang · Fri Oct 03 12:37:26 2008 -0400
  14. 272b596 Make DDR interleaving mode work correctly by Haiying Wang · Fri Oct 03 12:36:39 2008 -0400
  15. 35ad58d Fix compiler warning in mpc8xxx ddr code by Kumar Gala · Fri Sep 05 14:40:29 2008 -0500
  16. 124b082 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. by Kumar Gala · Tue Aug 26 15:01:29 2008 -0500