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git01.mediatek.com / filogic / uboot / 60b78045592ec9ecd1f011c6496e610043440c3f / arch / riscv / cpu / ax25 / Kconfig
  1. 2f00216 cpu: Rename SPL_CPU_SUPPORT to SPL_CPU by Simon Glass · Mon Mar 15 18:11:18 2021 +1300
  2. 5a23865 timer: Add _TIMER suffix to Andes PLMT Kconfig by Sean Anderson · Sun Oct 25 21:46:57 2020 -0400
  3. 9baaaef riscv: Rework riscv timer driver to only support S-mode by Sean Anderson · Mon Sep 28 10:52:21 2020 -0400
  4. 276292a riscv: ax25: add SPL support by Rick Chen · Thu Nov 14 13:52:21 2019 +0800
  5. 19117d2 riscv: ax25: add imply v5l2 cache controller by Rick Chen · Thu Aug 29 10:30:13 2019 +0800
  6. 6134659 riscv: add run mode configuration for SPL by Lukas Auer · Wed Aug 21 21:14:43 2019 +0200
  7. f71410a riscv: ax25: Andes specific cache shall only support in M-mode by Rick Chen · Tue Apr 02 15:56:42 2019 +0800
  8. 14a1075 riscv: ax25: Add platform-specific Kconfig options by Rick Chen · Tue Apr 02 15:56:41 2019 +0800
  9. 4b284ad riscv: ax25: Hide the ax25-specific Kconfig option by Bin Meng · Wed Dec 12 06:12:28 2018 -0800
  10. 842d580 riscv: cache: Implement i/dcache [status, enable, disable] by Rick Chen · Wed Nov 07 09:34:06 2018 +0800