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git01.mediatek.com / filogic / uboot / 6086d7f43559c1536408e22231bf1791e4fe86f0 / drivers / clk / rockchip / clk_rk3368.c
  1. 9bc1564 dm: core: Create a new header file for 'compat' features by Simon Glass · Mon Feb 03 07:36:16 2020 -0700
  2. 416f8d3 rockchip: clk: fix wrong CONFIG_IS_ENABLED handling by Heiko Stuebner · Sat Nov 09 00:06:30 2019 +0100
  3. 3045dc2 rockchip: clk: rk3368: remove clk_enable() by Kever Yang · Wed Aug 28 16:23:50 2019 +0800
  4. 9fbe17c rockchip: use 'arch-rockchip' as header file path by Kever Yang · Thu Mar 28 11:01:23 2019 +0800
  5. 10e4779 SPDX: Convert all of our single license tags to Linux Kernel style by Tom Rini · Sun May 06 17:58:06 2018 -0400
  6. bdfb5c4 Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTR by Tom Rini · Wed Apr 18 13:50:47 2018 -0400
  7. 9ffb695 rockchip: clk: rk3368: handle clk_enable requests for GMAC by Philipp Tomsich · Fri Feb 16 16:07:25 2018 +0100
  8. 6dd2fb4 rockchip: clk: guard set_parent implementations against OF_PLATDATA by Philipp Tomsich · Thu Jan 25 15:27:10 2018 +0100
  9. e72793d clk: rockchip: clk_rk3368: Implement "assign-clock-parent" by David Wu · Sat Jan 13 14:07:04 2018 +0800
  10. 432976f rockchip: clk: bind reset driver by Elaine Zhang · Tue Dec 19 18:22:38 2017 +0800
  11. 4fbb6c2 rockchip: clock: update sysreset driver binding by Kever Yang · Fri Nov 03 15:16:13 2017 +0800
  12. 81e1042 treewide: replace with error() with pr_err() by Masahiro Yamada · Sat Sep 16 14:10:41 2017 +0900
  13. 4771ba6 rockchip: clk: Add rk3368 SARADC clock support by David Wu · Wed Sep 20 14:37:50 2017 +0800
  14. 5355999 rockchip: clk: rk3368: Convert to livetree by Philipp Tomsich · Mon Sep 11 22:04:18 2017 +0200
  15. 1b1fe41 dtoc: Add support for 32 or 64-bit addresses by Simon Glass · Tue Aug 29 14:15:50 2017 -0600
  16. f20995b rockchip: clk: remove RATE_TO_DIV by Kever Yang · Thu Jul 27 12:54:02 2017 +0800
  17. b4fb55f rockchip: clk: rk3368: add support for configuring the SPI clocks by Philipp Tomsich · Tue Jul 25 16:48:16 2017 +0200
  18. 83a5d2c rockchip: clk: rk3368: mark 'priv' __maybe_unused in rk3368_clk_set_rate() by Philipp Tomsich · Wed Jul 05 12:11:58 2017 +0200
  19. a249f10 rockchip: clk: rk3368: add support for GMAC (SLCK_MAC) clock by Philipp Tomsich · Fri Jul 14 19:57:39 2017 +0200
  20. c23a993 rockchip: clk: rk3368: support configuring the DRAM PLL (from TPL) by Philipp Tomsich · Wed Jul 05 11:55:23 2017 +0200
  21. fbf07a5 rockchip: clk: rk3368: implement MMC/SD clock reparenting by Philipp Tomsich · Tue Jul 04 14:49:38 2017 +0200
  22. 313b2da rockchip: clk: rk3368: implement DPLL (DRAM PLL) support by Philipp Tomsich · Fri Jun 23 00:01:10 2017 +0200
  23. 415ff7e rockchip: clk: rk3368: do not change CPLL/GPLL before returning to BROM by Philipp Tomsich · Thu Jun 22 23:53:44 2017 +0200
  24. 79aa1ab rockchip: clk: rk3368: support OF_PLATDATA for the RK3368 clk driver by Philipp Tomsich · Thu Jun 22 23:51:37 2017 +0200
  25. 34b7613 rockchip: clk: rk3368: implement bandwidth adjust for PLLs by Philipp Tomsich · Thu Jun 22 23:47:11 2017 +0200
  26. ea825a3 rockchip: clk: rk3368: use correct (i.e. 'rk3368_clk_priv') structure for auto-alloc by Philipp Tomsich · Tue Jul 11 20:59:45 2017 +0200
  27. b9909aa rockchip: rk3368: Add clock driver by Andy Yan · Mon May 15 17:49:56 2017 +0800