| commit | 313b2daebda690a7692ce1e3e6bf3c368247737a | [log] [tgz] |
|---|---|---|
| author | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | Fri Jun 23 00:01:10 2017 +0200 |
| committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | Sun Aug 13 17:12:32 2017 +0200 |
| tree | 9494c847f063d2baf3c4d94bac4cb0b7e683d566 | |
| parent | 415ff7e99ef809d83c755f99ac9a851fcfd378fc [diff] |
rockchip: clk: rk3368: implement DPLL (DRAM PLL) support To implement a TPL stage (incl. its DRAM controller setup) for the RK3368, we'll want to configure the DPLL (DRAM PLL). This commit implements setting the DPLL (CLK_DDR) and provides PLL configuration details for the common DRAM operating speeds found on RK3368 boards. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>