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filogic
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uboot
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5ac3486fc686625baae7e3bddac707636b041da6
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arch
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riscv
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include
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asm
929c820
riscv: io.h: Fix signatures of reads/writes functions
by Igor Prusov
· Tue Nov 14 14:02:50 2023 +0300
cde3882
riscv: io.h: Add defines for reads/writes functions
by Igor Prusov
· Tue Nov 14 14:02:49 2023 +0300
d1898ce
riscv: import read/write_relaxed functions
by Chanho Park
· Wed Nov 01 21:16:48 2023 +0900
a23ab3d
riscv: cpu: jh7110: Add gpio helper macros
by Chanho Park
· Tue Oct 31 17:55:59 2023 +0900
b6b9900
riscv: Remove common.h usage
by Tom Rini
· Thu Oct 12 19:03:59 2023 -0400
60814cb
riscv: Add Zbb support for building U-Boot
by Yu Chien Peter Lin
· Wed Aug 09 18:49:30 2023 +0800
b29a747
Merge branch 'next'
by Tom Rini
· Mon Oct 02 10:55:44 2023 -0400
9b38810
Record the position of the SMBIOS tables
by Simon Glass
· Tue Sep 19 21:00:15 2023 -0600
a7289b6
risc-v: implement DBCN write byte
by Heinrich Schuchardt
· Mon Sep 04 13:24:03 2023 +0200
b8357c1
event: Convert existing spy records to simple
by Simon Glass
· Mon Aug 21 21:16:56 2023 -0600
70884d7
cmd/sbi: display new extensions
by Heinrich Schuchardt
· Wed Aug 02 22:39:46 2023 +0200
4cf9986
acpi: Add missing RISC-V acpi_table header
by Heinrich Schuchardt
· Wed Jul 26 08:05:13 2023 +0200
b5f0372
riscv: Rename SiFive CLINT to RISC-V ALINT
by Bin Meng
· Wed Jun 21 23:11:46 2023 +0800
39331e4
eeprom: starfive: Enable ID EEPROM configuration
by Yanhong Wang
· Thu Jun 15 17:36:48 2023 +0800
ad168d6
riscv: define test_and_{set,clear}_bit in asm/bitops.h
by Ben Dooks
· Fri May 05 09:02:07 2023 +0100
0cd077d
riscv: implement local_irq_{save,restore} macros
by Ben Dooks
· Fri May 05 09:02:06 2023 +0100
17f6b11
riscv: add generic link for <asm/atomic.h>
by Ben Dooks
· Fri May 05 09:02:05 2023 +0100
cd464d1
cmd/sbi: display new extensions
by Heinrich Schuchardt
· Wed Apr 12 10:38:16 2023 +0200
bd05090
common: spl: Add spl NVMe boot support
by Mayuresh Chitale
· Sat Jun 03 19:32:56 2023 +0530
e6618f4
include: Remove unused header files
by Tom Rini
· Tue May 16 12:34:47 2023 -0400
b5399d9
riscv: Correct a comment in io.h
by Bin Meng
· Mon Apr 03 11:37:32 2023 +0800
e28ec34
riscv: cpu: jh7110: Add support for jh7110 SoC
by Yanhong Wang
· Wed Mar 29 11:42:08 2023 +0800
82f0f53
riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()
by Yu Chien Peter Lin
· Mon Feb 06 16:10:47 2023 +0800
52d54e1
riscv: global_data.h: Correct the comment for PLICSW
by Yu Chien Peter Lin
· Mon Feb 06 10:06:29 2023 +0800
364d002
global: Finish CONFIG -> CFG migration
by Tom Rini
· Tue Jan 10 11:19:45 2023 -0500
c86cb4a
arch/riscv: add semihosting support for RISC-V
by Kautuk Consul
· Wed Dec 07 17:12:35 2022 +0530
739cd6f
riscv: Rename Andes PLIC to PLICSW
by Yu Chien Peter Lin
· Tue Oct 25 23:03:50 2022 +0800
9c4d5c1
riscv: Introduce AVAILABLE_HARTS
by Rick Chen
· Wed Sep 21 14:34:54 2022 +0800
7e5e029
spl: introduce SPL_XIP to config
by Nikita Shubin
· Fri Sep 02 11:47:39 2022 +0300
94b4fec
Convert CONFIG_SYS_BOOT_RAMDISK_HIGH to Kconfig
by Tom Rini
· Sat Jun 25 11:02:46 2022 -0400
53a442a
riscv: Clean up asm/io.h
by Leo Yu-Chi Liang
· Thu May 19 16:43:31 2022 +0800
7a35171
riscv: remove CONFIG_ARCH_MAP_SYSMEM from io.h
by Michal Simek
· Wed May 18 12:54:01 2022 +0200
f4b4d75
riscv: provide missing base extension functions
by Heinrich Schuchardt
· Thu Mar 17 07:36:14 2022 +0100
295e1ce
cmd: sbi: add Performance Monitoring Unit Extension
by Heinrich Schuchardt
· Wed Mar 16 21:21:18 2022 +0100
fc55736
event: Convert arch_cpu_init_dm() to use events
by Simon Glass
· Fri Mar 04 08:43:05 2022 -0700
47b4c02
doc: replace @return by Return:
by Heinrich Schuchardt
· Wed Jan 19 18:05:50 2022 +0100
2f5b807
riscv: add #define in asm/io.h for some device drivers
by Wei Fu
· Sun Oct 24 00:31:12 2021 +0800
69c681e
riscv: function to retrieve SBI implementation version
by Heinrich Schuchardt
· Mon Oct 25 15:09:34 2021 +0200
579f12b
riscv: Avoid io read/write cause wrong result
by Nick Hu
· Mon Oct 18 11:50:05 2021 +0800
cc382ff
sysreset: provide SBI based sysreset driver
by Heinrich Schuchardt
· Sun Sep 12 21:11:46 2021 +0200
2d1c651
riscv: add missing SBI extension definitions
by Heinrich Schuchardt
· Sun Sep 12 21:11:44 2021 +0200
b28d6b9
riscv: lib: modify the indent
by Zong Li
· Wed Sep 01 15:01:43 2021 +0800
ec34849
board: sifive: use ccache driver instead of helper function
by Zong Li
· Wed Sep 01 15:01:42 2021 +0800
dab3e8e
board: sifive: Add an interface to get PCB revision
by Zong Li
· Wed Jun 30 23:23:48 2021 +0800
7f33743
riscv: cpu: fu740: Add support for cpu fu740
by Green Wan
· Thu May 27 06:52:07 2021 -0700
614b1d8
riscv: Split SiFive CLINT support between SPL and U-Boot proper
by Bin Meng
· Tue May 11 20:04:12 2021 +0800
d62063d
lmb: move CONFIG_LMB in Kconfig
by Patrick Delaunay
· Wed Mar 10 10:16:25 2021 +0100
23caf66
riscv: assembler versions of memcpy, memmove, memset
by Heinrich Schuchardt
· Sat Mar 27 12:37:04 2021 +0100
440b77f
riscv: Change phys_addr_t and phys_size_t to 64-bit
by Bin Meng
· Sun Jan 31 20:36:04 2021 +0800
a235d43
riscv: Add DMA 64-bit address support
by Padmarao Begari
· Fri Jan 15 08:20:35 2021 +0530
b75b15b
dm: treewide: Rename ..._platdata variables to just ..._plat
by Simon Glass
· Thu Dec 03 16:55:23 2020 -0700
ff184fe
riscv: Use a valid bit to ignore already-pending IPIs
by Sean Anderson
· Mon Sep 21 07:51:37 2020 -0400
87e6ce5
riscv: Rework Andes PLMT as a UCLASS_TIMER driver
by Sean Anderson
· Mon Sep 28 10:52:24 2020 -0400
6e7eb46
riscv: define function set_gd()
by Heinrich Schuchardt
· Thu Sep 10 07:47:39 2020 +0200
95492ae
cmd: provide command sbi
by Heinrich Schuchardt
· Thu Aug 20 19:43:39 2020 +0200
2b2d9c4
riscv: sifive/fu540: spl: Rename soc_spl_init()
by Bin Meng
· Sun Aug 02 23:09:03 2020 -0700
63dcfcb
riscv: Call spl_board_init_f() in the generic SPL board_init_f()
by Bin Meng
· Sun Aug 02 23:09:01 2020 -0700
e1ff6eb
sifive: reset: add DM based reset driver for SiFive SoC's
by Sagar Shrikant Kadam
· Wed Jul 29 02:36:13 2020 -0700
90fa4e9
Merge branch 'next'
by Tom Rini
· Mon Jul 06 15:46:38 2020 -0400
8a52128
riscv: sifive: fu540: enable all cache ways from U-Boot proper
by Pragnesh Patel
· Fri May 29 12:14:51 2020 +0530
7f4b666
riscv: Add option to support RISC-V privileged spec 1.9
by Sean Anderson
· Wed Jun 24 06:41:19 2020 -0400
b1d0cb3
riscv: Clean up IPI initialization code
by Sean Anderson
· Wed Jun 24 06:41:18 2020 -0400
5aa0074
riscv: Add headers for asm/global_data.h
by Sean Anderson
· Wed Jun 24 06:41:16 2020 -0400
0961ae8
bdinfo: riscv: Use generic bd_info
by Simon Glass
· Sun May 10 14:16:26 2020 -0600
b391ead
riscv: sbi: Remove sbi_spec_version
by Bin Meng
· Wed May 27 02:04:52 2020 -0700
e00653c
riscv: sifive: fu540: add SPL configuration
by Pragnesh Patel
· Fri May 29 11:33:35 2020 +0530
25269c0
riscv: cpu: fu540: Add support for cpu fu540
by Pragnesh Patel
· Fri May 29 11:33:34 2020 +0530
a7edd07
riscv: Move all SMP related SBI calls to SBI_v01
by Atish Patra
· Tue Apr 21 14:51:57 2020 -0700
4dcacfc
common: Drop linux/bitops.h from common header
by Simon Glass
· Sun May 10 11:40:13 2020 -0600
111b804
riscv: Provide a mechanism to fix DT for reserved memory
by Atish Patra
· Tue Apr 21 11:15:01 2020 -0700
b161f90
riscv: Introduce SPL_SMP Kconfig option for U-Boot SPL
by Bin Meng
· Thu Apr 16 08:09:30 2020 -0700
f7e6d33
riscv: Implement new SBI v0.2 extensions
by Bin Meng
· Mon Mar 09 19:35:31 2020 -0700
887d809
riscv: Introduce a new config for SBI v0.1
by Bin Meng
· Mon Mar 09 19:35:30 2020 -0700
c20421b
riscv: Add SBI v0.2 extension definitions
by Bin Meng
· Mon Mar 09 19:35:29 2020 -0700
ee3bcd0
riscv: Add basic support for SBI v0.2
by Bin Meng
· Mon Mar 09 19:35:28 2020 -0700
9da11d1
riscv: Mark existing SBI as v0.1 SBI
by Bin Meng
· Mon Mar 09 19:35:27 2020 -0700
ad76cd4
riscv: Fix sbi_remote_sfence_vma{,_asid}
by Bin Meng
· Fri Mar 06 00:44:16 2020 -0800
6373a17
dma-mapping: move dma_map_(un)single() to <linux/dma-mapping.h>
by Masahiro Yamada
· Fri Feb 14 16:40:19 2020 +0900
05a5dba
dma-mapping: fix the prototype of dma_unmap_single()
by Masahiro Yamada
· Fri Feb 14 16:40:18 2020 +0900
7167d67
dma-mapping: fix the prototype of dma_map_single()
by Masahiro Yamada
· Fri Feb 14 16:40:17 2020 +0900
4a81a21
asm: dma-mapping.h: Fix dma mapping functions
by Vignesh Raghavendra
· Thu Jan 16 14:23:45 2020 +0530
c308e01
riscv: add option to wait for ack from secondary harts in smp functions
by Lukas Auer
· Sun Dec 08 23:28:51 2019 +0100
211be3b
gpio: sifive: add support for DM based gpio driver for FU540-SoC
by Sagar Shrikant Kadam
· Tue Oct 01 10:00:46 2019 -0700
396f0bd
riscv: add SPL support
by Lukas Auer
· Wed Aug 21 21:14:45 2019 +0200
6134659
riscv: add run mode configuration for SPL
by Lukas Auer
· Wed Aug 21 21:14:43 2019 +0200
f942636
riscv: Access CSRs using CSR numbers
by Bin Meng
· Wed Jul 10 23:43:13 2019 -0700
a27264c
riscv: Sync csr.h with Linux kernel v5.2
by Bin Meng
· Wed Jul 10 23:43:12 2019 -0700
9cce6f7
env: Drop environment.h header file where not needed
by Simon Glass
· Thu Aug 01 09:47:12 2019 -0600
e5e6c36
riscv: Introduce CONFIG_XIP to support booting from flash
by Rick Chen
· Tue Apr 30 13:49:33 2019 +0800
7376677
riscv: Add a SYSCON driver for Andestech's PLMT
by Rick Chen
· Tue Apr 02 15:56:40 2019 +0800
6df4ed0
riscv: Add a SYSCON driver for Andestech's PLIC
by Rick Chen
· Tue Apr 02 15:56:39 2019 +0800
a359665
riscv: add support for multi-hart systems
by Lukas Auer
· Sun Mar 17 19:28:37 2019 +0100
9c03845
riscv: import the supervisor binary interface header file
by Lukas Auer
· Sun Mar 17 19:28:33 2019 +0100
83d573d
riscv: add infrastructure for calling functions on other harts
by Lukas Auer
· Sun Mar 17 19:28:32 2019 +0100
818d49a
riscv: Enable CONFIG_SYS_BOOT_RAMDISK_HIGH for using initrd
by Anup Patel
· Mon Feb 25 08:15:33 2019 +0000
6f07f45
riscv: Add place-holder asm/arch/clk.h for driver compilation
by Anup Patel
· Mon Feb 25 08:14:24 2019 +0000
928452a
riscv: Add asm/dma-mapping.h for DMA mappings
by Anup Patel
· Mon Feb 25 08:14:17 2019 +0000
89681a7
riscv: Save boot hart id to the global data
by Bin Meng
· Wed Dec 12 06:12:45 2018 -0800
9e9e6fe
riscv: Add indirect stringification to csr_xxx ops
by Bin Meng
· Wed Dec 12 06:12:39 2018 -0800
731e2d4
riscv: Add exception codes for xcause register
by Bin Meng
· Wed Dec 12 06:12:37 2018 -0800
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