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git01.mediatek.com / filogic / uboot / 5931e5aa70cfc5acfc237e72c850d6bb982c7233 / arch / riscv
  1. bb721de Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into next by Tom Rini · Tue Jan 05 22:34:43 2021 -0500
  2. e6256ce Merge tag 'v2021.01-rc5' into next by Tom Rini · Tue Jan 05 16:20:26 2021 -0500
  3. 65130cd dm: Rename DM_GET_DRIVER() to DM_DRIVER_GET() by Simon Glass · Mon Dec 28 20:34:56 2020 -0700
  4. 2ddd3e0 riscv: Add device tree bindings for SPI by Sean Anderson · Fri Oct 16 18:57:54 2020 -0400
  5. fd9571a spi: dw: Add SoC-specific compatible strings by Sean Anderson · Fri Oct 16 18:57:50 2020 -0400
  6. dd5d79b riscv: Complete efi header for RV32/64 by Leo Yu-Chi Liang · Mon Nov 16 17:07:41 2020 +0800
  7. b68402d riscv: Fix efi header size for RV32 by Leo Yu-Chi Liang · Thu Nov 12 10:09:52 2020 +0800
  8. fa36696 riscv: Fix efi header for RV32 by Atish Patra · Tue Oct 13 12:23:31 2020 -0700
  9. b881ba8 riscv: reset after crash by Heinrich Schuchardt · Wed Dec 02 14:36:26 2020 +0100
  10. 4b96c88 riscv: fix the wrong swap value register by Brad Kim · Fri Nov 13 20:47:51 2020 +0900
  11. b75b15b dm: treewide: Rename ..._platdata variables to just ..._plat by Simon Glass · Thu Dec 03 16:55:23 2020 -0700
  12. 4f1b444 riscv: sifive/fu540: kconfig: Enable support for Opencores I2C controller by Pragnesh Patel · Sat Nov 14 14:42:35 2020 +0530
  13. 2dc5984 riscv: fu540: dts: Correct reg size of clint node by Pragnesh Patel · Tue Oct 20 11:03:02 2020 +0530
  14. 52a1db7 riscv: Move timer portions of SiFive CLINT to drivers/timer by Sean Anderson · Sun Oct 25 21:46:58 2020 -0400
  15. 5a23865 timer: Add _TIMER suffix to Andes PLMT Kconfig by Sean Anderson · Sun Oct 25 21:46:57 2020 -0400
  16. 5abf1f3 riscv: Move Andes PLMT driver to drivers/timer by Sean Anderson · Sun Oct 25 21:46:56 2020 -0400
  17. d1b3321 riscv: k210: Reduce DMA block size by Sean Anderson · Mon Oct 12 14:18:15 2020 -0400
  18. 584a5ee riscv: Only enable OF_BOARD_FIXUP for S-Mode by Sean Anderson · Sat Sep 05 09:22:11 2020 -0400
  19. 947fc2d timer: Return count from timer_ops.get_count by Sean Anderson · Wed Oct 07 14:37:44 2020 -0400
  20. 36d38fd riscv: add DT binding for BOOT button on Maix board by Heinrich Schuchardt · Mon Sep 14 11:02:05 2020 -0400
  21. 6870556 riscv: Add pinmux and gpio bindings for Kendryte K210 by Sean Anderson · Mon Sep 14 11:02:04 2020 -0400
  22. 38ae92e Merge branch 'next' by Tom Rini · Mon Oct 05 13:05:46 2020 -0400
  23. 5bdad9f riscv: Add some comments to start.S by Sean Anderson · Mon Sep 21 07:51:41 2020 -0400
  24. 2c4c7d1 riscv: Ensure gp is NULL or points to valid data by Sean Anderson · Mon Sep 21 07:51:40 2020 -0400
  25. 934b24a riscv: Consolidate fences into AMOs for available_harts_lock by Sean Anderson · Mon Sep 21 07:51:39 2020 -0400
  26. dd1cd70 riscv: Clear pending IPIs on initialization by Sean Anderson · Mon Sep 21 07:51:38 2020 -0400
  27. ff184fe riscv: Use a valid bit to ignore already-pending IPIs by Sean Anderson · Mon Sep 21 07:51:37 2020 -0400
  28. cfb0809 riscv: Match memory barriers between send_ipi_many and handle_ipi by Sean Anderson · Mon Sep 21 07:51:36 2020 -0400
  29. e8de08b Revert "riscv: Clear pending interrupts before enabling IPIs" by Sean Anderson · Mon Sep 21 07:51:35 2020 -0400
  30. 3d999194 riscv: Update SiFive device tree for new CLINT driver by Sean Anderson · Mon Sep 28 10:52:29 2020 -0400
  31. c6d0ef8 riscv: Update Kendryte device tree for new CLINT driver by Sean Anderson · Mon Sep 28 10:52:28 2020 -0400
  32. 272ab20 riscv: Rework Sifive CLINT as UCLASS_TIMER driver by Sean Anderson · Mon Sep 28 10:52:26 2020 -0400
  33. 28bfc32 riscv: Clean up initialization in Andes PLIC by Sean Anderson · Mon Sep 28 10:52:25 2020 -0400
  34. 87e6ce5 riscv: Rework Andes PLMT as a UCLASS_TIMER driver by Sean Anderson · Mon Sep 28 10:52:24 2020 -0400
  35. 9baaaef riscv: Rework riscv timer driver to only support S-mode by Sean Anderson · Mon Sep 28 10:52:21 2020 -0400
  36. fbef54d riscv: restore global data pointer in trap handler by Heinrich Schuchardt · Sat Sep 26 07:50:36 2020 +0200
  37. 646f8c6 fdtdec: optionally add property no-map to created reserved memory node by Etienne Carriere · Thu Sep 10 10:49:59 2020 +0200
  38. 6e7eb46 riscv: define function set_gd() by Heinrich Schuchardt · Thu Sep 10 07:47:39 2020 +0200
  39. 95492ae cmd: provide command sbi by Heinrich Schuchardt · Thu Aug 20 19:43:39 2020 +0200
  40. c78eef7 riscv: fix building with CONFIG_SPL_SMP=n by Heinrich Schuchardt · Sat Aug 15 09:49:26 2020 +0200
  41. 54bcf26 riscv: fu540: Use correct API to get L2 cache controller base address by Bin Meng · Tue Aug 18 01:09:20 2020 -0700
  42. 77efe24 riscv: additional crash information by Heinrich Schuchardt · Sat Aug 01 15:15:39 2020 +0000
  43. 03de50e riscv: sifive: fu540: redundant initialization by Heinrich Schuchardt · Mon Aug 03 23:09:49 2020 +0200
  44. d2014d1 riscv: remove redundant logical constraint. by Heinrich Schuchardt · Mon Aug 03 23:33:42 2020 +0200
  45. 6b15551 riscv: sifive/fu540: kconfig: Move FU540 driver related options to the SoC level by Bin Meng · Sun Aug 02 23:09:04 2020 -0700
  46. 2b2d9c4 riscv: sifive/fu540: spl: Rename soc_spl_init() by Bin Meng · Sun Aug 02 23:09:03 2020 -0700
  47. 63dcfcb riscv: Call spl_board_init_f() in the generic SPL board_init_f() by Bin Meng · Sun Aug 02 23:09:01 2020 -0700
  48. e1ff6eb sifive: reset: add DM based reset driver for SiFive SoC's by Sagar Shrikant Kadam · Wed Jul 29 02:36:13 2020 -0700
  49. b0357f4 fu540: dtsi: add reset producer and consumer entries by Sagar Shrikant Kadam · Wed Jul 29 02:36:12 2020 -0700
  50. a9e7ec5 riscv: dts: hifive-unleashed-a00: Make memory node available to SPL by Bin Meng · Sun Jul 19 23:06:34 2020 -0700
  51. 4e3ba2a riscv: Fix linking error when building u-boot-spl with no SMP support by Leo Yu-Chi Liang · Mon Jun 29 16:27:28 2020 +0800
  52. 3af8678 Revert "riscv: Allow use of reset drivers" by Bin Meng · Sun Jul 19 20:06:45 2020 -0700
  53. e70ef90 env: Enable SPI flash env for SiFive FU540 by Jagan Teki · Wed Jul 15 15:39:00 2020 +0530
  54. 05fb96d sifive: fu540: Add Booting from SPI by Jagan Teki · Wed Jul 15 15:38:59 2020 +0530
  55. 257875d riscv: Make SiFive HiFive Unleashed board boot again by Bin Meng · Sun Jul 19 23:17:07 2020 -0700
  56. 90fa4e9 Merge branch 'next' by Tom Rini · Mon Jul 06 15:46:38 2020 -0400
  57. 8cfbea0 riscv: use log functions in fdt_fixup by Heinrich Schuchardt · Tue Jun 30 11:30:59 2020 +0200
  58. 8a52128 riscv: sifive: fu540: enable all cache ways from U-Boot proper by Pragnesh Patel · Fri May 29 12:14:51 2020 +0530
  59. 491734f riscv: Use optimized version of fdtdec_get_addr_size_no_parent by Atish Patra · Wed Jun 24 14:56:15 2020 -0700
  60. f0947db riscv: Do not return error if reserved node already exists by Atish Patra · Wed Jun 24 14:56:14 2020 -0700
  61. c71f100 riscv: Do not build reset.c if SYSRESET is on by Bin Meng · Mon Jun 22 22:29:44 2020 -0700
  62. 2bdcd05 riscv: Enable CONFIG_OF_BOARD_FIXUP by default for OF_SEPARATE by Bin Meng · Thu Jun 25 18:16:08 2020 -0700
  63. 7a36bd8 riscv: Expand the DT size before copy reserved memory node by Bin Meng · Thu Jun 25 18:16:07 2020 -0700
  64. 77073f4 riscv: Avoid the reserved memory fixup if src and dst point to the same place by Bin Meng · Thu Jun 25 18:16:06 2020 -0700
  65. 3961e14 riscv: fu540: dts: Correct reg size of otp and dmc nodes by Bin Meng · Mon Jun 08 20:28:26 2020 -0700
  66. e3870c8 riscv: fu540: dts: Remove the unnecessary space in the cpu2_intc node by Bin Meng · Mon Jun 08 20:28:25 2020 -0700
  67. d2b7f84 riscv: dts: hifive-unleashed-a00: add cpu aliases by Sagar Shrikant Kadam · Sun Jun 28 07:45:00 2020 -0700
  68. edc32ab riscv: Add Sipeed Maix support by Sean Anderson · Wed Jun 24 06:41:25 2020 -0400
  69. d11b582 riscv: Add device tree for K210 and Sipeed Maix BitM by Sean Anderson · Wed Jun 24 06:41:23 2020 -0400
  70. 35e14fb riscv: Allow use of reset drivers by Sean Anderson · Wed Jun 24 06:41:20 2020 -0400
  71. 7f4b666 riscv: Add option to support RISC-V privileged spec 1.9 by Sean Anderson · Wed Jun 24 06:41:19 2020 -0400
  72. b1d0cb3 riscv: Clean up IPI initialization code by Sean Anderson · Wed Jun 24 06:41:18 2020 -0400
  73. 84df2e1 riscv: Clear pending interrupts before enabling IPIs by Sean Anderson · Wed Jun 24 06:41:17 2020 -0400
  74. 5aa0074 riscv: Add headers for asm/global_data.h by Sean Anderson · Wed Jun 24 06:41:16 2020 -0400
  75. 0961ae8 bdinfo: riscv: Use generic bd_info by Simon Glass · Sun May 10 14:16:26 2020 -0600
  76. e622c74 riscv: sbi: Move sbi_probe_extension() out of CONFIG_SBI_V01 by Bin Meng · Wed May 27 02:04:53 2020 -0700
  77. b391ead riscv: sbi: Remove sbi_spec_version by Bin Meng · Wed May 27 02:04:52 2020 -0700
  78. e00653c riscv: sifive: fu540: add SPL configuration by Pragnesh Patel · Fri May 29 11:33:35 2020 +0530
  79. 25269c0 riscv: cpu: fu540: Add support for cpu fu540 by Pragnesh Patel · Fri May 29 11:33:34 2020 +0530
  80. 01ec498 riscv: dts: sifive: Sync hifive-unleashed-a00 dts from linux by Pragnesh Patel · Fri May 29 11:33:33 2020 +0530
  81. bb337f9 riscv: sifive: dts: fu540: set ethernet clock rate by Pragnesh Patel · Fri May 29 11:33:32 2020 +0530
  82. 45ffc91 riscv: sifive: dts: fu540: add U-Boot dmc node by Pragnesh Patel · Fri May 29 11:33:28 2020 +0530
  83. 8f4a403 sifive: dts: fu540: Add DDR controller and phy register settings by Pragnesh Patel · Fri May 29 11:33:27 2020 +0530
  84. b65f19f riscv: sifive: dts: fu540: Add board -u-boot.dtsi files by Pragnesh Patel · Fri May 29 11:33:25 2020 +0530
  85. 45b4ad9d riscv: Add _image_binary_end for SPL by Pragnesh Patel · Fri May 29 11:33:23 2020 +0530
  86. 2a449a3 riscv: sifive: fu540: Use OTP DM driver for serial environment variable by Pragnesh Patel · Fri May 29 11:33:22 2020 +0530
  87. a7edd07 riscv: Move all SMP related SBI calls to SBI_v01 by Atish Patra · Tue Apr 21 14:51:57 2020 -0700
  88. 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · Sun May 10 11:40:13 2020 -0600
  89. 0f2af88 common: Drop log.h from common header by Simon Glass · Sun May 10 11:40:05 2020 -0600
  90. ed38aef command: Remove the cmd_tbl_t typedef by Simon Glass · Sun May 10 11:40:03 2020 -0600
  91. 9758973 common: Drop init.h from common header by Simon Glass · Sun May 10 11:40:02 2020 -0600
  92. 2dc9c34 common: Drop image.h from common header by Simon Glass · Sun May 10 11:40:01 2020 -0600
  93. 1ea9789 common: Drop bootstage.h from common header by Simon Glass · Sun May 10 11:40:00 2020 -0600
  94. 274e0b0 common: Drop net.h from common header by Simon Glass · Sun May 10 11:39:56 2020 -0600
  95. 76c8522 sifive: fu540: Enable spi-nor flash support by Jagan Teki · Wed Apr 29 21:03:53 2020 +0530
  96. 0c2964b riscv: dts: hifive-unleashed-a00: Add -u-boot.dtsi by Jagan Teki · Thu Apr 23 22:30:56 2020 +0530
  97. 82ed8ef riscv: Move all fdt fixups together by Atish Patra · Tue Apr 21 11:15:04 2020 -0700
  98. 5fbac33 riscv: Copy the reserved-memory nodes to final DT by Atish Patra · Tue Apr 21 11:15:03 2020 -0700
  99. 7379192 riscv: Setup reserved-memory node for FU540 by Atish Patra · Tue Apr 21 11:15:02 2020 -0700
  100. 111b804 riscv: Provide a mechanism to fix DT for reserved memory by Atish Patra · Tue Apr 21 11:15:01 2020 -0700