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git01.mediatek.com
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filogic
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uboot
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55f51d92f8c06efba5a26734c748c1093a748e64
/
drivers
/
clk
/
rockchip
/
clk_rk3368.c
4fbb6c2
rockchip: clock: update sysreset driver binding
by Kever Yang
· Fri Nov 03 15:16:13 2017 +0800
81e1042
treewide: replace with error() with pr_err()
by Masahiro Yamada
· Sat Sep 16 14:10:41 2017 +0900
4771ba6
rockchip: clk: Add rk3368 SARADC clock support
by David Wu
· Wed Sep 20 14:37:50 2017 +0800
5355999
rockchip: clk: rk3368: Convert to livetree
by Philipp Tomsich
· Mon Sep 11 22:04:18 2017 +0200
1b1fe41
dtoc: Add support for 32 or 64-bit addresses
by Simon Glass
· Tue Aug 29 14:15:50 2017 -0600
f20995b
rockchip: clk: remove RATE_TO_DIV
by Kever Yang
· Thu Jul 27 12:54:02 2017 +0800
b4fb55f
rockchip: clk: rk3368: add support for configuring the SPI clocks
by Philipp Tomsich
· Tue Jul 25 16:48:16 2017 +0200
83a5d2c
rockchip: clk: rk3368: mark 'priv' __maybe_unused in rk3368_clk_set_rate()
by Philipp Tomsich
· Wed Jul 05 12:11:58 2017 +0200
a249f10
rockchip: clk: rk3368: add support for GMAC (SLCK_MAC) clock
by Philipp Tomsich
· Fri Jul 14 19:57:39 2017 +0200
c23a993
rockchip: clk: rk3368: support configuring the DRAM PLL (from TPL)
by Philipp Tomsich
· Wed Jul 05 11:55:23 2017 +0200
fbf07a5
rockchip: clk: rk3368: implement MMC/SD clock reparenting
by Philipp Tomsich
· Tue Jul 04 14:49:38 2017 +0200
313b2da
rockchip: clk: rk3368: implement DPLL (DRAM PLL) support
by Philipp Tomsich
· Fri Jun 23 00:01:10 2017 +0200
415ff7e
rockchip: clk: rk3368: do not change CPLL/GPLL before returning to BROM
by Philipp Tomsich
· Thu Jun 22 23:53:44 2017 +0200
79aa1ab
rockchip: clk: rk3368: support OF_PLATDATA for the RK3368 clk driver
by Philipp Tomsich
· Thu Jun 22 23:51:37 2017 +0200
34b7613
rockchip: clk: rk3368: implement bandwidth adjust for PLLs
by Philipp Tomsich
· Thu Jun 22 23:47:11 2017 +0200
ea825a3
rockchip: clk: rk3368: use correct (i.e. 'rk3368_clk_priv') structure for auto-alloc
by Philipp Tomsich
· Tue Jul 11 20:59:45 2017 +0200
b9909aa
rockchip: rk3368: Add clock driver
by Andy Yan
· Mon May 15 17:49:56 2017 +0800